applied sciences Article
Two Dimensional Parity Check with Variable Length Error Detection Code for the Non-Volatile Memory of Smart Data Cihun-Siyong Alex Gong 1,2,3, *,† ID , Yung-Chang Chang 4,† , Li-Ren Huang 4 , Chih-Jen Yang 4 , Kung-Ming Ji 4 , Kuen-Long Lu 4 and Jian-Chiun Liou 5, * 1 2 3 4
5
* †
Department of Electrical Engineering, College of Engineering, Chang Gung University, Taoyuan 33302, Taiwan Portable Energy System Group, Green Technology Research Center, College of Engineering, Chang Gung University, Taoyuan 33302, Taiwan Department of Ophthalmology, Chang Gung Memorial Hospital, Linkou Branch, Taoyuan 33305, Taiwan Information and Communications Research Laboratories, Industrial Technology Research Institute, Hsinchu 31040, Taiwan;
[email protected] (Y.-C.C.);
[email protected] (L.-R.H.);
[email protected] (C.-J.Y.);
[email protected] (K.-M.J.);
[email protected] (K.-L.L.) School of Biomedical Engineering, College of Biomedical Engineering, Taipei Medical University, Taipei 11031, Taiwan Correspondence:
[email protected] (C.-S.A.G.);
[email protected] (J.-C.L.) These authors contributed equally to this work.
Received: 18 June 2018; Accepted: 21 July 2018; Published: 24 July 2018
Abstract: This paper proposes a novel technology of memory protection for the Non-Volatile Memory (NVM), applied to smart sensors and smart data. Based on the asymmetry of failure rate between the statuses of bit-0 and bit-1 in the non-volatile memory, as a result of the pollution of the radiation of cosmic ray, a two-dimensional parity with variable length error detection code (2D-VLEDC) for memory protection is proposed. 2D-VLEDC has the feature of variable length of redundant bits varied with content of data word in the NVM. The experimental results show that the same error detection quality could be achieved with a 30% redundancy improvement by applying the proposed 2D-VLEDC. The proposed design is particularly suitable for the use of safety-related fields, such as the automotive electronics and industrial non-volatile memories involved in the industrial automation. Keywords: memory; protection; ECC; parity; non-volatile; variable length; data integrity; smart sensor
1. Introduction It has been well known that non-volatile memory (NVM) plays an important role in various systems with the embedded or external structures. For smart data and smart sensor applications, data integrity is of primary importance. From automotive to aerospace fields, research continuously discusses the topic of non-volatile memory’s failure models. Experimental results show that the erased and programed cells have different threshold voltage (VTH ) shifts [1]. For the programed cells, VTH decreases when the floating gate is hit by an ion, resulting in a reduction of the floating gate stored negative charge. On the contrary, in the case of erased cells, no threshold variation is observed. Figure 1 shows one of the results in [1]. Read only memory (ROM) is a semiconductor memory. Its characteristics is its contents cannot be changed or erased once they have been stored in it. Moreover, its contents will not disappear in spite of power-off. It can be either Electrically-Erasable Programmable Read-Only Memory (EEPROM) or NOR FLASH in implementation. In this study, any floating-gate
Appl. Sci. 2018, 8, 1211; doi:10.3390/app8081211
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Programmable Programmable Read-Only Read-Only Memory Memory (EEPROM) (EEPROM) or or NOR NOR FLASH FLASH in in implementation. implementation. In In this this study, study, any any floating-gate floating-gate ROMs ROMs can can match match the the characteristics characteristics in in Figure Figure 1. 1. Two Two ROM ROM devices devices can can be be chosen chosen for for verification—the AT24CS of Atmel, and the S25FL128S of CYPRESS. They are popular and easily verification—the AT24CS of Atmel,inand the1.S25FL128S CYPRESS. arefor popular and easily ROMs can match the characteristics Figure Two ROMof devices can beThey chosen verification—the available. available. AT24CS of Atmel, and the S25FL128S of CYPRESS. They are popular and easily available.
Figure Figure 1. 1. Cumulative Cumulative distributions distributions of of threshold threshold voltages voltages for for exposed exposed cells cells [1]. [1]. threshold voltages for exposed cells [1].
According specifies how reading error is caused by the shifted V According to to Reference Reference [2], [2], Figure Figure 222 specifies specifies how how reading reading error error is iscaused causedby bythe theshifted shiftedV VTH TH According to Reference [2], Figure TH (ΔV TH When the cell’s V TH lower than read voltage (V read read error happens because status “0” (ΔV TH). ). When the cell’s V TH is is lower than read voltage (V read), ), read error happens because status “0” (∆VTH ). When the cell’s VTH is lower than read voltage (Vread ), read error happens because status “0” is have this side-effect, because the ΔV is read read as as “1”. “1”. Status Status “1” “1” does does not not have have this this side-effect, side-effect,because becausethe the∆V ΔVTH TH of of status status “1” “1” is is almost almost zero zero is read as “1”. Status “1” does not TH of status “1” is almost zero according to the conclusion in Reference [1]. Obviously, the error rates caused by radiation are according to the conclusion in Reference [1]. Obviously, the error rates caused by radiation are according to the conclusion in Reference [1]. Obviously, the error rates caused by radiation are different different between erased cells (status “1”), and programmed cells (status “0”). In Reference [3], a different between erased cells (status “1”), and programmed cells (status “0”). In Reference [3], between erased cells (status “1”), and programmed cells (status “0”). In Reference [3], a dynamic reada dynamic read reference voltage is used in reading data from non-volatile memory cells. The read dynamic voltage read reference is used in reading data from non-volatile memory cells. The read reference is used voltage in reading data from non-volatile memory cells. The read reference voltage reference voltage is calibrated. An Error Checking and Correction (ECC) algorithm is performed to reference voltage is calibrated. An Error Checking and Correction (ECC) algorithm is performed to is calibrated. An Error Checking and Correction (ECC) algorithm is performed to identify whether identify whether errors exist in the data for read using the initial read reference voltage level. If errors identify whether errors exist in the data for read using the initial read reference voltage level. If errors errors exist in the data for read using the initial read reference voltage level. If errors in the data are in are when value is to adjust the read in the the data datawhen are identified identified when read, read, aa pre-determined pre-determined is retrieved retrieved to read adjust the initial initial read identified read, a pre-determined value is retrievedvalue to adjust the initial reference voltage reference voltage level to aa new read reference voltage level. reference voltage level to new read reference voltage level. level to a new read reference voltage level.
error due to shifted voltage of V TH Figure [2]. Figure2. 2. The The situation situation of of reading readingerror errordue dueto toshifted shiftedvoltage voltageof ofV VTH TH [2] [2]..
In novel technology Length Error Detection Code” In this this paper, paper, aaa novel novel technology technology called called “Variable “Variable Length Length Error Error Detection Detection Code” Code” (VLEDC) (VLEDC) for for In this paper, called “Variable (VLEDC) for the Non-Volatile Memory (NVM) protection is proposed. Although there have been some methods the Non-Volatile Non-Volatile Memory Memory (NVM) (NVM) protection protection is is proposed. proposed. Although Although there there have have been been some some methods methods the about variable length coding of memory protection [4,5], they were developed without considering about variable length coding of memory protection [4,5], they were developed without considering about variable length coding of memory protection [4,5], they were developed without considering the difference between status “1” and status “0” in the memory content. the error error rate rate difference difference between between status status “1” “1” and and status status “0” “0” in in the thememory memory content. content. Combined Combined with with the error rate Combined with two-dimensional parity check architecture, 2D-VLEDC can aa high error two-dimensionalparity paritycheck check architecture, the proposed proposed 2D-VLEDC can achieve achieve high error two-dimensional architecture, the the proposed 2D-VLEDC can achieve a high error coverage coverage with cost with traditional ECC techniques, selectivity coverage with significant significant cost reduction. reduction. Compared Compared with the theECC traditional ECCselectivity techniques, selectivity with significant cost reduction. Compared with the traditional techniques, can be made
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canour bedesign made to in allow our design user to choose either ECCaccording or paritytocheck according to the in a user to to allow chooseaeither ECC or parity check the contents stored in contents storeddecreasing in ROM, thereby decreasing the required redundant bits significantly. ROM, thereby the required redundant bits significantly. This paper was organized as follows: In Section 2, how the 2D-VLEDC works and is applied to NVM is described. Section 3 discusses the experiments on performance comparison of other methods with our our 2D-VLEDC. 2D-VLEDC. Concluding Concluding remarks remarks are are given given in in Section Section4. 4. of memory protection with 2. Proposed Method Method 2. Proposed Before we first first introduce parity (2D-parity) (2D-parity) check. check. Before discussing discussing 2D-VLEDC, 2D-VLEDC, we introduce aa two-dimensional two-dimensional parity Figure 32 (address (address 0~19, each address address has has 32 Figure 33 describes describes aa ROM ROM whose whose physical physical size sizeisis20 20× × 32 0~19, each 32 bits) bits) bits bits as The addresses addresses from from 0 0 to as an an example. example. The to 16 16 contain contain the the program program codes codes that that Central Central Processing Processing Unit Unit (CPU) The C1 is Y-axis (CPU) runs runs with. with. It It is is called called as as data data area. area. The C1 column column is Y-axis 1-bit 1-bit parity parity check check of of data data word word at at relative parity coding coding relative address. address. For For example, example, green green square square (address (address 0) 0) in in the the Figure Figure 33 specifies specifies an an even even parity scheme. In the the address address 0, 0, only only bit bit (0, (0, 30) 30) from from bit bit 0 scheme. In 0 to to 31 31 equals equals to to 1, 1, so so bit bit (0, (0, C1) C1) equals equals to to 1. 1. In In the the same way, address 17 is X-axis 1-bit even parity bit for column bits of the program codes. As shown same way, address 17 is X-axis 1-bit even parity bit for column bits of the program codes. As shown as blue square in the Figure 3, there are totally 15 ones in the column 1 from address 0 to address 16, so the (17, 1) equals to 1 according according to to even even parity parity rule. rule. To the 2D-parity 2D-parityin inaatypical typicalmemory, memory,the theY-axis Y-axis parity bits (address stored in To apply the parity bits (address 18)18) are are stored in the the address behind program codes (address to 16), X-axis parity (address shown address behind the the program codes (address 0 to0 16), andand X-axis parity (address 17).17). AsAs shown in in Figure 3, the Y-axis (column C1) bits are stored at the address 18 as presented in the red square. Figure 3, the Y-axis (column C1) bits are stored at the address 18 as presented in the red square. The The remaining in the address filled with Thestorage storageofofX-axis X-axisand andY-axis Y-axis is is called as remaining bits bits in the address 18 18 areare filled with 0. 0.The signature area. In addition, as shown in address 19, the same 2D-parity can be applied to the signature signature area. addition, area again to implement self-checking-like scheme to improve the fault tolerant quality. self-checking-like scheme to improve the fault tolerant quality.
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19
0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 0 1 1 1 1 0
1 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 1 1 0 1
2 0 1 1 1 1 1 1 1 1 1 1 1 1 1 0 1 1 1 1 0
3 0 1 0 1 1 1 1 1 0 1 1 1 1 0 0 0 0 0 1 1
4 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0
5 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 1 1
6 0 1 0 1 1 1 1 1 0 1 1 1 1 0 0 0 0 0 0 0
7 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 1 1
8 0 1 0 1 1 1 1 1 0 1 1 1 1 0 0 0 0 0 1 1
9 0 1 0 1 1 1 1 1 0 1 1 1 1 0 0 0 0 0 1 1
10 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 1 1
11 0 1 0 1 0 1 1 1 0 1 1 1 1 0 0 0 0 1 1 0
12 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0
13 0 1 0 1 1 1 1 1 0 1 1 1 1 0 0 0 0 0 0 0
14 0 1 0 1 1 1 1 1 0 1 1 1 1 0 0 0 0 0 0 0
15 0 1 0 1 1 1 1 1 0 1 1 1 0 0 0 0 0 1 1 0
16 0 1 0 1 1 1 1 1 0 1 1 1 1 0 0 0 0 0 1 1
17 0 1 1 1 1 1 0 1 1 1 1 1 1 1 1 1 1 1 1 0
18 0 1 0 1 1 1 1 1 0 1 1 1 1 0 0 0 0 0 0 0
19 0 1 0 1 1 1 1 1 0 1 1 1 1 0 0 1 0 1 0 1
20 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0
21 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0
22 0 1 0 1 1 1 1 1 0 1 1 1 1 0 1 0 0 1 0 1
23 0 1 0 1 1 1 1 1 0 1 1 1 1 0 0 1 0 1 0 1
24 0 1 0 1 1 1 1 1 0 1 1 1 1 0 0 0 0 0 0 0
25 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0
26 0 1 0 1 1 1 1 1 0 1 1 1 1 0 0 0 0 0 0 0
27 0 1 1 0 0 0 0 0 1 0 0 0 0 1 1 1 1 1 0 1
28 0 1 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0
29 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0
30 1 1 1 0 0 0 0 0 1 0 0 0 0 1 1 1 1 0 0 0
31 0 1 0 1 1 1 1 1 0 1 1 1 1 0 0 1 0 1 0 1
C1 1 0 1 1 0 1 0 1 1 1 1 1 0 0 0 1 1 1
Figure 3. 2D-parity check applied to non-volatile memory (NVM).
The 2D-parity single bitbit error in both datadata areaarea and signature area. area. Any The 2D-parity could coulddetect detectand andcorrect correct single error in both and signature 2-bit 2-bit errorerror couldcould be detected. However, the locating of two bits is not successful. For Any be detected. However, the locating of error two error bits is always not always successful. example, if there are two error bits in one data word, the X-axis shows no change of parity bit even For example, if there are two error bits in one data word, the X-axis shows no change of parity bit two of bitof changes in Y-axis parity are found⎯that is to is say, this this 2-bit2-bit errorerror can can be identified but but the even two bit changes in Y-axis parity are found—that to say, be identified location of error bit bit cannot be be found, resulting ininfailure error the location of error cannot found, resulting failuretotorecover recoverthem. them.As Asaa result, result, the the error handling capability is named as single error correction and double error detection (SECDED). handling capability is named as single error correction and double error detection (SECDED). To compare the undetected error rate of 2D-parity with ECC, a fault injection simulation was applied, as shown in Table 1. In this simulation, 1 to 4 errors were injected and all possible error
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4 ofwas 10 error rate of 2D-parity with ECC, a fault injection simulation applied, as shown in Table 1. In this simulation, 1 to 4 errors were injected and all possible error location location combinations in an 8 × 32 size of ROM were evaluated. In other words, for 4-errors fault combinations in an 8 × 32 size of ROM were evaluated. In other words, for 4-errors fault injection injection simulation, there are C (8 × 32, 4) operations including injecting fault, decoding, and simulation, there are C (8 × 32, 4) operations including injecting fault, decoding, and comparison in comparison in the simulation, where C means “combination”. Table 1 shows the results of fault the simulation, where C means “combination”. Table 1 shows the results of fault injection simulation injection simulation with 2D-parity and ECC. Undetected error rate equals to (undetected error with 2D-parity and ECC. Undetected error rate equals to (undetected error counts)/C (8 × 32, 4) × counts)/C (8 × 32, 4) × 100%. Table 1 show that 2D-parity and ECC can detect all errors from 1 to 3 100%. Table 1 show that 2D-parity and ECC can detect all errors from 1 to 3 errors’ fault injection. errors’ fault injection. In the 4 errors’ fault injection simulation, ECC has effectiveness better (twice) In the 4 errors’ fault injection simulation, ECC has effectiveness better (twice) than 2D-parity. The cost than 2D-parity. The cost overhead of 2D-parity equals to ((8 + 32)/(8 × 32)) × 100% = 15.625%. The cost overhead of 2D-parity equals to ((8 + 32)/(8 × 32)) × 100% = 15.625%. The cost of ECC equals to of ECC equals to ((7 × 8)/(8 × 32)) × 100% = 21.875%. 2D-parity overhead/ECC overhead = 71.43%. ((7 × 8)/(8 × 32)) × 100% = 21.875%. 2D-parity overhead/ECC overhead = 71.43%.
Table 1. Fault injection simulation of ROM size 8 × 32. Table 1. Fault injection simulation of ROM size 8 × 32.
No. of Injected Undetected Error of Error Checking and No. of Injected Undetected Error of Error Checking Error Correction (ECC) Error and Correction (ECC) 1 0 1 2 0 0 2 0 3 0 0 3 4 0.003% 4 0.003%
Undetected Error of 2D Undetected Error of Parity 2D Parity
0
0 0 0 0 0 0.007% 0.007%
One possible way to improve the error detection rate of 2D parity is to include ECC on data One possible way to improve the error detection rate of 2D parity is to include ECC on data word word to replace the X-axis parity. However, it induces significant increase in redundancy. Here an to replace the X-axis parity. However, it induces significant increase in redundancy. Here an idea of idea of variable length error detection code is proposed. The probability of read error between 1-to-0 variable length error detection code is proposed. The probability of read error between 1-to-0 and and 0-to-1 is different after NVM in the radiation. It was taken into account to select appropriate X0-to-1 is different after NVM in the radiation. It was taken into account to select appropriate X-axis axis redundancy. Figure 4 shows the concept of our VLEDC, the content of data word decides the redundancy. Figure 4 shows the concept of our VLEDC, the content of data word decides the method method of encoding with respective redundant bits. As a result, the length of redundant bits is of encoding with respective redundant bits. As a result, the length of redundant bits is variable for variable for each data word in NVM. each data word in NVM.
Figure 4. Length of redundant bits depends on the content of data word. Figure 4. Length of redundant bits depends on the content of data word.
Figure 5 shows the architecture of the proposed 2D-VLEDC, including: Filter, encoder, boot Figure 5 shows the architecture of includes the proposed 2D-VLEDC, including: Filter,technologies, encoder, boot checker and NVM modules. The encoder several known memory protection checker and NVM modules. The encoder includes several known memory protection technologies, like 1-bit parity and 7-bits ECC. Before encoding data word, filter module generates encoder-selecting like 1-bit parity andthe 7-bits Before encoding dataAword, filterrules module generates encoder-selecting signals by analyzing zeroECC. counts in the data word. few filter could be applied for the filter, signals by analyzing the zero counts in the data word. A few filter rules could be applied for of therule, filter, such as the number of zero count, the consecutive zero bits, and so on. These threshold values suchasasthe the number number of of zero count, the consecutive bits, andtosothe on.demands These threshold valuesinofthe rule, such “0” bits, could be adjustedzero according of reliability such as the number of “0” bits, could be adjusted according to the demands of reliability in the system. system.
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Figure 5. The architecture of the proposed two-dimensional parity with variable length error Figure 5. The architecture of the proposed two-dimensional parity with variable length error detection detection code (2D-VLEDC). code (2D-VLEDC).
Thesame sameas asthose those in in the the 2D-parity, The redundant bits bitsare arestored storedininthe thesignature signaturearea. area. 2D-parity, the generated redundant Figure66shows showsthat thatthe theredundant redundantbits bitsare arestored storedatatthe theaddresses addressesfrom fromNo. No.2121totoNo. No.2222asasmarked markedin Figure in red the box. red box. Address 20 stores the Y-axis bits.example, For example, theofbit-0 datainword in the the Address 20 stores the Y-axis parityparity bits. For the bit-0 dataofword the address address 20to is XOR equalall to bit-0 XORfrom all bit-0 from 0 address 0 to address 16 as presented in thebox. green box.isThat 20 is equal address to address 16 as presented in the green That even is even parity check for all bit-0 from address 0 to address 16. parity check for all bit-0 from address 0 to address 16. BeforeCPU CPUboots bootsup, up,Boot BootROM ROM checker checker module module first first performs performs the Before the boot boot ROM ROM checking. checking.Boot Boot ROMchecker checkermodule modulereads readsdata dataword, word, sends sends data data word word to ROM to filter filter module module to toperform performencoding encodingprocess process againand andfinally finallycompares comparesthe theredundant redundantbit bit in in the the NVM NVM with with re-calculated again re-calculated ones. ones. IfIfthe theresults resultsof ofthe the identical comparison are true, CPU will fetch instructions normally. If the results of the comparison identical comparison are true, CPU will fetch instructions normally. If the results of the comparison arefalse, false,Boot BootROM ROMchecker checkermodule modulewill willalarm alarm an an error error signal signal to to external external interface. are interface.
Figure 6. 2D-VLEDC applied in NVM. Figure 6. 2D-VLEDC applied in NVM.
3. Experiments 3. Experiments This section illustrates an experiment to evaluate the performance of the proposed 2D-VLEDC. This section illustrates an experiment to evaluate the performance of the proposed 2D-VLEDC. The performance comparison between other methods of memory protection and 2D-VLEDC are The performance comparison between other methods of memory protection and 2D-VLEDC are given. given. Table 2 shows the filer rule applied to the experiments. One-bit parity was applied to those Table 2 shows the filer rule applied to the experiments. One-bit parity was applied to those data words data words with less than half of content is “0”. The 7-bit ECC was applied to those data words with with less than half of content is “0”. The 7-bit ECC was applied to those data words with more than more than half of content is “1”. As shown in Table 2, the 1-bit parity is used when the number of “0” half of content is “1”. As shown in Table 2, the 1-bit parity is used when the number of “0” is 0–15 is 0–15 in an address date. On the other hand, a 7-bit ECC is applied to the system when the number inofan address date. On the other hand, a 7-bit ECC is applied to the system when the number of “0” “0” becomes 16–31. becomes 16–31.
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Table 2. Filter rule of the proposed 2D-VLEDC. Count of Zero
ECC Encode
0~15 16~31
1-bit parity 7-bit ECC
3.1. Experiment Flow The experiments were exercised with different ROM sizes from 8 × 32, 16 × 32, 32 × 32, 64 × 32, 128 × 32, to 256 × 32. For each ROM size, 100 trials are exercised, and each trial runs 106 times of fault injection and error detection evaluation. The flow chart of the provided experiments is shown in Figure 7 and described step by step as follows: Step 1. Specify ROM size and target simulation times (sim_times). The parameter “sim_times” is defined as 106 times here. Step 2. Repeat step 3 to step 9 100 times, and go to step 10. Step 3. Generate a random content of ROM. Step 4. Based on generated random content in the step 3, generate the encoding results as golden patterns of 1-bit parity, 2D parity, 7-bits ECC and 2D-VLEDC. Step 5. Repeat step 6 to step 8 106 times, and go to step 9. Step 6. Inject four random errors into the ROM randomly. Step 7. Perform the decoding flow of 1-bit parity, 2D parity, 7-bits ECC and 2D-VLEDC with the injected-errors ROM. Step 8. Check error detection of each decoding result. Accumulate the number of un-detected errors into the un-detected error counter and then go to step 4. Step 9. Log undetected error rate (Rateud ) and size overhead of each memory protection technology in the log-files. Go to step 2. Rateud = (un-detected error times/sim_times) × 100%
(1)
size_overhead = (redundant bits)/(total bits of memory)
(2)
Step 10. Analyze 95% confidence interval from the log-files. Step 11. Finish experiment. Therefore, there are 100 Rateud data for each ROM size with 1-bit parity, 2D parity, 7-bits ECC and 2D-VLEDC.
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Figure 7. 7. The The flow flow of of experiment. experiment. Figure
3.2. Performance Comparison 3.2. Performance Comparison The result result of of analyzing analyzing 95% 95% confidence confidence level level interval intervalwith with100 100Rate Rateud data for each ROM size are The ud data for each ROM size are 0.50.5 shown in the Table 3. In the Table 3, “Margin of Error” = 1.96 × σ/n . “StdDev” is the abbreviation of shown in the Table 3. In the Table 3, “Margin of Error” = 1.96 × σ/n . “StdDev” is the abbreviation “Standard Deviation”. “UDR” is is the of “Standard Deviation”. “UDR” theabbreviation abbreviationofof“Un-Detected “Un-Detectederror error Rate”. Rate”. Each Each “Average”, “Average”, 6 fault injection “StdDev” and “Margin of Error” value comes from the 100 trials, and each trial has 10 “StdDev” and “Margin of Error” value comes from the 100 trials, and each trial has 106 fault injection 6 fault injection simulations, the Rateud (UDR in the Table 3) from the simulations. From the 10 6 simulations. From the 10 fault injection simulations, the Rateud (UDR in the Table 3) from the Equation Equation can be obtained. (1) can be (1) obtained. Figure 8 shows the the undetected undetected error error rate rate of of each each methodology methodology versus versus ROM ROM size. size. The The point point of of Figure 8 shows the value value in in the the Figure Figure 88 is is the the field field of of “Average” “Average” in in the the Table Table33with withthe theprocess processof oflog log10.. 2D-VLEDC 2D-VLEDC the 10 has better performance at the ROM size 8 × 32. With the growing of the ROM size, ECC is getting getting has better performance at the ROM size 8 × 32. With the growing of the ROM size, ECC is better performance than the 2D-VLEDC. However, the error detection performance has no significant better performance than the 2D-VLEDC. However, the error detection performance has no significant difference between between them. them. difference Figure 9 shows thesize sizeoverhead overheadofofeach each methodology versus ROM size. It was calculated by Figure 9 shows the methodology versus ROM size. It was calculated by the the Equation overhead of 2D-parity gradually reduces approaches the overhead of Equation (2). (2). TheThe overhead of 2D-parity gradually reduces andand approaches the overhead sizesize of the the 1-bit parity with the growing of the ROM size. 2D-VLEDC has approximate 10 times 1-bit parity with the growing of the ROM size. 2D-VLEDC has approximate 10 times improvement improvement in error over the pays overhead. for 10~12%The overhead. results in error coverage rate coverage over the rate 2D-parity, but2D-parity, pays for but 10~12% resultsThe show that show that 2D-VLEDC needs 15% redundancy while ECC needs 22% redundancy in average. The 2D-VLEDC needs 15% redundancy while ECC needs 22% redundancy in average. The 2D-VLEDC 2Dhas VLEDC only the improvement of error rate that approximates coverage of ECC not only has the not improvement of error coverage ratecoverage that approximates the coveragethe of ECC but also has but also 30% less overhead than ECC’s.ofFor address of n,worst-case the required and best30% less has overhead than the ECC’s. Forthe address n, the required andworst-case best-case redundant caseare redundant are 7n andunder n, respectively, under the 2D-VLEDC. bits 7n and n,bits respectively, the 2D-VLEDC.
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Table 3. The comparison of the overhead of redundant bits. ROM (Read only memory); UDR (UnTable 3. The of the overhead of redundant bits. ROM (Read only memory); UDR Detected errorcomparison Rate); StdDev (Standard Deviation). (Un-Detected error Rate); StdDev (Standard Deviation).
ROM 8 × 32 Method/Statistics ROM 8 × 32 Method/Statistics Average 4.88 1-bit_parity Average StdDev 4.888.14 × 10−2 1-bit_parity −2 UDR (%) StdDev 8.14 × 10 Margin of Error 1.59 × 10−2 UDR (%) Margin of Error 1.59 × 10−2 Average 1.1 × 10−3 −3 2D_parity Average StdDev 1.1 × 10 3.78 × 10−4 2D_parity UDR (%) StdDev 3.78 × 10−4 UDR (%) Margin of Error 7.41 × 10−5 Margin of Error 7.41 × 10−5 Average 2.12 × 10−4 7-bit-ECC Average 2.12 × 10−4 7-bit-ECC StdDev 1.4 × 10−4 StdDev 1.4 × 10−4 UDR (%) UDR (%) −5 × 10−5 Margin 2.76 Margin of Error of Error 2.76 × 10 Average 7.7 × 10−5 Average 7.7 × 10−5 2D-VLEDC 2D-VLEDC −4 × 10−4 StdDev StdDev 1.4 × 101.4 UDR (%) UDR (%) −5 × 10−5 Margin 2.76 Margin of Error of Error 2.76 × 10 ROM ROM 64 × 3264 × 32 Method/Statistics Method/Statistics −1 Average Average 6.22 × 10 6.22 × 10−1 1-bit_parity 1-bit_parity StdDev 6.21 × 10−1 UDR (%) StdDev 6.21 × 10−1 Margin of Error 1.91 × 10−3 UDR (%) Margin of Error 1.91 × 10−3 Average 7.8 × 10−5 Average 7.8 × 10−5 2D_parity StdDev 1.03 × 10−4 2D_parity UDR (%) StdDev 1.03 −5 × 10−4 Margin of Error 2.02 × 10 UDR (%) Margin of Error 2.02 × 10−5 Average 3.0 × 10−6 7-bit-ECC 3.0 −5 × 10−6 StdDev Average 1.32 × 10 UDR (%) 7-bit-ECC −6 × 10−5 StdDev 1.32 Margin of Error 3.44 × 10 UDR (%) Margin of Error 3.44 × 10−6 Average 1.3 × 10−5 2D-VLEDC −5 × 10−5 StdDev Average 5.8 × 101.3 UDR (%) 2D-VLEDC −5 × 10−5 Margin of Error StdDev 5.8 1.13 × 10 UDR (%) Margin of Error 1.13 × 10−5
16 × 32 16 × 32
32 × 32 32 × 32
2.39 3.132.39 × 10−2 −2 3.13 × 6.14 × 10 10−−33 6.14 × 10 −4 4.25 × 10 −4 4.25 2.11×× 10 10−4 2.11 × 10−−54 4.15 × 10 4.15 × 10−5 2.8 × 10−55 2.8 × 10−−5 4.94 × 10 4.94 × 10−5 9.68 10−−66 9.68 ×× 10 2.9 × 10−5 2.9 × 10−5 5.7×× 10 10−−55 5.7 1.12×× 10 10−−55 1.12
1.2 1.44 × 10−21.2 −2 2.83 ×1.44 10−3× 10−3 2.83 × 10 1.66 × 10−4 −4 1.17 ×1.66 10−4× 10−4 1.17 × 10 2.3 × 10−5 2.3 × 10−5 5.0 × 10−6 5.0 × 10−6 2.19 × 10−5 2.19 × 10−5 4.29 ×4.29 10−6× 10−6 1.0 × 10−5 1.0 × 10−5 3.33 ×3.33 10−5× 10−5 6.53 ×6.53 10−6× 10−6
128 32 128× × 32
256 × 32 256 × 32
−1 3.35 3.35×× 10 10−1 5.78 × 10−−33 5.78 × 10−3 1.5 × 10
1.93 ×1.93 10−1× 10 1.36−3× 10−3 1.36 × 10 5.14 × 10−4 5.14 × 10−4 2.09 × 10−5 2.09 × 10−5 5.14 × 10−5 5.14 ×1.53 10−5× 10−5 1.53 × 10−5 9.3 × 10−7 −7 9.3 × 10 6.0 × 10−6 −6 6.0 × 10 1.82 × 10−6 1.82 ×2.32 10−6× 10−6 2.32 ×1.52 10−6× 10−5 1.52 ×4.55 10−5× 10−6 4.55 × 10−6
1.5 × 10−3
3.85 × 10−−55 3.85 × 10 5.26 × 10−5 5.26 10−−55 1.36 ×× 10
1.36 × 10−5
1.92 × 10−6 1.92×× 10 10−−65 1.32 1.32×× 10 10−−56 3.44
3.44 × 10−6
7.01 × 10−6 7.01×× 10 10−−65 5.29 5.29×× 10 10−−55 1.37
1.37 × 10−5
Figure Figure 8. 8. The The comparison comparison of of error error coverage coverage performance. performance.
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Appl. Sci. 2018, 8, 1211 Appl. Sci. 2018, 8, x FOR PEER REVIEW
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Figure Thecomparison comparison of the overhead of redundant bits. The overhead was by calculated Figure 9. 9. The of the overhead of redundant bits. The overhead was calculated Equation by (2). Equation (2).
4. Conclusions 4. Conclusions 2D-parity has a good error coverage rate, with very low cost when applied to NVM or ROM 2D-parity has a good error coverage rate, with very low cost when applied to NVM or ROM protection. Combining with the variable length of the error detection code, the 2D-VLEDC improves protection. Combining with the variable length of the error detection code, the 2D-VLEDC improves flexibility, achieving better tradeoffs between reliability and cost. In our experiments, a very simple flexibility, achieving better tradeoffs between reliability and cost. In our experiments, a very simple rule has been used in accordance with the asymmetric phenomenon between the 1-to-0 and 0-to-1 rule has been used in accordance with the asymmetric phenomenon between the 1-to-0 and 0-to-1 failures. 2D-VLEDC not only improves error coverage rate but also has the less overhead as compared failures. 2D-VLEDC not only improves error coverage rate but also has the less overhead as compared with other methodologies. NVM cell designer, NVM controller and system designer can co-work and with other methodologies. NVM cell designer, NVM controller and system designer can co-work and come out an optimized rule to be satisfied with the requirement of reliability. In the future, 2-bits parity, come out an optimized rule to be satisfied with the requirement of reliability. In the future, 2-bits 3-bits checksum or 4-bits CRC could be added into the encoder module. The rule table can also be parity, 3-bits checksum or 4-bits CRC could be added into the encoder module. The rule table can adjusted according to the requirement of reliability. The more zero counts included in the data word, also be adjusted according to the requirement of reliability. The more zero counts included in the the more redundant bits applied to memory protections. data word, the more redundant bits applied to memory protections. Author Contributions: C.-S.A.G. co-proposed the idea, performed the data verification, revised the manuscript, Author Contributions: C.-S.A.G. performed themanuscript. data verification, revised the manuscript, and supervised the work. Y.-C.C.co-proposed co-proposed the the idea, idea and wrote the L.-R.H. provided funding and supported the project. C.-J.Y. co-proposed the idea and carried outthe themanuscript. experiments.L.-R.H. K.-M.J.provided supported this project. and supervised the work. Y.-C.C. co-proposed the idea and wrote funding and K.-L.L. contributed the C.-J.Y. technical details. J.-C.L. thisout study. supported the project. co-proposed the co-supervised idea and carried the experiments. K.-M.J. supported this project. K.-L.L. the technical details. this study. Funding: Thiscontributed study was funded in part with J.-C.L. grantsco-supervised from the Ministry of Science and Technology (MOST), Taiwan, under Grants MOST 105-2221-E-182-039, MOST 106-2221-E-182 -005-, and MOST 107-2221-E-182 -075 Funding: This study was funded ininpart grants from theMemorial Ministry Hospital of Science and Technology -MY2. This work is also supported part with by the Chang Gung (CGMH) under the (MOST), contracts Taiwan, under Grants MOST 105-2221-E-182-039, MOST 106-2221-E-182 -005-, and MOST 107-2221-E-182 -075 CMRPD2F0103, CMRPD2G0331, and CMRPD2H0041. Financial support provided by Industrial Technology Research appreciated. MY2. ThisInstitute work is is also supported in part by the Chang Gung Memorial Hospital (CGMH) under the contracts CMRPD2F0103, CMRPD2G0331, CMRPD2H0041. Conflicts of Interest: The authorsand declare no competingFinancial interests. support provided by Industrial Technology Research Institute is appreciated.
References Conflicts of Interest: The authors declare no competing interests. 1.
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