IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 56, NO. 5, MAY 2009
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Understanding and Optimization of Hot-Carrier Reliability in Germanium-on-Silicon pMOSFETs Debabrata Maji, Felice Crupi, Esteve Amat, Eddy Simoen, Brice De Jaeger, David P. Brunco, C. R. Manoj, V. Ramgopal Rao, Senior Member, IEEE, Paolo Magnone, Gino Giusi, Calogero Pace, Luigi Pantisano, Jérôme Mitard, Rosana Rodríguez, and Montserrat Nafría, Senior Member, IEEE
Abstract—In this paper, a comprehensive study of hotcarrier injection (HCI) has been performed on high-performance Si-passivated pMOSFETs with high-k metal gate fabricated on n-type germanium-on-silicon (Ge-on-Si) substrates. Negative bias temperature instability (NBTI) has also been explored on the same devices. The following are found: 1) Impact ionization rate in Ge-on-Si MOSFETs is approximately two orders higher as compared to their Si counterpart; 2) NBTI degradation is a lesser concern than HCI for Ge-on-Si pMOSFETs; and 3) increasing the Si-passivation thickness from four to eight monolayers provides a remarkable lifetime improvement. Index Terms—Germanium, high-k, hot carrier (HC), impact ionization, negative bias temperature instability (NBTI), pMOSFET.
I. INTRODUCTION
R
ECENTLY, germanium-based CMOS devices have gained much attention because of their higher channel mobility and higher on current with respect to the silicon counterpart. Several research groups have successfully demonstrated higher performance Ge pMOSFETs utilizing high-k/metal gate stacks [1]–[7]. Generally, fabrication of high-performance CMOS devices requires the control of short-channel effects, like threshold voltage roll-off and drain-induced barrier lowering (DIBL), as well as control of the leakage currents and good reliability. Recently, it has been shown that halo implants can provide such short-channel control for Ge pMOSFETs [4], [8] at the cost of a higher drain-to-well leakage current with respect to silicon devices [9]. For the silicon case, it is known [10] that halo implant increases hot-carrier (HC) degradation. To date, the most promising Ge results have been obtained using a Si-passivation layer where a few monolayers (MLs) of Si are epitaxially grown on the Ge surface immediately prior to gate Manuscript received September 2, 2008; revised November 12, 2008. First published March 24, 2009; current version published April 22, 2009. This work was supported in part by the Italian Ministry of University and Research (MIUR) under the project “Grants for Young Indian Researchers.” The review of this paper was arranged by Editor J. Suehle. D. Maji, C. R. Manoj, and V. R. Rao are with the Department of Electrical Engineering, Indian Institute of Technology, Bombay 400 076, India. F. Crupi, P. Magnone, G. Giusi, and C. Pace are with the DEIS, University of Calabria, 87036 Rende, Italy (e-mail:
[email protected]). E. Amat, R. Rodríguez, and M. Nafría are with the Departament d’Enginyeria Electrònica, Escola Tècnica Superior d’Enginyeria, Universitat Autònoma de Barcelona, 08193 Barcelona, Spain. E. Simoen, B. De Jaeger, L. Pantisano, and J. Mitard are with the Interuniversity Microelectronics Center, 3001 Leuven, Belgium. D. P. Brunco was with the Interuniversity Microelectronics Center, 3001 Leuven, Belgium. He is now with Intel Corporation, Hillsboro, OR 97124 USA. Digital Object Identifier 10.1109/TED.2009.2015854
stack formation [3], [4], [7], [8], [11]. In particular, it is interesting to note that Si-passivated Ge devices showed better electrical performance and reliability than silicon-nitride-passivated Ge devices, and Si-passivated Ge devices also showed better negative-bias-temperature-instability (NBTI) performance than their Si counterpart [12]. Recently, studies have found that the Si-passivation layer thickness influences drive current, mobility, and subthreshold slope in Ge pMOSFETs, suggesting an optimal thickness of approximately six Si MLs [7], [11]. In addition, the time-dependent dielectric breakdown (TDDB) was investigated for Si-passivated Ge devices, indicating a good quality of the high-k gate stack [13]. Recently, Loh et al. examined Si/Si1−x Gex /Si pMOSFETs with x = 0.2 to 0.5 and reported that a higher Ge percentage and thinner Si cap are preferable for HC reliability [14]. All these results renew our interest to study the reliability of the Si-passivated Ge pMOSFETs. Eventually, there are no reports which clearly indicate what will limit the lifetime of a 22-nm-node Ge pMOSFET, whether it is TDDB, HC injection (HCI), or NBTI. Considering all these facts, we present a comprehensive study of HC degradation for high-performance epitaxial Ge-on-Si high-k/metal gate pMOSFETs. This paper is organized as follows. Section II describes the samples and the measurement details. In Section III, after a brief report on the device electrical characteristics (Section III-A), the HC reliability is investigated from different perspectives: impact ionization rate and device lifetime (Section III-B), simulation (Section III-C), comparison with NBTI (Section III-D), and impact of Si-passivation thickness (Section III-E). In the Conclusion, we summarize the main results of the present work. II. EXPERIMENTAL Devices were fabricated using 200-mm Ge-on-Si wafers. A relaxed ∼1.6–2-μm Ge layer was deposited epitaxially on top of the Si. First, an n-well was formed with 31 P implants of 1 × 1013 cm−2 dose at 570 keV followed by 2.5 × 1012 cm−2 at 180 keV. The threshold voltage adjust implant was 4 × 1012 cm−2 at 90 keV with 31 P. Isolation was achieved using a deposited and patterned SiO2 layer. The Ge surface was passivated with four, six, or eight MLs of epi Si grown at 500 ◦ C using SiH4 as a precursor, followed promptly by oxidation in slightly ozonated water to get approximately 0.5-nm SiO2 . Immediately after, 4-nm HfO2 was deposited by atomic layer deposition (ALD). The gate metal consisted of TiN/TaN. A 31 P dose of 4 × 1013 cm−2 at 60 keV was used for halo to
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Fig. 1. Schematic cross-sectional diagram of Ge pMOSFET.
Fig. 3. IOFF as a function of gate length for Ge pMOSFETS. IOFF is measured at VG = VT + 0.33 V.
Fig. 2. Threshold voltage and DIBL as a function of gate length for Ge pMOSFETs.
control the short-channel performance. A detailed process flow can be found elsewhere [4]. For comparison purposes, we characterized a second set of devices on a Si substrate and with similar gate stack consisting of 0.8 nm of SiO2 , 2 nm of ALD HfO2 , and TiN metal gate. The device performance and reliability characterization were done using a Keithley 4200 semiconductor characterization system and an Agilent E4980A precision LCR meter. All measurements were done at room temperature unless stated otherwise. In Fig. 1, a schematic diagram of the Ge-on-Si pMOSFET used in this paper is shown.
Fig. 4. Effective hole mobility as a function of hole inversion charge. A 2× mobility improvement is observed for Ge compared to Si.
III. RESULT AND DISCUSSION A. Device Characterization In this section, we highlight the performances of six-ML Sipassivated Ge pMOSFETs. These Ge devices show acceptable threshold voltage (VT ) roll-off and DIBL characteristics as shown in Fig. 2. Good control of off current is observed for Ge pMOSFETs, when measured at the source [15], [16]. The off currents were measured at room temperature with the source and substrate grounded, the gate at VT + 0.33 V [4], and the drain at −1 V. The IOFF is close to the ITRS-specified value of 7 nA/μm as shown in Fig. 3 and also reported by Nicholas et al. [4]. All these results confirm that Ge-on-Si pMOSFETs have good short-channel performance. The advantage of using Ge as a channel material lies in the higher hole mobility with respect to Si. The hole mobility was extracted by measuring the channel-to-gate capacitance (CGC ) and ID –VG at −20-mV drain bias. The contribution from the source and drain overlap capacitance has been nullified from CGC by subtracting the average minimum CGC value from the overall CGC data. Fig. 4 shows the extracted effective hole mobility
Fig. 5. Comparison of ISUB –Ijnleakage versus VGT for Si and Ge pMOSFET devices at a drain bias of −2.1 V. ISUB for Ge is at least two orders higher.
as a function of hole Ninv for Ge and Si pMOSFETs from a split C–V measurement. We observe a 2× peak hole mobility enhancement for Ge compared to Si in Fig. 4. B. HC Degradation In this section, our discussion will be focused mainly on HC degradation of the six-ML Si-passivated Ge pMOSFETs. The smaller bandgap of Ge as compared to that of Si is expected to yield higher HC effects in the Ge devices. To investigate the effect of the bandgap on impact ionization on real devices, the substrate current as a function of gate voltage overdrive (VGT ) is plotted at high drain bias values in Fig. 5 for both Ge and
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MAJI et al.: UNDERSTANDING AND OPTIMIZATION OF HC RELIABILITY IN GERMANIUM-ON-SILICON pMOSFET
Fig. 6. Impact ionization rate at ISUBpeak plotted as a function of VD for both Ge and Si pMOSFETs.
Fig. 8. Comparison of pMOSFET lifetime at room temperature (25 for Ge and Si devices. The stress condition is VG = VD = −Vstress .
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Fig. 7. Threshold variation at VG = VD = −1.6 V at room temperature (25 ◦ C). Ge devices show worse degradation compared to Si.
Si devices. It is important to observe that the substrate current ISUB is corrected from the drain-well junction leakage current contribution measured at the same VD with source and gate floating. The corrected ISUB is still two orders of magnitude higher compared to the Si counterpart. The bell-shaped curve is wider in the Ge case, and the peak occurs at a higher VGT value when compared to the Si devices. As known, the ratio ISUB /ID gives the electron–hole pair generation rate at the drain end. From Fig. 6, it is clear that the ratio is higher in the Ge case and that impact ionization is a serious issue for Ge devices because the generated hot holes can be injected into the gate oxide and degrade the interface and quality of the oxide. Moreover, it is already known from our previous study that the density of initial traps present in the gate oxide on Ge is higher than for Si devices, due to Ge outdiffusion into the gate oxide [17]. In order to investigate the oxide degradation, HCI stress under VG = VD = −1.6 V was investigated for 155-nm gate length (LG ) devices. Stress was interrupted periodically, ID –VG was measured at −50-mV drain bias each time, and VT was extracted using the maximum transconductance method. As stress time increases, VT shifts toward the negative direction which indicates positive charge trapping into the oxide. Fig. 7 shows that damage of the Ge device is a serious concern. Fig. 8 compares the lifetime of Si and Ge devices. The lifetime was defined when the VT shift reaches 30 mV in absolute value. Lifetime is worst in case of Ge when compared with the Si device. It also indicates that HC degradation can be an issue for Ge pMOSFETs.
Fig. 9. Two-dimensional Sentaurus SPARTA simulations show (upper) higher longitudinal electric field and (lower) hole temperature for Ge compared to Si. ISUBMAX and VG = VD are two stress biases used for simulation. Zero is the center of the channel.
C. Simulation To confirm the mechanisms for accelerated degradation, 2-D device simulations have been performed with the TCAD package “Sentaurus Sparta,” a full-band Monte Carlo simulator which includes all the common scattering mechanisms including impact ionization. From Fig. 9, it is evident that the lateral electric field for the case of Ge-based devices is higher with respect to the Si case. The higher electric field and the lower bandgap are the root causes for the higher impact ionization rate and carrier temperature. The impact ionization rate, as shown in Fig. 10, has been simulated by using the van Overstraeten–de Man model [18]. Fig. 10 shows that a difference of two orders exists in the impact ionization rate between the Si and Ge devices, confirming the experimental
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Fig. 10. Two-dimensional Sentaurus SPARTA simulations show two orders high hole generation rate (Gp ) near the drain. Gp for Si is equal to 4.7 × 1019 cm−3 /s, and for Ge, the value is equal to 2.7 × 1021 cm−3 /s. Zero is the center of the channel.
Fig. 12. HCI (25 ◦ C) and NBTI (85 ◦ C) data are shown for Ge pMOSFETs for gate length of 125 nm. NBTI lifetime is better than HCI lifetime at lower VG = VD stress condition.
Fig. 11. HCI induces higher degradation compared to NBTI at low stress bias and shows comparable degradation at higher stress bias for Ge devices. For Si samples, HCI induces lower degradation compared to NBTI at low stress bias as well as at higher stress bias.
Fig. 13. VT shift as a function of stress time for Ge with different numbers of Si MLs. HCI degradation decreases with increasing the number of Si MLs.
data in Fig. 6. In addition, the hole temperature in Fig. 9 for the Ge case is higher in agreement with the higher HC degradation observed in experiments as shown in Fig. 7.
D. HC Versus NBTI NBTI is known to be the dominant degradation mechanism for Si pMOSFETs. On the other hand, HCI is not a serious reliability issue for Si pMOSFETs. Here, we report a comparison study of HCI and NBTI on Ge-on-Si pMOSFETs. The experiment has been carried out using a 125-nm gate length, which is the shortest available for both our Ge and Si devices. NBTI measurements were carried out at 85 ◦ C, and HCI measurements were at 25 ◦ C. To observe NBTI VT degradation, ID –VG sweeps were used and the threshold voltage was monitored after each stress. The measurement time was kept to a minimum between consecutive stresses to avoid charge carrier detrapping. From Fig. 11, it is clear that at low VG (= −1.2 V), HCI dominates over NBTI for Ge pMOSFET, and at VG = −1.5 and −1.8 V, HCI and NBTI degradations are comparable. However, in Fig. 12, the lifetime projections of HCI and NBTI with a 30-mV VT shift criterion clearly indicate that HCI dominates over NBTI. On the other hand, NBTI is a more prominent degradation mechanism for Si pMOSFET in
Fig. 14. Lifetime for Ge pMOSFETs for different numbers of Si MLs. The HCI stress condition is VG = VD . Additional Si MLs improve the lifetime for Ge pMOSFETs.
the investigated stress condition. HCI and NBTI degradation mechanisms differ, with HCI degradation strongly dependent on longitudinal electric field. As the channel length decreases, the lateral electric field increases; hence, the impact ionization near the drain increases. This produces energetic carriers which create interface traps and bulk oxide traps depending on vertical electric field. Adding the fact that Ge is a small bandgap material, we observe worse HCI degradation in Ge pMOSFET in the operating voltage regime. As expected, NBTI degradation is always higher for the Si pMOSFETs. Fig. 12 suggests that HCI is a major reliability issue for Ge-on-Si pMOSFETs.
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MAJI et al.: UNDERSTANDING AND OPTIMIZATION OF HC RELIABILITY IN GERMANIUM-ON-SILICON pMOSFET
E. HC Reliability Optimization Interestingly, when the deposited Si layer is increased from four to eight MLs, the HCI reliability of the Ge devices improves in terms of degradation and lifetime, as shown in Figs. 13 and 14. In particular, a maximum operating voltage higher than 1 V can be obtained by using eight Si MLs. This result clearly indicates that the HC problem in Ge pMOSFETs can be strongly alleviated by using an appropriate Si-passivation thickness. The improved HCI lifetime well correlates with previous studies which have shown that by increasing the thickness of the Si-passivation layer up to eight MLs, it is possible to improve the device performance in terms of mobility and subthreshold slope [11]. According to the study in [11], only traps in the valence band half of the Ge bandgap contribute to scattering of free inversion carriers. Hence, improvements in terms of performance and HCI lifetime can be considered as effects originated by a common root cause, which consists of the reduction of traps in the valence band half of the bandgap with the thickness of the Si-passivation layer. In addition, increasing the number of Si MLs shifts the VT to a more negative value and makes the device behave more like a buried channel [7], [11]. Eventually, it reduces the effective oxide electric field and, hence, the HC degradation. IV. CONCLUSION HC reliability is investigated for state-of-the-art Si-passivated pMOSFETs with high-k/metal gate fabricated on n-type Ge-on-Si substrates. On the basis of the experimental results, we conclude the following: 1) A two orders higher impact ionization rate is observed in Ge devices compared to their Si counterparts; 2) HC degradation seems to be the dominant degradation mechanism for Ge-on-Si pMOSFETs, even more than NBTI; and 3) by increasing the Si-passivation thickness, HC degradation can be significantly reduced and meet the required lifetime projections. R EFERENCES [1] C. O. Chui, H. Kim, D. Chi, B. B. Triplett, P. C. McIntyre, and K. C. Saraswat, “A sub-400 ◦ C germanium MOSFET technology with high-k dielectric and metal gate,” in IEDM Tech. Dig., 2002, pp. 437–440. [2] N. Wu, Q. Zhang, C. Zhu, D. S. H. Chan, A. Du, N. Balasubramanian, M.-F. Li, A. Chin, J. K. O. Sin, and D.-L. Kwong, “A TaN-HfO2 -Ge pMOSFET with novel SiH4 surface passivation,” IEEE Electron Device Lett., vol. 25, no. 9, pp. 631–633, Sep. 2004. [3] P. Zimmerman, G. Nicholas, B. De Jaeger, B. Kaczer, A. Stesmans, L.-Å. Ragnarsson, D. P. Brunco, F. E. Leys, M. Caymax, G. Winderickx, K. Opsomer, M. Meuris, and M. M. Heyns, “High performance Ge pMOS devices using Si-compatible process flow,” in IEDM Tech. Dig., 2006, pp. 655–657. [4] G. Nicholas, B. D. Jaeger, D. P. Brunco, P. Zimmerman, G. Eneman, K. Martens, M. Meuris, and M. Heyns, “High-performance deep submicron Ge pMOSFETs with halo implants,” IEEE Trans. Electron Devices, vol. 54, no. 9, pp. 2503–2511, Sep. 2007. [5] J. Oh, P. Majhi, H. Lee, O. Yoo, S. Banerjee, C. Y. Kang, J.-W. Yang, R. Harris, H.-H. Tseng, and R. Jammy, “Improved electrical characteristics of Ge-on-Si field effect transistors with control Ge epitaxial layer thickness on Si substrates,” IEEE Electron Device Lett., vol. 28, no. 11, pp. 1044–1046, Nov. 2007. [6] A. Ritenour, J. Hennessy, and D. A. Antoniadis, “Investigation of carrier transport in germanium MOSFETs with WN/Al2 O3 /AlN gate stacks,” IEEE Electron Device Lett., vol. 28, no. 8, pp. 746–749, Aug. 2007.
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[7] D. P. Brunco, B. De Jaeger, G. Eneman, J. Mitard, G. Hellings, A. Satta, V. Terzieva, L. Souriau, F. E. Leys, G. Pourtois, M. Houssa, G. Winderickx, E. Vrancken, S. Sioncke, K. Opsomer, G. Nicholas, M. Caymax, A. Stesman, J. Van Steenbergen, P. W. Mertens, M. Meuris, and M. M. Heyns, “Germanium MOSFET devices: Advances in materials understanding, process development, and electrical performance,” J. Electrochem. Soc., vol. 155, no. 7, pp. H552–H557, 2008. [8] E. Simoen, E. Voroshazi, J. Mitard, G. Eneman, D. P. Brunco, B. De Jaeger, and M. Meuris, “Substrate bias effect on Ge pMOSFETs with and without halo,” in Proc. Int. Conf. Ultimate Integration Silicon, 2008, pp. 11–14. [9] G. Eneman, O. Sicart i Casain, E. Simoen, D. P. Brunco, B. De Jaeger, A. Satta, G. Nicholas, C. Claeys, M. Meuris, and M. M. Heyns, “Analysis of junction leakage in advanced germanium P+/n junctions,” in Proc. ESSDERC, 2007, pp. 454–457. [10] A. Das, H. De, V. Misra, S. Venkatesan, S. Veeraraghavan, and M. Foisy, “Effect of halo implant on hot carrier reliability of sub-quarter micron MOSFETs,” in Proc. Int. Rel. Phys. Symp., 1998, pp. 189–193. [11] K. Martens, J. Mitard, B. De Jaeger, M. Meuris, H. Maes, G. Groeseneken, F. Minucci, and F. Crupi, “Impact of Si-thickness on interface and device properties for Si-passivated Ge pMOSFETs,” in Proc. ESSDERC, 2008, pp. 138–141. [12] N. Wu, Q. Zhang, C. Zhu, C. Shen, M. F. Li, D. S. H. Chan, and N. Balasubramanian, “BTI and charge trapping in germanium p- and n MOSFETs with CVD HfO2 gate dielectric,” in IEDM Tech. Dig., 2004, p. 558. [13] B. Kaczer, B. De Jaeger, G. Nicholas, K. Martens, R. Degraeve, M. Houssa, G. Pourtois, F. Leys, M. Meuris, and G. Groeseneken, “Electrical and reliability characterization of metal-gate/HfO2 /Ge FETs with Si passivation,” Microelectron. Eng., vol. 84, no. 9/10, pp. 2067–2070, Sep. 2007. [14] W.-Y. Loh, P. Majhi, S.-H. Lee, J.-W. Oh, B. Sassman, C. Young, G. Bersuker, B.-J. Cho, C.-S. Park, C.-Y. Kang, P. Kirsch, B.-H. Lee, H. R. Harris, H.-H. Tseng, and R. Jammy, “The effect of Ge composition and Si cap thickness on hot carrier reliability of Si/Si1−x Gex /Si p-MOSFETs with high-k/metal gate,” in VLSI Symp. Tech. Dig., 2008, pp. 56–57. [15] G. Hellings, J. Mitard, G. Eneman, B. De Jaeger, D. P. Brunco, D. Shamiryan, T. Vandeweyer, M. Meuris, M. M. Heyns, and K. De Meyer, “High performance 70 nm germanium pMOSFETs with boron LDD implants,” IEEE Electron Device Lett., vol. 30, no. 1, pp. 88– 90, Jan. 2009. [16] J. Mitard, B. De Jaeger, F. Leys, G. Hellings, K. Martens, G. Eneman, D. P. Brunco, R. Loo, D. Shamiryan, T. Vandeweyer, G. Winderickx, E. Vrancken, K. De Meyer, M. Caymax, L. Pantisano, M. Meuris, and M. Heyns, in IEDM Tech. Dig., San Francisco, CA, Dec. 15–17, 2008, p. 873. [17] D. Maji, F. Crupi, G. Giusi, C. Pace, E. Simoen, C. Claeys, and V. R. Rao, “On the dc and noise properties of the gate current in epitaxial Ge p-channel metal oxide semiconductor field effect transistors with TiN/TaN/HfO2 /SiO2 gate stack,” Appl. Phys. Lett., vol. 92, no. 16, p. 163 508, Apr. 2008. [18] R. van Overstraeten and H. de Man, “Measurement of the ionization rates in diffused silicon p-n junctions,” Solid State Electron., vol. 13, no. 1, pp. 583–608, Jan. 1970.
Debabrata Maji received the B.Tech. and M.Tech. degrees in radiophysics and electronics from the Institute of Radiophysics and Electronics, University of Calcutta, Kolkata, India, in 2001 and 2003, respectively. He is currently working toward the Ph.D. degree in the Electrical Engineering Department, Indian Institute of Technology, Bombay, India. He was a Summer Intern with Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu, Taiwan. Currently, he is a Visiting Indian Researcher with the University of Calabria, Rende, Italy. His research interests include device characterization, reliability, and noise measurements in advanced MOS devices.
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Felice Crupi received the M.Sc. degree in electronic engineering from the University of Messina, Messina, Italy, in 1997, and the Ph.D. degree from the University of Firenze, Firenze, Italy, in 2001. Since 2002, he has been with the University of Calabria, Rende, Italy, where he is currently an Associate Professor of electronics. Since 1998, he has been a repeat Visiting Scientist with the Interuniversity Micro-Electronics Center, Leuven, Belgium. In 2000, he was a Visiting Scientist with the IBM Thomas J. Watson Research Center, Yorktown Heights, NY. In 2006, he was a Visiting Scientist with the Universitat Autonoma de Barcelona, Barcelona, Spain. His main research interests include reliability of very large scale integration CMOS devices, electrical characterization techniques for solid-state electronic devices, and the design of ultralownoise electronic instrumentation. He has authored or coauthored more than 100 publications in international scientific journals and in international conference proceedings.
Esteve Amat received the M.Sc. degree in electronic engineering from the Universitat Autònoma de Barcelona, Barcelona, Spain, in 2004, where he is currently working toward the Ph.D. degree in the Departament d’Enginyeria Electrònica, Escola Tècnica Superior d’Enginyeria. Recently, he joined the Interuniversity MicroElectronics Center, Leuven, Belgium, within the APROTHIN project (Marie Curie Actions), where he worked on the channel hot-carrier degradation nMOS and pMOS transistors with different dielectric materials (SiO2 or high-k). His main research interest is focused on the analysis of the degradation in ultrathin SiO2 or high-k dielectrics films.
Eddy Simoen received the M.S. degree in physics engineering and the Doctoral degree in engineering from the University of Gent, Ghent, Belgium, in 1980 and 1985, respectively. His doctoral thesis was devoted to the study of trap levels in high-purity germanium by deep-level transient spectroscopy. In 1986, he joined the Interuniversity MicroElectronics Center (IMEC), Leuven, Belgium, to work in the field of low-temperature electronics. His current research interests cover the field of device physics and defect engineering in general, with particular emphasis on the study of low-frequency noise, low-temperature behavior, and of radiation defects in semiconductor components and materials. He is an IMEC Scientist, currently involved in the study of defect and strain engineering in high-mobility and epitaxial substrates and defect studies in germanium. In these fields, he has (co)authored over 900 journals and conference papers and, in addition, 11 book chapters and a monograph on Radiation Effects in Advanced Semiconductor Devices and Materials (Springer, 2002) whereof the Chinese translation has been published in March 2008. He was also a Coeditor of the book Germanium-based Technologies—from Materials to Devices (Elsevier, March 2007). A new book on the “Fundamental and Technological Aspects of Extended Defects in Germanium” will be published by Springer in January 2009. He acted as a Coeditor of four international conference proceedings and was a Lecturer with the International Noise School held at IMEC, in 1993, at the ENDEASD Workshop in Santorini (Greece, April 1999) and Stockholm (Sweden, June 2000) and at the EUROSOI Workshop in Leuven (January, 2007).
Brice De Jaeger received the B.S. and M.S. degrees in electrical engineering from the Universiteit Gent, Ghent, Belgium, in 1994 and 1997, respectively. Since 1997, he has been a Researcher with the CMOS Device Research Department, Interuniversity Microelectronics Center, Leuven, Belgium, where he is currently an Intel Assignee. His current research interests include the technology, device integration, and characterization of germanium and III/V transistors.
David P. Brunco received the B.S. degree in materials science and engineering from the Massachusetts Institute of Technology, Cambridge, in 1988, and the Ph.D. degree in materials science and engineering from Cornell University, Ithaca, NY, in 1995. In 1995, he joined Intel as an RTA Process Engineer at D2 in Santa Clara, CA, where he contributed to process technologies from the 0.25-μm to the 45-nm nodes. Between July 2004 and July 2008, he was an Intel Assignee to the Interuniversity Microelectronics Center, Leuven, Belgium, focusing on the high-k/metal gate, Ge/II–V, and flash memory programs. Since August 2008, he has been with the Intel D1D Ramp organization in Hillsboro, OR, where he is currently working on front-end integration for the 32-nm node.
C. R. Manoj received the B.Tech. degree in electronics and communication engineering from the College of Engineering, Trivandrum, Kerala, India, in 1995, and the M.Tech. and Ph.D. degrees in microelectronics from the Indian Institute of Technology (IIT), Bombay, India, in 2002 and 2008, respectively. From 1996 to 1998, he was a Deputy Engineer with Bharat Electronics Ltd., Bangalore, India. From 1998 onward, he was a faculty member with the National Institute of Technology, Calicut, India. In 2007, he was a Visiting Research Student with Taiwan Semiconductor Manufacturing Company, Hsinchu, Taiwan, where he worked on TCAD simulation of novel CMOS devices. He is currently with IIT Bombay. His research interest includes novel CMOS devices such as FinFETs, Tunnel FETs, etc.
V. Ramgopal Rao (M’98–SM’02) received the M.Tech. degree from the Indian Institute of Technology (IIT) Bombay, Mumbai, India, in 1991, and the Dr. Ingenieur degree from the Faculty of Electrical Engineering, Universitaet der Bundeswehr Munich, Germany, in 1997. From 1997 to 1998 and again in 2001, he was a Visiting Scholar with the Electrical Engineering Department, University of California, Los Angeles. He is currently a Professor with the Department of Electrical Engineering, IIT Bombay. He is the Chief Investigator for the Centre for Excellence in Nanoelectronics project at IIT Bombay besides being the Principal Investigator for many ongoing sponsored projects funded by various multinational industries and government agencies. He also serves on various Government of India committees on nanotechnology. His research interests include physics, technology, and characterization of silicon CMOS devices for logic and mixed-signal application and nanoelectronics. He has over 200 publications in these areas in refereed international journals and conference proceedings. He is the holder of three patents, with seven currently pending. Prof. Rao is a Fellow of the Indian National Academy of Engineering, the Indian Academy of Sciences, and the Institution of Electronics and Telecommunication Engineers. He is an Editor for the IEEE TRANSACTIONS ON ELECTRON DEVICES in the CMOS devices and technology area and is a Distinguished Lecturer of the IEEE Electron Devices Society. He was the organizing committee Chair for the 17th International Conference on VLSI Design and the 14th International Workshop on the Physics of Semiconductor Devices and serves on the program/organizing committees of various international conferences, including the International Electron Devices Meeting, IEEE Asian Solid-State Circuits Conference, 2006 IEEE Conference on NanoNetworks, ACM/IEEE International Symposium on Low Power Electronics and Design, 11th IEEE VLSI Design & Test Symposium, among others. He was the Chairman of the IEEE AP/ED Bombay Chapter during 2002–2003 and currently serves on the executive committee of IEEE Bombay Section besides being the Vice-Chair of the IEEE Asia-Pacific Regions/Chapters Subcommittee. He received the Shanti Swarup Bhatnagar Prize in Engineering Sciences, in 2005, for his work on electron devices. He also received the Swarnajayanti Fellowship Award for 2003–2004, instituted by the Department of Science and Technology, Government of India; the 2007 IBM Faculty award; and the 2008 “The Materials Research Society of India (MRSI) Superconductivity & Materials Science Prize.”
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MAJI et al.: UNDERSTANDING AND OPTIMIZATION OF HC RELIABILITY IN GERMANIUM-ON-SILICON pMOSFET
Paolo Magnone received the B.S. and M.Sc. degrees in electronic engineering from the University of Calabria, Rende, Italy, in 2003 and 2005, respectively, where he is currently working toward the Ph.D. degree. From October 2006 to April 2007 and from October 2007 to April 2008, he was with the Interuniversity Micro-Electronics Center, Leuven, Belgium, within the APROTHIN project (Marie Curie Actions), where he worked on parameter extraction and matching analysis of FinFET devices. His research interests include the electrical characterization of semiconductor devices with particular emphasis on the study of low-frequency noise.
Gino Giusi received the M.Sc. and Ph.D. degrees in electronic engineering from the University of Messina, Messina, Italy, in 2002 and 2005, respectively. In 2005, he was a Visitor with the Interuniversity Micro-Electronics Center, Leuven, Belgium. In 2006, he was with the National Research Center, Catania, Italy. He is currently a Contract Researcher and Contract Professor with the University of Calabria, Rende, Italy. His main research interests include the study of electrical characterization techniques and reliability for solid state electronic devices, the modeling and simulation of nanoscale CMOS transistors and memories, and the design of ultralow-noise electronic instrumentation and techniques for low-frequency noise measurements. He is the author of more than 20 international journals. Dr. Giusi serves as a reviewer for internal journals like IEEE TRANSAC TIONS ON E LECTRON D EVICES and IEEE E LECTRON D EVICE L ETTERS .
Calogero Pace received the M.Sc. and Ph.D. degrees in electronic engineering from the University of Palermo, Palermo, Italy, in 1990 and 1994, respectively. In 1996, he was with the University of Messina, Messina, Italy, as an Assistant Professor. In 2002, he moved to the University of Calabria, Rende, Italy, where he is currently an Associate Professor of electronics. He is currently involved in research projects, on the design of low-noise electronic instrumentation, on the design and characterization of electronic gas sensors, and on the study of nanocrystal and SONOS memory devices. He coordinated the Italian Ministry of Foreign Affairs international project “RHESSA” on the radiation hardness of electronic devices and systems for space applications. He is a coauthor of about 40 scientific and technical papers published in international refereed journals.
Luigi Pantisano received the M.S. and Ph.D. degrees in electrical engineering from the University of Padova, Padova, Italy, in 1996 and 2000, respectively. In 2000, he was with Bell Laboratories, Lucent Technologies, Murray Hill, NJ, pursuing the impact of plasma-charging damage on RF CMOS devices. Since 2001, he has been with the Interuniversity Micro-Electronics Center, Leuven, Belgium, working on high-k gate dielectrics for CMOS and memory technologies. He has contributed more than 150 papers in the field of plasma damage, RF measurements, reliability, and electrical characterization of novel high-k devices. Dr. Pantisano is a committee member of several conferences, namely, SISC, IRPS, IGSAT, and ICMTS.
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Jérôme Mitard received the degree in microelectronic engineering from the Polytechnic University School of Marseilles, France, in 2003. For three years, he acted as the ST Assignee at CEA-LETI, Grenoble, France, where he was involved in the electrical characterization of hafniumbased dielectrics with metal gate for sub-70-nm CMOS technologies. After his Ph.D. in microelectronics at Minatec Center, Grenoble, France, he joined the Interuniversity Micro-Electronics Center, Leuven, Belgium, as a Postdoctoral Researcher, where he is currently working on the integration of germanium and III–V substrates for 22-nm CMOS node.
Rosana Rodríguez received the degree in telecommunication engineering from the Universitat Politècnica de Catalunya, Barcelona, Spain, in 1995, and the Ph.D. degree in electrical engineering from the Universitat Autònoma de Barcelona, Barcelona, in 2000. Funded by the Fulbright program, she was with the IBM Thomas J. Watson Research Center, Yorktown Heights, NY, working on device and circuit reliability. Currently, she is an Associate Professor with the Departament d’Enginyeria Electrònica, Escola Tècnica Superior d’Enginyeria, Universitat Autònoma de Barcelona. Her main research interests are focused on the effect of CMOS dielectric failure on the performance of single devices and digital and analog circuits. In particular, she analyzes, both experimental and theoretically, different failure mechanisms such as dielectric degradation and breakdown, NBTI, and channel hot carriers on state-of-the-art gate dielectrics under dc and ac conditions.
Montserrat Nafría (M’99–SM’03) received the Ph.D. degree in physics from the Universitat Autònoma de Barcelona, Barcelona, Spain, in 1993. She is currently an Associate Professor with the Departament d’Enginyeria Electrònica, Escola Tècnica Superior d’Enginyeria, Universitat Autònoma de Barcelona. Her major research interest is in the area of CMOS device and circuit reliability. In particular, she has been engaged in the characterization and modeling of the dielectric breakdown of SiO2 based MOS devices using standard electrical characterization techniques and, recently, also conductive atomic force microscopy. Her current research interests are in the field of high-k dielectric-based MOS device reliability, including its nanoscale characterization using AFM-related techniques and the modeling of gate-dielectric-related failure mechanisms (breakdown, BTI, hot carriers, etc.) for circuit reliability simulation. She has (co)authored more than 150 research papers in scientific journals and conferences in all these fields.
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