Using Asynchronous circuits for Communications in Wireless Endoscopic Capsule Xiaoyu Zhang
Hanjun Jiang, Zhihua Wang
Department of Electronic Engineering Tsinghua University Beijing, China Email:
[email protected]
Institute of Microelectronics Tsinghua University Beijing, China Email: {jianghanjun, zhihua}@tsinghua.edu.cn
Abstract—An ultra-low-power baseband controller in wireless endoscopic capsule is designed in asynchronous circuits based on the 2-wire protocols. The controller is adaptive to different data rates defined by an external reference data rate clock source. Other than the ultra low power property, the controller has the advantages of high bandwidth utilization efficiency and low complexity. The interfaces for asynchronous handshake and baseband channel communication are improved so that it can work with other synchronous functional parts in the application system efficiently. The asynchronous controller implementation is 2.1K equivalent gates in standard 0.18um CMOS process. If working at 1.8V power supply, the IC core consumes 11.7uW at 2Mbps and 64.9uW at 12Mbps respectively. It proves to have about 60% area and 30% power consumption of the synchronous counterpart.
I.
INTRODUCTION
Power-limited mobile consuming electronic applications for digital communication technology are in a growing demand, and low-power and small-area baseband transceiver designs are greatly needed accordingly [1,2]. One of these applications is the wireless endoscopic capsule (WEC) which is a capsule-like medical device for the painless digestive tract examination [3]. The capsule must work inside the human body for 10-22 hours [3,4]. In this application, an ultra-lowpower baseband controller is greatly needed, which consists of a baseband transceiver and the interfaces to the control unit and baseband channel coding protocol in the application. In the baseband communication, the over-sampling technique is widely used, and it can easily be implemented in synchronous digital circuits. This technique has also been used for the previous version of WEC developed by Tsinghua University [4,5]. However, the baseband controller implemented in synchronous circuits requires quite large power consumption and large die area due to better quality of the over-sampling module. In contrast, the asynchronous communication does not have to extract (or recover) the data synchronous information in the transmission link. A simple 2wire interconnection can be used for implementing the
asynchronous communication, which can save a lot of power and die area compared to its synchronous counterpart. In this work, an asynchronous baseband controller is implemented based on the 2-wire asynchronous protocols: dualrail (regular) and level-encoded dualrail (LEDR). The dualrail is a well-known handshake protocol which encodes “request” into the data signals; in contrast, the LEDR protocol is not so common in control circuits but practical in communication link [6,7]. So we utilize the composite implementation to take advantages of both two protocols: dualrail for inter-module control (req and ack come in pairs for each operation) and LEDR for the communication link (ack don’t come with each data req, but only after one frametransmission done). The controller is implemented in the asynchronous digital circuit, which has the benefits of lowpower, self-clocked, low-EMI, and robustness to the physical parameters (voltage, temperature, RC, noise, manufacturing, etc.), and so on [6]. The overall power consumption of the controller can be greatly reduced compared to the previous versions in synchronous circuits by removing those powerhungry synchronous modules. The fabricated controller IC occupies only 2.1K equivalent NAND2X1 gates in standard 0.18um CMOS technology, which is only 60% of the previously implemented synchronous controller. Experimental results prove that the energy consumed per bit for this new controller can reach as low as 5.4pJ when operating at a speed of 12Mbps. This power consumption is only 30% of the previous synchronous one. This paper is organized as follows. The architecture of the asynchronous baseband transceiver and the principle of the dualrail protocols are given in Section II. The controller implementation details are presented in Section III at the module level. Section IV gives the experimental results. II.
ARCHITECTURE
A. Topview The proposed system architecture of WEC is mainly composed of a VGA CMOS image sensor, a digital baseband
module, a dedicated 2.4GHz wireless transceiver module[5], flash LED and batteries. The architecture of the baseband of the proposed wireless endoscope capsule is shown in Figure 1.
Figure.1 Architecture of WEC and the baseband controller
In the WEC application system, communication link has an unbalanced data throughput: More than 99% of the time of communication is used for sending image data while less than 1% is used for receiving commands. Considering about the unbalance transmitting and receiving time, a dedicated communication protocol is developed in order to increase the efficiency of communication and lower the power dissipation. The protocol stack can be divided into several layers: physical layer, link layer, MAC layer, transport layer and application layer. The first 3 layers of the whole protocol stack are implemented in asynchronous circuits: it effectively increases the communication reliability and lowers the power consumption at the same time [5]. The dashed-line block in fig.1 shows the asynchronous baseband controller module. The MCU and image processor are designed in synchronous circuits, which will take out the signal “data rate clock” for the 8-bit data bus, together with the control signals indicating “data valid” and “data rate”. When signals come from MCU to the baseband controller, they must meet the transition requirements of synchronous and the asynchronous circuit design. A 4-phase bundled-data (8 bits) handshake turns up at their interface for the internal control. If connected to the RF module in wireless communication or baseband direct interconnection, the other interface converts the asynchronous control to LEDR for link protocol almost seamlessly. The interfaces complete conversions not only between the control signals, but also between data signals of 8-bit (parallel) and 1-bit (serial). It is well known that the timing issue is one of critical issues of digital communication. If there is only 1-wire signal transmitted through the channel, the data clock (timing information) is not contained in the 1-bit data itself. One of the clock-extracting methods is over-sampling, which cause extra power consumption consequently. However, if we use 2-wire signal to make up the defect of 1-wire signal, the problem turns to be how to utilize the 2-wire signals more efficiently. There are several problems to solve: (a) the number of transitions in data clock/request for each data bit, which stands for the transmission efficiency measured by bit/symbol; (b) the power spectrum density (PSD) had better be equalized between the data wire and the clock/request wire for better utilization of bandwidth; (c) the unmatched delays of the two wires should be tolerated when smaller than one data bit period. The baseband channel coding protocol we used in this paper can solve all the problems above.
B. Physical layer & Link layer In the proposed system, the physical layer is in charge of sending, receiving data bits and correcting frequency; the link layer performs CRC check, bit-stream operation and extracts synchronization. Using asynchronous protocols in baseband controller can bring in benefits of low complexity of data synchronous modules due to asynchronous self-timed property. The conventional bundled-data handshake protocols cannot meet the requirement of baseband communication due to the unmatched delays in the request and data paths. The LEDR protocol is adopted to solve the problem of unmatched delays in asynchronous communications without any clock recovery circuitry. It is a channel coding method resembling the dual-rail protocol in asynchronous circuits. Its power spectrum density (PSD) after channel modulation and bit error rate characteristic are identical to those of Offset-QPSK.
Figure.2 2-wire link protocol (a) coding scheme table (b) constellation (c) state transition in constellation
The coding scheme of the LEDR-like protocol is shown in Fig 2(a)(b)(c). As shown in the constellation, when a ‘1’ is being transmitted, the 2-wire signals will rotate 90º clockwise, and they will rotate 90º counter-clockwise when a ‘0’ is being transmitted. Actually, the constellation is almost identical to that of O-QPSK (not symbol shaping yet), except for the special rotation directions. In Fig 2(a), d[1] and d[0] are the 2wire signals. The baseband protocol promises a continuous-phase characteristic by avoiding 180º phase change as shown in the constellation. For example, when “111001” is to be transmitted and ‘00’ is assumed as the initial channel state, the link-symbol code will be “00-01-11-10-11-01-11”, This coding scheme proves no error bit propagating that exists in Manchester coding. Also this protocol has a constant bitsymbol efficiency of 1bit/symbol. C. Transmitter & Receiver The transmitter consists of common modules so as to perform serialize conversion and some basic channel control, such as sending data in frame and CRC code. The serialize module receives 8-bit data from the control unit, covert them into the form of 1-bit data. When a transmission starts, the transmitter adds FCS at the head and calculated CRC at the tail of the frame. The data contain handshake-request information after 2-wire encoder. During receiving, the receiver must perform channel decoding as frame data extraction, CRC verification, parallelize conversion, etc. The modules are cascaded in a daisy-chain. Handshake request information can immediately be recovered from the incoming data “d[1]d[0]” after the 2-wire decoder. Then the regular 4-phase handshake takes place. If the frame-head detection is passed OK, request and data goes
in to the next module. CRC calculation of the frame data is executed while processing the parallel-to-serial conversion. When a frame accomplished, CRC verification can make sure the correctness of data received. III.
MODULES’ IMPLEMENTATION
A. Frame Sequence Detector In respect that data are transmitted and received in format of frames, they must be extracted out of frames before use. An asynchronous finite state machine (AFSM) is designed to detect the frame head sequence. The state transition of an 8-bit frame head sequence “01011010” is shown in Fig 3.
C. 2-wire Encoder/Decoder A sample encoder is illustrated in Fig 5(a), of which the left-hand side environment is asynchronous handshaking protocol (e.g. 4-phase bundled-data here) including “data”(1bit), “data req” and “data ack”, and the right-hand side environment is LEDR protocol. The output data must be at a certain bit rate in actual communication, so the data rate signal acts as a handshake signal. A sample decoder is given in Fig 5(a): “D” is the data value to transmit; “d[0]_next”/ “d[1]_next” is the next value in communication while “d[0]”/ “d[1]” is the current value already exists. The Boolean equation is: d [1] _next = D ⋅ d [0] + D ⋅ d [0]
(1)
d [0] _next = D ⋅ d [1] + D ⋅ d [1]
(2)
The encoder can easily include the functions of data-rate control and interface from 4-phase bundled-data to LEDR.
Figure.3 A sample: sequence detector state transition graph
B. Asynchronous Parallelizer & 1-hot index shifter Generally the serial data is written into the FIFO bit-by-bit, and read out in a certain format (e.g. byte), the problem is how to determine the proper occasion to read, since the inner asynchronous shifting-pipeline will take an uncertain time before stability. In order to overcome the defect, a “1-hot index shifter” and choice select elements are used to generate “gated-request” for the buffers (usually latches), as illustrated in Fig 4. Note that the signals “byte write”, “start shift” and “byte out valid” enclose handshake control signals, and the direction of the arrow shows request direction.
Figure.4 Asynchronous parallelize converter
The “1-hot index shifter” is a ring shifter with only one ‘1’ value inside, indicating the bit to be operated as a “bit-token”. Consequently, only 1 choice-select element which acts as the control logic of buffers is available at a time, though the input data tied to all the latches. So there is no bubbles, no rippletime when empty, and the problem of determining synchronous parallel output time can be resolved in this way. When the last bit of the byte has been prepared (‘index[0]’ of the shifter is ‘1’), The handshake “byte write” takes place. After all the 8-bit data go in to the byte-register, the data is ready for the synchronous part to read. The byte-register has plenty of time to wait for the sync central control module with an interval of 7 bit timing-span before the next refresh, under the selected data rate.
Figure.5 A sample: 2-wire (a) encoder, (b) decoder
The circuit of decoder may be a little complex compared with the encoder circuit. Firstly, a 2-phase handshake-request is made straightly from the encoded LEDR signals. There’s no need to recover data clock, just an XOR is needed to generate “request” of 2-phase bundled-data handshake instead. Secondly, if a 4-phase handshake used in the central block for data processing, the conversion from 2-phase to 4-phase handshake must be done. Thirdly, if error bits come out during the channel transmission, “completion detect” must be done additionally after decoding, to detect the only transmissionerror in this protocol: the 2-wire signals change simultaneously. At the last stage, bit error is checked. A sample decoder is shown in Fig 5(b): “d[0]in”/“d[1]in” is the signal just received, while “d[0]new”/“d[1]new” and “d[0]old”/“d[1]old” are buffered values; “D” is the decoded data to deal with for further processing: D = d [1]old ⊕ d [0]new = d [1]new ⊕ d [0]old (3) It is fine even if long sequences of zeros or ones in sequence to be transmitted because the 2-wire signal changes every bit transmission, whatever the data is. Compared with the synchronous counterpart, the power consumption of this design can be reduced to less than 20% at the 2Mbps speed.
D. CRC Cyclic Redundancy Check (CRC) is integrated in this controller to protect data from bit errors in transmission, protecting data from bit errors in data communication. Considering efficiency and complexity in implementation, the CCITT CRC-16 frame checked sequence (FCS) has been chosen, of which the polynomial is x16+x12+x5+1 and undetected error probability can be neglected when the BER is smaller than 10-5. Additionally, benefited from the LEDR
only 30% of that of the controller presented in [4,5]. Due to the leakage power loss, the average energy-per-bit get more when working at a low frequency, as in Fig.8 (b). 2
Power consumption (uW)
protocol used in communication link, there is no need to avoid long continuous 0’s or 1’s in the transmitted bits and no scrambler is required, thus bringing low complexity in circuits design. The implementation of CRC could be very different because of the storage elements. In the algorithm it is supposed to calculate the residual polynomial from all of the entire data to be verified. We use two implementations in the transceiver: 8-bit for transmission and 1-bit for reception.
10
0
10
-2
10
-3
10
-2
10
-1
10
0
10
(a)
EXPERIMENTAL RESULTS
Energy per bit (pJ/bit)
IV.
1
10 Data rate (Mbps)
60
The controller prototype has been implemented 2.1K equivalent gates totally in the standard 0.18um CMOS technology, which is only 60% of the synchronous controller in [4,5]. The chip die photo is shown in Fig 6. The core area is 200×230 um2,
40
20
0 -3 10
-2
10
-1
10
(b)
0
10
1
10 Data rate (Mbps)
Figure.8 Core power consumption at various data rates: (a) total power (b) energy per bit
CONCLUSION
Figure.6 Die photo of the chip
The experimental results show that the baseband controller works perfectly as expected. Though the operation speed is expected to reach 100Mbps, the controller is only measured up to 12Mbps due to limitation from the available instruments. The waveforms of the transmitted 2-wire signals and received/decoded data (lowest 2 bits) are captured and shown in Fig 7. The data rate for this measurement is 12Mbps. The measured waveforms match the simulation results quite well.
An asynchronous baseband controller is proposed and implemented based on the dualrail and LEDR protocol. The controller contains interfaces to RF and synchronous blocks. Benefited from the protocol and the design style of asynchronous circuits, the controller has the advantages of ultra low power and small die area. The implemented IC with interfaces to the synchronous modules works at a 1.8V power supply (I/O power supply 3.3V). The IC core consumes 11.7uW at 2Mbps and 64.9uW at 12Mbps, respectively. The energy-per-bit is 5.84pJ/bit at 2Mbps and 5.40pJ/bit at 12Mbps, respectively, which is only 30% of the synchronous counterpart. The asynchronous baseband controller has a core area of 200×230 um2, which is about 60% area of the synchronous counterpart. ACKNOWLEDGMENT The authors thank Liyuan Liu for his contribution to the asynchronous cell library. REFERENCES [1]
[2]
[3] [4]
[5]
Figure.7 Expected and measured waveforms of (a) the 2-wire encoded data, (b) the lowest 2 bits of decoded data
The measured power consumption data are shown in Fig 8. The controller core consumes 11.7uW at the speed of 2Mbps and 64.9uW at 12Mbps; the energy-per-bit is 5.84pJ/bit at 2Mbps and 5.40pJ/bit at 12Mbps. The power consumption is
[6]
[7]
John G.Proakis, ‘Digital Communication, 4th Edition’, McGraw Hill Higher Education, Dec 2000, ISBN-10: 0071181830, ISBN-13: 9780071181839. Leon W.Couch II, ‘Digital and Analog Communication Systems, 6th Edition’, Addison Wesley/Pearson, Jan 2001, ISBN-10: 0130812234, ISBN-13: 978-0130812230. Gavriel Iddan, Gavriel Meron, Arkady Glukhovsky, et al., “Wireless capsule endoscopy”, Nature, Vol.405, 25 May.2000, Page 417-418. Xiang Xie, Guolin Li, et al., “A Low-Power Digital IC Design Inside the Wireless Endoscopic Capsule”, IEEE Journal of Solid-State Circuit, Vol.41, No.11, Nov.2006, Page 2390-2400. Xinkai Chen, GuoLin Li, et al., “A Low-Power Digital Baseband for Wireless Endoscope Capsule”, IEEE International Symposium on Circuits and Systems (ISCAS) 2007, 28-30 May 2007, Page 4 pp. Jens SparsØ, Steve Furber, ‘Principles of Asynchronous Circuit Design – A Systems Perspective’. Kluwer Academic Publishers, Boston, 2001, ISBN 0-7923-7613-7. M.T. Dean et al. "Efficient Self-Timing with Level-Encoded 2-Phase Dual-Rail (LEDR)," Proc. ARVLSI, pp. 55-70, 1991.
