VLSI Architecture of Reduced Rule Base Inference for Run-Time Configurable Fuzzy Logic Controllers Bhaskara Rao Jammu1, Sarat Kumar Patra2 , Kamala Kanta Mahapatra3 1
Senior Research Fellow , Deptartment Of ECE, NIT Rourkela, Rourkela,India.
2
Professor, SMIEE, Department Of ECE, NIT Rourkela, Rourkela, India.
3
Professor, Department Of ECE, NIT Rourkela, Rourkela,India. {
[email protected];
[email protected];
[email protected]}
Abstract. In this paper, a new VLSI architecture is provided for the application of quad-input and dual-output Fuzzy Logic Controller (FLC) with maximum seven fuzzy membership functions. Our approach is based on classical three stage implementation process – fuzzification, rule inference and defuzzification cores. An innovative design methodology is proposed by splitting the process between DSP processor and FPGA to implement run time configurable FLC. Since the target application takes a maximum of 4 inputs and 7 membership functions, the rule base comprises of 2401 (74) rules. It increases the complexity of the overall system. To minimize this effect, rule reduction VLSI architecture is suggested to bind the no of rules to 16 (24). The Rule inference is designed for seeking the maximum frequency of operation for targeted Virtex 5 LX110T FPGA. The simulation results obtained with Modelsim 6.3g show satisfactory results for all test vectors. Keywords: FPGA, FLC, FSM, VERILOG, VLSI, hardware implementation.
1 Introduction In recent times fuzzy logic is addressing complex control problems such as robotic arm movement, chemical or manufacturing control process and automatic transmission control with more precision than conventional control techniques. The important principles inside the FLC have been broadly covered in the literature [1] [2]. Fuzzy logic is a methodology for expressing operation laws of a system in linguistic terms instead of mathematical operations. Fuzzy logic linguistic terms provide a useful method to define the operation characteristic of a system which is too complex to model accurately even with complex mathematical equations. The field of fuzzy systems and control has been making rapid progress in recent years. Due to practical success in consumer-product and industrial process control there has been rigorous research and development and theoretical studies.
J. C. Bansal et al. (eds.), Proceedings of Seventh International Conference on Bio-Inspired Computing: Theories and Applications (BIC-TA 2012), Advances in Intelligent Systems and Computing 202, DOI: 10.1007/978-81-322-1041-2_7, Ó Springer India 2013
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This has led to a tremendous increase in the amount of work in the field of fuzzy systems and fuzzy control. Due to the increased complexity level of the plant, the demand for controllers in the market is increasing day by day. In order to meet the market demand, controllers have to be designed according to the market needs. Some of the market needs highlighted are increasing in computational speed, decrease in computational complexity, ease of know-how of the product, easy working with the product and less turnaround time in terms of design. One of the best solutions to meet the above market demand is to switch over to a digital domain. The lookout for such a device, where thousands of gates can be incorporated ended up in Field Programmable Gate Arrays (FPGA). The application specific FPGA based architectures for FLC [3] [4] [5] show the maximum implementation efficiency in terms of silicon utilization and processing speed. In general, fuzzy logic is implemented in 3 phases. They are Fuzzification (Crisp input to fuzzy set mapping), Inference (fuzzy rule generation) and Defuzzification (fuzzy to crisp out transformation). This paper gives Very Large Scale Integration (VLSI) Architecture for general purpose Inference module suitable for all applications where as fuzzification and defuzzification are performed in DSP processor. The architecture includes the design for rule base reduction and the interface between the DSP and the FPGA to read and write the fuzzified and inference output data. This paper provides the design of all modules with its module level verification and FPGA implementation. The processor interface register information is provided for software programming. This paper is organized as follows: in section 2 provides a brief introduction to the specification of the generalized FLC. Section 3 describes the VLSI architecture of the rule base reduction module or inference module. Section 4 lists design choices we have made. Section 5 outlines the test bench and test vector generation. The developed model is simulated and synthesized as sketched in section 6. Finally, conclusions are presented in section 7.
Input Channels
DSP Processor
FPGA
Output Channels
Control Signal Data Bus
Fig. 1. System Platform to implement general purpose fuzzy logic controller.
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2 Specification Of Fuzzy Logic Controller The fuzzy logic controller proposed in this paper is standalone, configurable and generalized for any control application or requirement. Here the idea is to implement a run time configurable algorithm which can be configured according to requirement and can tune the parameters at any point of time. The main parameters and their limitations are given as follows: 1) 2) 3) 4) 5) 6) 7) 8)
No of inputs : maximum 4 (configurable) No of outputs: maximum 2 (configurable) Shape of membership function : Triangular No of membership function for each input and output : maximum 7 (configurable) Implication model: Mamdani Aggregation model: Mamdani Inference rules should be field programmable For each input variable, the overlapping degree of its membership function is a maximum of two.
Since the standalone configurable FLC hardware takes maximum four inputs, each with maximum seven membership functions. The rule base comprises of 2401 (74) rules and the fuzzification and defuzzification algorithms need more complex mathematical operations. Hence the complexity of the algorithm increases if the FLC is implemented in FPGA alone [6] [7] [8]. It is proposed in this paper that the data acquiring, fuzzification and defuzzification can accommodate by the DSP processor because of its proficiency in handling complex mathematical functions. The FPGA is selected to generate Rule Base and inference. The suggested platform for this model is shown in Fig. 1.
3 VLSI Architecture of reduced rule base module Once membership functions are defined for input and output variables a control rule base can be developed to relate the output actions of the controller to the observed inputs. This phase is known as the inference or a rule definition portion of the fuzzy logic. There are Nm (where N= No of Inputs and m= No of Membership functions) rules can be created to define the actions of fuzzy logic controller. This section gives VLSI Architecture of the rule base module for a generalized fuzzy logic controller with the specifications defined in the earlier section. The architecture also includes the interface between DSP and FPGA to program or to tune FLC parameters. Inside the inference we can observe that the design of rule base consists of 2401 (with Maximum of 4 inputs and 7 membership functions) rules and consuming much gate count in the FPGA, to reduce the device utilization one way is to reduce the no of rules in the rule base.
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w Fuzzifier
}
µ0 µ1 µ2 µ3 µ4 µ5 µ6
At most two are Non-Zero values
Fig. 2. The Fuzzification Unit
From limitation number 8 in specification mentioned in the previous section the fuzzifier gives two non-zero fuzzy term sets at most as seen in figure 2. Hence the no of rules will be reduced to 42 (for 4 inputs and 2 membership functions), Results in a reduction in logic utilization and improves the overall system performance, in our design we have achieved maximum frequency of operation as 175.809MHz. The rule selector unit outputs these two fuzzified values with its Index number and its fuzzy value. The index number is used by the address generator to generate activated rule with respect to linguistic variables. Fuzzy value is used by the inference engine with Mamdani max-min inference rule. The proposed VLSI architecture (see Fig. 3) for a rule base module with rule reduction includes five principal units: 1) Rule selector unit to select non zero fuzzy term set; 2) An address generator unit which generates an address to read the appropriate active rule; 3) Rule base memory unit to store the user defined rules, provision is provided to program at any interval of time. 4) An inference engine unit which performs approximate reasoning by associating input variables with fuzzy rules. 5) The CPU registers unit is memory with 32 bit data width is used to store fuzzified values for four input variables, inference output values and Register to program no of inputs and no of membership functions (Tuning parameters). 6) Here the inference engine involves in another sub-block which performs Mamdani min-max implication operation and calculates the degree of applicability of all active rules selected from the rule base memory by address generator. The results are stored in the CPU registers for defuzzification process. Typically the DSP processor and FPGA runs in different clock frequencies interrupt handler is used here as a status flag to tell internal state machine that new data is available. Subsequently a Finite State Machine (FSM) within the FPGA can use the interrupt handler to generate an interrupt to DSP Processor. The architecture specifies 32 bit memory
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space is in Table I. The rule reduction algorithm used in this architecture is given in Fig. 4. µ10 µ11 . . µ16 µ20 µ21 . . µ26 µ30 µ31 . . µ36 µ40 µ41 . . µ46
Rule Selector 1
Index No
Rule Address Generator
No Of Inputs No Of MFs
Address to Read Rule Selector 2
Rule Selector 3
Rule Selector 4
RuleFill
ConfigReg FSM Controller
No Of Inputs No Of MFs
Rule Base Memory Valid Rules Inference Engine
Index Value Inference Output MF's Fill CPU Register Registers Fill & ISR
Reading µ10 to µ46 & Cpu Registers
Fig. 3. VLSI Architecture of the Reduced Rule Base
4 Design Choices of Internal Modules As we have discussed from previous section the rule base is filled with 2401, the software fills this data with address from 0 to 2400. To read the appropriate rule for non-zero fuzzified values it needs to generate matching addresses with its index numbers. For example if non-zero value of input 1 is with index numbers 1 and 2, input 2 is 2 and 3, input 3 is 4 and 5, input 4 is 5 and 6, it needs to read the rule addresses as shown in Fig. 5. The module rule address generator from Fig. 3 arranges index numbers to address shown in Fig. 5 with the programming value of no of inputs, if no of inputs are 4 the rules are 16 and to 3 inputs rules become 8 and to 2 inputs rules become 4. The address generator module does the mapping of the rule index with the rule base
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address (filled by the software). Part of the VERILOG code to evaluate rule address to match with rule base memory addresses is provided in Fig. 6.
Begin
Read Fuzzy & Register Data Wait for Interrupt
Zero Non-Zero Values
Select Non Zero Fuzzified Values Data Valid Generation of Address to read from rule base Address Valid Read Rule Base Data Reduced Rules
Enable Inference
Write Inference data into memory & clear Mask
Fig. 4. Rule Reduction Algorithm for VLSI Implementation
001010100101 1 2 4 5 001010100110 1 2 4 6 001010101101 1 2 5 5 001010101110 1 2 5 6
1 1 1 1 2 2 2 2
3 3 3 3 2 2 2 2
4 4 5 5 4 4 5 5
5 6 5 6 5 6 5 6
2 2 2 2
3 3 3 3
4 4 5 5
5 6 5 6
Fig. 5. Addresses of rules
The module rule address generator from Fig. 3 arranges index numbers to address shown in Fig. 5 with the programming value of no of inputs, if no of inputs
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are 4 the rules are 16 and to 3 inputs rules become 8 and to 2 inputs rules become 4. The address generator module does the mapping of the rule index with the rule base address (filled by the software). Part of the VERILOG code to evaluate rule address to match with rule base memory addresses is provided in Fig. 6. Table 1. Memory Space SI. No
Memory Information Address
Access
0X00H to 012D 012E to 0137
Read
Name
Description
3
0138
4
0139
Read
ISR
2401 Rules are filled in this Memory 28 fuzzified values, inference output values No of Inputs, No Of Membership functions for input and output Interrupt status register
013A
Read/ Write
IMR
Interrupt Mask Register
1 2
5
Read/ Write Read
NRULE FUZZYV CONTROL REG
The block model of the rule evaluator along with index values is shown in the Fig. 7. Based on the inputs the decision of which output is to be chosen is decided here. This module consists of the two memories one memory is used to read the reduced rules continuously to find maximum values. Another memory is stored with minimum values of corresponding Index values of rule selector. In this design memories have been chosen to utilize the memory blocks in the FPGA and to reduce the logic count and corresponding delay and power dissipation. Provision is provided for all parameters in the design unit using `define and ìfdef compiler directives provided by VERILOG [7]. if (RuleIndex[11:3] == 0) RuleAddress
