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Wireless Security System
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Video Capture Overview. Camera. ADV7185. Composite In tv_in_ycrcb. [19:0]. Clock_27MHz tv_clock. Memory. Controller. Dual-Port. Block. Memory. VGA.
Wireless Security System
Noel Campbell Vivek Shah Raymond Tong
Video Surveillance Block Diagram
Video Capture Overview Clock_27MHz
Y isolator
Y [7:0] 8
Clock_27MHz
WE
ADV7185
Memory Controller
Camera
X ADDR
Dual-Port Block Memory
Composite In 20 tv_clock
tv_in_ycrcb [19:0]
ycrcb [29:0]
Y
30
encode_busy writing_memory
NTSC Decoder
Async FIFO RGB
YCrCb to RGB Converter
VGA Controller
Display
Z
Syncing and blanking signals
Technical Considerations
Synchronization of data ADV7185
Displaying data in VGA Acquire
clock vs lab kit 27 MHz clock
240 X 240 real time video
Write data to block memory then continuously read from it
Memory Controller Write
a frame worth of data into block memory for encoding and transmission
Video Compression Discrete Cosine Transform
512 bits/block 56 bits/block
Inverse Discrete Cosine Transform
Video Encoder DCT Coefficients
Dual Port Block Memory (64x900) Dual Port Block Memory (64x900) Dual Port Block Memory (64x900) Dual Port Block Memory (64x900)
144
64 Dout
288
Matrix_int0
144
64 Dout
Matrix_int1
Multiplier Block
8
DCT Coefficients
64 Dout
64 Dout
144
288
Adder Block And Truncate Module
144
Multiplier Block
288
Adder Block
Matrix_int2
144
288
Matrix_int3 Address (10) and WE
Address (10)
Line_write (5)
Finite State Machine
Encoding_line (10)
Wireless_busy
Dual Port Block Memory (80x900)
Wireless Transmission
Data is sent serially from the labkit to the wireless kit
Data is assembled into packets and sent from camera-end to fixed-end via CC2420 radio
Data is then sent serially from receiver wireless kit to the receiver labkit
Transmitter from encoder
Transmitter Control Unit 80 x 900 Dual Port BRAM
80
Shift Register
8
RS232 Sender
serial cable
Radio Transmitter
to receiver
FPGA
microcontroller
Receiver from transmitter
Transmitter Control Unit Radio Receiver
80 serial cable
RS232 Receiver
Shift Register
80 x 900 Dual Port BRAM
to decoder
microcontroller
FPGA
Video Decoder DCT Coefficients
144
80
Registers (80)
DCT Coefficients
Dout
144
288
64
144
288
64
Matrix_int0 Multiplier Block 144 Matrix_int1 Multiplier Block
Adder Block 144
288
64
Dual Port Block Memory (64x900)
144
288
64
Dual Port Block Memory (64x900)
Address LINE_DONE (5)
Ready Block_done
Dual Port Block Memory (64x900)
Adder Block
Address (10) and WE Finite State Machine
Dual Port Block Memory (64x900)
LINE_READ (5)
Video Display Overview Clock_27MHz to all modules Y [7:0]
Dual-Port Block Memory
Addr
8
RGB
YCrCb to RGB Converter
Display Delay
X Z
decode_done
Memory Controller
VGA Controller
Syncing and blanking signals
* Only chrominance (Y) is important if displaying grayscale image
Z
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