The VHSIC Hardware Description Language (VHDL) was created for the
purposes of ... Ashenden, P. J., The Designer's Guide to VHDL (2nd Edition),
Morgan ...
EECE 443 - Hardware Design with VHDL or VHDL: The Language and Its Applications Instructor: L. H. Pollard Office: ESL 330 Office Hours: Mon & Wed 1-2 PM
e-mail:
[email protected],
[email protected] Phone: 277-5982 (Other times by appointment.)
The VHSIC Hardware Description Language (VHDL) was created for the purposes of documentation and communication with respect to hardware systems. The language was created with features specifically crafted to represent the complexities of digital hardware and systems, from the intricacies of clocked systems, parallel operations, and signals on buses to the high level abstractions of floating point numbers and data structures. Thus, the language can be utilized to represent digital systems at the gate level, at the register level, at the chip level, or the system level. This semester we will examine the language and how it represents digital systems at these various levels. We will also examine how this enables us to become better designers, and better communicators. With an ability to represent the systems at various levels in a precise manner, it is also possible to create simulation systems which will accept as input a digital system described in VHDL and simulate the action of the system to verify that the design functions as desired. It is also possible to create synthesis systems to implement specific digital systems from a VHDL description. We will become familiar with VHDL by studying the language and its features, then using the language to represent and simulate digital systems at various levels. Thus, the homework will consist of creating VHDL representations of digital systems, then simulating those systems. We will work at various levels, from the lower (gate) level representations to the higher (system) level representations. There will be a final project at the end of the semester. Of particular interest for the class will be preparation of VHDL representations for synthesis purposes. The VHDL system that we will utilize is the ModelSim system available with the Mentor Graphics tool suite available on many of the department PC systems (check those in EECE 211). If you have access to another system and wish to use it, that will generally be okay, but be aware that not all VHDL systems have the same characteristics. Hence, I may not be able to help you resolve an error in a system with which I am not familiar. In order to access the ModelSim system, you will need an account on the EECE systems. Grading: • • • •
Homework: 35 % Semester Project: 15 % Mid-Term Exams: 25 % Final Exam: 25 %
Textbook: Pong P. Chu, RTL Hardware Design Using VHDL, Coding for Efficiency, Portability, and Scalability, John Wiley & Sons, 2006. Reference Books: J. R. Armstrong & F. G. Gray, VHDL Design; Representation and Synthesis, 2nd Ed, Prentice-Hall, 2000. Ashenden, P. J., The Designer's Guide to VHDL (2nd Edition), Morgan Kaufmann Publishers, 2001. Bhasker, J., A Guide to VHDL Syntax, Prentice-Hall, 1995. Bhasker, J., A VHDL Primer, 3rd Edition, Prentice-Hall, 1999.
Topics to be covered: Fundamental Concepts Modeling concepts and methodologies Levels of representation/action Syntax and Semantics of VHDL Signals and variables Overloading Testing of VHDL modules Scheduling Algorithm and its implications Data representation Numeric (integer, fixed point, floating point) Physical Enumeration Logical (bit, byte, bus) Composites: putting elements together Architectures and entities Communication between modules Communication within modules Encapsulation strategies Sequential vs. concurrent statements Processes and sequential constructs Blocks and concurrent constructs Multiple connections: resolved signals and their uses Mechanisms for modeling open collector/tri-state Multiple values: digital approximation of analog reality Resolution functions Sense and drive functions Other uses of resolution mechanisms Modeling methodologies and their uses Behavioral mechanisms Structural mechanisms Algorithmic level design Register level design Gate level design Multilevel design Combinational system techniques Sequential system techniques Design for cooperation and re-use Libraries and packages Use statements Visibility of identifiers Configurations Use of multiple clock domains Synthesis Strategies Synthesis of VHDL descriptions Strategies for large systems Strategies for high speed systems I/O in VHDL File I/O Formatted I/O Text I/O
