ESTIMATION OF THE USEFULNESS OF TEST VECTOR COMPONENTS FOR DETECTING FAULTS RESULTING FROM SHORTS IN STANDARD CELLS M. BLYZNIUK (1), W. PLESKACZ (2), M. LOBUR (1), W. KUZMICZ (2) STATE UNIVERSITY “LVIVSKA POLYTECHNICA”, UKRAINE (2) WARSAW UNIVERSITY OF TECHNOLOGY, POLAND
(1)
KEYWORDS: Spot Defects, Critical Area, Shorts Faults, Functional Faults, Faults Identification, Test Vectors ABSTRACT: This paper proposes a new methodology for estimation of effectiveness of the test vector components for detecting faults resulting from shorts in digital CMOS standard cells. This methodology is based on the developed approach of identification and probability of occurrence estimation of different types functional faults caused by spot defects in conductive layers of VLSI circuit layout. The application of this methodology is demonstrated. Estimation of usefulness of the test vector components for detecting identified functional faults resulting from shorts in digital gates from an industrial standard cell library has been shown.
1. INTRODUCTION Traditionally when the problem of estimation and decrease of the influence of spot defects on IC manufacturability is solved the faults resulting from shorts and opens (caused by this defects) are considered as the faults that are always fatal. On the one hand, it does not matter for schematic and layout designers what type of functional fault will be caused by shorts and opens. It is quite enough for them to know that such fault is fatal, i.e. circuit does not perform its own function. On the other hand, the information about types of functional faults (caused by shorts and opens) and their probability of occurrence is important for the developers of VLSI circuits tests [4]. As a result of shorts and opens caused by spot defects the different types of faults may occur in standard gates, for example: a) the result of shorts is stable one on the output Q of the gate (ST1); b) the result of shorts is stable zero on the output Q of the gate (ST0); c) the result of shorts modify the function of the gate, for instance from Q=not(A+B+C+D) for 4-INPUT NOR gate to Q=not(A*B+C+D) or to Q=A*(not(B+C+D)) or to Q=not(A+C+D)) and so on [5]. The information about types of functional faults and their probability of occurrence for certain gates of VLSI circuits would help and improve the work on development and generating of test cycles. Using this information we were able to foresee the effectiveness of test vector components and to find their optimal sequence for detecting faults caused by spot defects. If we take into account that the model of probability of occurrence of various functional faults caused by shorts and opens in a real gate is layout-driven, the effectiveness of test vector components for detecting this faults will be determined not only by the logic function of the gate, but also by its physical design. The main goal of this work is the development the methodology for estimation of usefulness of the test vector components for detecting faults resulting from
shorts in conductive layers of an IC layout.
2. ESTIMATION USEFULNESS METHODOLOGY This work is limited to estimation of the effectiveness of the test vector components for detecting faults resulting from shorts caused by spot defects in conductive layers of standard gates only.
2.1. Estimation of Probability of Occurrence of Different Functional Faults 2.1.1. Identification of faults types. Obviously it is necessary to perform the analog circuit simulation for all possible shorts (double Shdouble, triple Shtriple and shorts of higher order) between nets (nodes of schematic) using circuit simulator to determine all possible types of faults in a gate. Taking into account the fact that probability of occurrence of shorts of order higher than double is very small we can neglect these shorts. For identification of types of faults caused by double shorts we introduce the concept of symbolic matrix of functional fault types FTF with the dimensions [ N Net × N Net ] where the matrix element fTF =" type short fault" , i ≠ j is the type of fault ij
caused by shorted Neti with Netj. The type of short fault is determined by the results of comparison of waveforms obtained from analog simulation of gate with shorted nets and gate without faults. The technique of identification of types of faults caused by shorted nets are described in more detail elsewhere [6].
FTF=
Net2
0
"ST1"
Net2
"ST1"
0
.
"ST0"
L
L
.
L
.
"ST0"
Neti
Q=(A*B+C+D)
"ST0"
.
0
.
"ST1"
"ST0" "ST1"
. .
L 0
NetN
L "ST0"
Neti
Net1 Net1
. Q=(A*B+C+D) .
. L Q=A*(B+C+D) .
NetN
"ST0"
. Q=A*(B+C+
critical area for certain defect radius from the given layout [5]. Figure 1 shows the example of critical area extraction. The probability of short for certain defect radius may be determined geometrically as Psh( R ) = S CrAr( R ) / S GtAr where S GtAr – gate area. Figure 2 shows the dependence Psh( R ) obtained for the POLY1 layer of 0.8 µm CMOS NOR4 gate. POLY: Critical area:
Net A Net B Net C Net D Net Q
SA&B SB&C SC&D SA&Q
0,8
0,00025
Defect radius probability density function pdf(R) Total probability of faults short Product of probability of faults short and defect radius probability density function
0,7
0,0002
0,6
Psh(R)
0,5
Pdf(R)
0,00015
Pdf(R) Psh(R)
0,4 0,0001
Psh(RSTART - RSTOP)
0,3 0,2
0,00005 0,1 0
0 0 0,1 0,2 0,3 0,4 0,5 0,6 0,7 0,8 0,9 1 1,1 1,2 1,3 1,4 1,5 1,6 1,7 1,8 1,9 2 2,1 2,2 2,3 2,4 2,5 2,6 2,7 2,8 2,9 3 3,1 3,2 3,3 3,4 3,5 3,6 3,7 3,8 3,9 4
RSTART
a) Complete layout of NOR4 gate designed in 3µ m CMOS technology [2].
b) POLY 1 layer layout with double shorts critical area for Rdanger=2.1µ m.
Fig.1. Model of layer with critical area. As a result of comparison we can identify the types of faults and form the symbolic matrix FTF : The example of such determined symbolic matrix of functional faults types caused by nets shorted on METAL 1 layer for NOR4 gate from an industrial standard cell library in 0.8 µm CMOS technology is given in Table 1. Table 1. Functional fault types for NOR4 gate Net[1]=A Net[1]=A
Net[2]=B
Net[3]=C
Net[4]=D
not((A*B)+C+D) not((A*C)+B+D) not((A*D)+C+B)
Net[5]=Q
Net[6]=Vdd
Net[7]=Vss
A*(not(C+B+D))
ST0forQ
not(B+C+D)
RSTOP
Defect radius R [um]
Fig.2. Determination of the total probability of fault shorts caused by spot defects. Obviously if we take into account that the defect probability distribution quickly falls off as the defect size increase, it is much more likely for short to occur for small defect radius than for a large one. The product of defect probability density function Pdf ( R ) and probability of short occurrence Psh( R ) allows to determine the most dangerous defect radius for certain layer of a layout [1]. The total probability of short fault occurrence PShT otal can be calculated as: RST OP
òD
PSh ( RSTART ≤ R ≤ RSTOP ) =
0
Total
× Psh( R ) × Pdf ( R ) dR
R START Net[2]=B
not((C*B)+A+D) not((D*B)+C+A)
B*(not(A+C+D))
ST0forQ
Net[3]=C
not((C*D)+A+B)
C*(not(A+B+D))
Notshorted not(A+B+D)
D*(not(A+B+C))
ST0forQ
Net[4]=D Net[5]=Q Net[6]=Vdd
ST1forQ
not(A+C+D)
not(A+B+C) ST0forQ Notshorted
Net[7]=Vss
“Not Shorted” in Table 1 indicates that symbolic matrix was formed taking into account the probability of short between certain nets of the gate, i.e. probability of short between given nets equals zero and fault caused by this short is not considered. 2.1.2. Probability of occurrence estimation of identified faults. Determination of the total probability of short fault occurrence is usually based on the development of the defect placement methods or region expansion methods [3] (i.e. development of model of critical area of layout for shorts [1]). In our work the model of critical area was used [1]. This model reflects the dependence of critical area value for shorts SCrAr on the value of spot defects radius R. This dependence is obtained not analytically but on the basis of computer experiment with the use of the developed software tools which allow to extract the
where R ST AR T ÷ R ST OP – region of variation of the defect radius in computer experiment; D0 – density of spot defects [N/cm2]. The Pdf ( R ) and D0 are determined using statistical information from fabrication process or from published literature [1,3] . Traditionally modelling of the probability of fault resulting from shorts is accompanied by determination of the total probability of short. Analysis of subdivision of probability caused by shorts between nets is not undertaken. Generally PShT otal consists of probabilities of shorts between nodes PSh
N eti Net j
where PS h
N et i N et j
, i = 1, N Net ; j = 1,N Net ,
is the value of probability of shorts
between i-th and j-th net. So, the concept of matrix of subdivision of probability of short fault caused by shorts between nets PSh with the dimensions [ N Net × N Net ] should be introduced. The element of the matrix PSh is determined as: PSh
Neti &NetJ
( RSTART ≤ R ≤ RSTOP ) =
RSTOP
ò D ×P 0
ShNeti &NetJ
( R) × Pdf ( R) dR .
RSTART
Using model of critical area for determination of the
total probability of short fault occurrence the probability of short between i-th and j-th net for certain defect radius may be determined geometrically as ( R) Psh ( R ) = SCrAr ( R ) / SGtAr , where SCrAr Neti &Net j
Neti &Net j
Neti &Net j
Net[1]=A
0
Net[1]=A
Net[2]=B
Net[3]=C
Net[4]=D
0,000439 0,000054 0,000001 0 0,000399 0,000043 0 0,000475 0
Net[2]=B Net[3]=C Net[4]=D Net[5]=Q
Net[5]=Q
Net[6]=VDD Net[7]=VSS
0,000168 0,000132 0,000204 0,000867 0
0,000188 0,000026 0 0,000035 0,000542 0
Net[6]=VDD
is the value of critical area between i-th and j-th net. Figure 3 demonstrates graphically the determination of the elements of the matrix subdivision of probability of short fault caused by shorts between nets on POLY 1 layer for NOR4 gate from an industrial standard cell library in 0.8 µm CMOS technology. 0,00016 0,00014
Pdf(R)*Psh_A&B
Pdf(R)*Psh_A&C
Pdf(R)*Psh_A&D
Pdf(R)*Psh_B&C
Pdf(R)*Psh_B&D
Pdf(R)*Psh_C&D
0,00012 0,0001 0,00008 0,00006
PSh NetB&NetC
0,00004
Net[7]=VSS
0,000043 0,000035 0,000033 0,000026 0,000863 0 0
2.1.3. Probability estimation of different functional faults. Matrix of subdivision of probability of short faults PSh and the matrix of the identified types of functional faults FTF allow to estimate the probability of occurrence of the different functional faults resulting from shorts caused by spot defects in standard gate. These matrices are symmetric matrices and matrix FTF may contain equal elements, i.e. some shorts between nodes will cause the identical type of functional fault. Namely for a given standard gate some non-diagonal elements will be equal, for example fTF = fTF =" ST1" , i > j , k > l, ( i ≠ k ) ∨( j ≠ l) . In this ij
kl
0,00002 0 0 0,1 0,2 0,3 0,4 0,5 0,6 0,7 0,8 0,9 1 1,1 1,2 1,3 1,4 1,5 1,6 1,7 1,8 1,9 2 2,1 2,2 2,3 2,4 2,5 2,6 2,7 2,8 2,9 3 3,1 3,2 3,3 3,4 3,5 3,6 3,7 3,8 3,9 4 4,1 4,2 4,3 4,4 4,5 4,6 4,7 4,8 4,9 5
Defect Radius [um]
Fig.3. Determination of the elements of the matrix subdivision of probability of short faults caused by shorts between nets. The diagram presented in Figure 4 clearly demonstrates the significant differences between probabilities of shorts between nets on METAL 1 layer for NOR4 gate designed in 0.8 µm CMOS technology. Net[1]=A Net[2]=B Net[3]=C Net[4]=D Net[5]=Q Net[6]=VD D 0,00 09
Net[7]=VS S
0,00 08 0,000 7 0,0006
case the probability of occurrence ST1 type fault equals the probability of fault shorts between i-th and j-th net plus the probability of fault short between k-th and n-th + PSh . net: PST 1 = PSh N et i N et j
N et k N et l
Number and value of non-equal elements (excluding “Not shorted”, see Table 1) of upper triangular matrix of FTF allow to determine the types of functional faults in a gate and to form the vector Ftype (probable types of functional faults resulting from shorts caused by spot defects). For example:
{
}
Ftype = " ST1" ," ST0" ," A ×( B +C + D)" ,"( A × B +C + D)" ,...," Type of fault" .," Other"
Element “Other” in the vector Ftype means that for some gates the shorted nets may cause not detectable type of functional faults. The main result is the vector formation of subdivision of probability between types of functional faults caused by shorts:
{
Ptype = PS T 1 ,PST 0 , PA ×( B +C +D ) ,P( A × B +C + D ,..., Ptype of
0,0005 0,000 4 0,00 03 0,0002
N et[7]=V S S
0,0001
Net[6]=VD D
0
Net[3]= C
,...,POther
}
Figure 5 illustrates the determined vector of subdivision of probability between identified types of functional faults caused by shorts between nets on METAL 1 layer for NOR4 gate designed in 0.8 µm CMOS technology. 0,0012
Net[1]= A Net[7]=VSS
Net[6]=VDD
Net[2]=B Net[5]=Q
Net[4]=D
Net[3]=C
Ne t[4 ]=D Net[2]=B
Net[1]=A
Ne t[5 ]=Q
fault
0,001
0,0008
0,0002
ST1 for Q
not(A+B+C)
not(A+B+D)
D*(not(A+B+C))
C*(not(A+B+D))
not(A+C+D)
not((C*D)+A+B)
B*(not(A+C+D))
not((D*B)+C+A)
not((C*B)+A+D)
ST0 for Q
not(B+C+D)
A*(not(C+B+D))
0
not((A*D)+C+B)
Table 2. Matrix of subdivision of probability of short faults.
0,0004
not((A*C)+B+D)
The results of calculation of the matrix of subdivision of probability between short faults on METAL 1 layer for NOR_4 standard gate are presented in Table 2.
0,0006
not((A*B)+C+D)
Fig.4 Diagram of subdivision of probability between short faults resulting from nets shorted on METAL 1 layer for NOR_4 standard gate.
Fig.5 Diagram of subdivision of probability between
types of functional faults caused by nets shorted on METAL 1 layer for NOR4 gate. The application of the proposed technique of estimation of probability of different functional faults is demonstrated on the example of analysis standard gates from an industrial standard cell library in 0.8 µm CMOS technology: NOR_4, NO42, NAND_4, AND_2/NOR_3, and AND_2,2/NOR_2. The conditions of experiment were the following: interval of defect radius range - [0 µm - 5 µm]; value of defect radius step 0.1 µm; density of spot defects D0 =1 on gate area; layer of investigation – Metal 1 layer. After data processing we obtained the vector of identified functional faults and their occurrence probability for NAND_4, AND_2/NOR_3, and AND_2,2/NOR_2 standard gates. These results are presented in Table 3, 4 and 5. Table 3. Identified functional faults and their occurrence probability for NAND_4. not[((A*B)+(A*C)+ (B*C))*not(D)]
not[((A*B)+(A*D)+ (B*D))*not(C)]
not[((A*C)+(A*D)+ (D*C))*not(B)]
not[((C*B)+(B*D)+ (C*D))*not(A)]
0,000074
0,000156
0,00023
0,000751
0,001227 Not detected
0,000492 ST0 for Q
0,001196 ST1 for Q
0,000032 not(C*B*D)
0,000032 not(A*C*D)
0,000072 not(A*B*D)
Probability
0,000166 not(A*B*C)
Functional faults
NAND_4 Standard Gate: Q=not(A*B*C*D)
detecting identified faults and determination of their usefulness are possible. For determination of the usefulness of test vector components we introduce the concept of matrix TV of components of test vector for detecting the identified types of functional faults caused by shorts between nets. This matrix has the dimensions [ N Net × N Net ] . The
{
}
matrix element tV = V 1 ,...,V q , i ≠ j contains qij ij
ij
components of test vector which may detect the type of fault caused by shorted Neti with Netj (excluding undetectable faults for which qij=0). Depending on the type of functional fault and on the logic function of the gate the fault may be detected by several components of test vector (minimum one component - qij =1 up to qij = N V , where NV is the dimension of test vector V ). For
example,
element
of
matrix
tVDQ = {V 1 ,V 2 } = { 0000 , 0001 }
TV
for
equals detecting
functional fault Q=D*(not(A+B+C) caused by shorted NetD & NetQ in NOR_4 standard gate. Matrix TV is determined by: the symbolic matrix of identified functional faults FTF , matrix of subdivision of probability of short fault PSh and T Det - matrix of the abilities of test vector components to detect. The last matrix has dimensions [ N V × N Sh ] , where the double
Table 4. Identified functional faults and their occurrence probability for AND_2/NOR_3.
not((A*B)+C)
SA1 for Q
0,000003
0,000242
SA0 for Q 0,000787
D*(not((A*B)+C))
not(A+C+D) 0,000002
not((A*B)+D)
B*(not(C+D)) 0,000126
0,000597
not((B*D)+C) 0,00004
D*(not((A*B)+D))
not((B*C)+D) 0,000386
0,00029
B*(not(A+C+D)) 0,000274
0,000004
not(C|D) 0,000097
not((A*B)+(C*D))
not(B+C+D) 0,000004
(B*C)+(B*D)+(C*D))
A*(not(C+D)) 0,000037
0,000494
not((A*C)+D) 0,000025
not((A*B)+(A*C)+(A*D)+
A*(not(B+C+D))
ij
vector could detect j-th short fault and vice versa t Det = 0 . N S h is the number of non-zero elements ij
0,000086
Not detected
0,000225
Functional faults Probability
0,001125
AND_2/NOR_3 Standard Gate: Q=not((A*B)+C+D)
matrix element t Det = 1 when i-th component of test
double
in the upper triangular matrix of subdivision of probability of short fault PSh , i.e. number of probable nets shorted. Example of technique for determination of the elements of matrix T Det is given in Table 6. Grey cells in Table 6 indicate that corresponding element t Det will equals 1. ij
Table 5. Identified functional faults and their occurrence probability for AND_2,2/NOR_2. AND_2,2/NOR_2 Standard Gate:
Table 6. Fragment of table of gate output values resulting from shorts for NOR_4 standard gate.
not(A+(C*D))
not(C*D)
not((A*C)*(B+D))
not((A*D)*(B+C))
A*(not(B))
A*(not(C*D))
not(B+(C*D))
not(A+B+D)+ (C*(not((A*B)+D)))
C*(not(A*B))
not(A*B)
not(A+B+C)+ (D*(not((A*B)+C)))
D*(not(A*B))
0,000008
0,000166
0,000461
0,000061
0,00018
0,000121
0,000001
0,000095
0,000158
0,000024
0,000036
0,000696
SA1 for Q
B*(not(C*D)) 0,000035
0,000067
B*(not(A)) 0,000202
0,00118
not((B*D)*(A+C)) 0,000004
fault
not((A*B)+(B*C*D)+ (A*C*D)) not((C*D)+(A*B*D)+ (A*B*C))
not((B*C)*(A+D)) 0,000048
Quantitative estimation of the Ptype of
0,000669
Not detected 0,00083
Probabilit
Functional faults
Q=not((A*B)+(C*D))
values in
Ptype vector will allow to determine the usefulness of
components of test vector for detecting identified types of functional faults.
2.2. Estimation of The Usefulness of Test Vector Components When the types of functional faults result from shorts are identified and their probabilities are determined too, the determination of the components of test vector for
Psh_A&B
Psh_A&C
Psh_A&D
TestVect
Qtrue
Qfalse
not((A*B) +C+D)
not((A*C) +B+D)
not((A*D) +C+B)
A*(not(C+ B+D))
Psh_A&Q Psh_A&Vdd Psh_A&Vss Psh_B&C
0000 1000 0100 0010 0001 1100 1010 1001 0110 0101 0011 1110 1011 0111 1101 1111
1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0
1 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0
1 1 0 0 1 0 0 0 0 0 0 0 0 0 0 0
0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0
ST0forQ not(B+C+D) not((C*B) +A+D)
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0
1 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0
Element of matrix TV is determined by corresponding column of matrix T Det . The results of such determination of matrix TV for NOR_4 gate are presented in Table 7. Table 7. TV matrix of test vector components for detecting types of functional faults for NOR_4 gate
Net[1]=A Net[2]=B
Net[3]=C
Net[4]=D
Net[5]=Q
1000,0100 1000,0010 1000,0001 0000,1000 0100,0010 0100,0001 0000,0100 0010,0001 0000,0010 0000,0001
Net[1]=A Net[2]=B Net[3]=C Net[4]=D
Net[6]=Vdd
Net[7]=Vss
0000 0000 Not shorted 0000
1000 0100 0010 0010
1000,0100,0010,0001,1100, 1010,1001,0110,0101,0011, 1110,1011,0111,1101,1111
Net[5]=Q Net[6]=Vdd
0000 Not shorted
Net[7]=Vss
{
P = P − ((( P Sh V V m
m
Neti Net j
m=1,NV ,m≠ h.
Step 3. Remove the faults that are detected by h-th test vector components from symbolic matrix of faults FTF
(remove f
if Vh = tV ij (Vk ) , k = 1,qij ) ,i = 1,( N Net − 1)) , j = ( i + 1),N Net )
TFij
Elements of matrix TV indicate that some faults may be detected by several components of test vector (see Table 7) and on the contrary elements of matrix T Det indicate that some components of test vector detect several faults (see Table 6). So, we can estimate the effectiveness ( PV ) of test vector components for detection of identified functional faults. To do this we sum the probabilities of functional faults detected by certain component of test vector: PV =0, PV = PV
(((0 if Vm ≠tV (Vk ),k =1,qij ),i =1,( NNet −1)), j =( i +1),NNet ) ij
+
((( PSh if Vm =tVij(Vk ),k =1,qij ),i =1,( NNet −1)), j =( i +1),NNet )
}
if Vh =tV ij(Vk ),k =1,qij ),i =1,( NNet −1)), j =( i +1),NNet ) ,
Step 4. Let PU = PV . h
h
Step 5. Let PV = 0; h
Step 6. If number of iteration is less than (Nv-1) we return to Step 1. The results of estimation of the usefulness of test vector components for NOR_4 gate by described algorithm are presented in Table 9. Table 9. Usefulness of the test vector components in detection of functional faults for NOR_4 gate. Test Vector
Nets short detected
where m = 1, NV . The results of determination of the effectiveness of test vector components for detecting fault shorts in NOR_4 gate are presented in Table 8.
V(1)=0000
A&Q A&VDD B&Q B&VDD C&Q D&Q D&VDD Q&VSS
0,002484
V(2)=1000
A&D A&VSS
0,000044
V(3)=0100
A&B B&D B&VSS
0,000518
V(4)=0010
A&C B&C C&D C&VSS D&VSS Q&VDD
0,00153
V(5)=0001
0
Table 8. Effectiveness of test vector components in detection of functional faults for NOR_4 gate.
V(6)=1100
0
V(7)=1010
0
V(8)=1001
0
V(9)=0110
0
V(10)=0101
0
V(11)=0011
0
m
m
m
Probability of nets shorted
Neti Net j
Test Vector
Probability of nets shorted
Nets short detected
V(1)=0000
A&Q A&VDD B&Q B&VDD C&Q D&Q D&VDD Q&VSS
0,002484
V(12)=1110
0
V(2)=1000
A&B A&C A&D A&Q A&VSS Q&VDD
0,001248
V(13)=1011
0
V(3)=0100
A&B B&C B&D B&Q B&VSS Q&VDD
0,001591
V(14)=0111
0
V(4)=0010
A&C B&C C&D C&Q C&VSS D&VSS Q&VDD
0,001734
V(15)=1101
0
V(5)=0001
A&D B&D C&D D&Q Q&VDD
0,001929
V(16)=1111
0
V(6)=1100
Q&VDD
0,000542
V(7)=1010
Q&VDD
0,000542
V(8)=1001
Q&VDD
0,000542
V(9)=0110
Q&VDD
0,000542
V(10)=0101 Q&VDD
0,000542
V(11)=0011 Q&VDD
0,000542
V(12)=1110 Q&VDD
0,000542
V(13)=1011 Q&VDD
0,000542
V(14)=0111 Q&VDD
0,000542
V(15)=1101 Q&VDD
0,000542
V(16)=1111 Q&VDD
0,000542
The results of estimation of the usefulness of test vector components for detecting faults caused by shorts on METAL 1 layer of such standard gates (0.8 µm technology) as NAND_4, AND_2/NOR_3, and AND_2,2/NOR_2 are presented on the diagrams in Figures 6, 7, 8. 0,0025
Taking into account that in many cases some fault is detected by several components of test vector, we introduce the concept of usefulness ( PU ) of test vector components. Usefulness PU of m-th component of test
0,002
0,0015
0,001
m
{
PV h = max PV m , m = 1,N V
} , h=m.
Step 2. Subtract the probabilities of the faults that are detected by h-th test vector components from remaining terms of the effectiveness of test vector components for PV m > 0 PV :
0,0005
V(16)=1111
V(14)=0111
V(15)=1101
V(13)=1011
V(12)=1110
V(11)=0011
V(9)=0110
V(10)=0101
V(8)=1001
V(7)=1010
V(6)=1100
V(5)=0001
V(4)=0010
V(3)=0100
V(2)=1000
0
V(1)=0000
vector is determined by its possibility to detect the greatest number of faults which sum probabilities of occurrence are the highest on condition that there are no faults detected by several components. The algorithm of defining the usefulness of test vector components is as follows: Step 1. Choose the component with the highest effectiveness from test vector PV :
)
Fig.6. Usefulness of the test vector components in detection of functional faults for NAND_4 gate.
the 0.8µm CMOS AND_2,2/NOR_2 gate.
0,0025
0,002
0,0015
0,001
0,0005
V(16)=1111
V(15)=1101
V(14)=0111
V(13)=1011
V(12)=1110
V(11)=0011
V(9)=0110
V(10)=0101
V(8)=1001
V(7)=1010
V(6)=1100
V(5)=0001
V(4)=0010
V(3)=0100
V(2)=1000
V(1)=0000
0
Fig. 7. Usefulness of the test vector components in detection of functional faults for AND_2/NOR3 gate. All results presented in this paper were obtained automatically by the developed special software tools 0,0025
0,002
Fig. 9. Example of FIESTA GUI.
0,0015
CONCLUSIONS
0,001
0,0005
V(16)=1111
V(15)=11010
V(14)=0111 0
V(13)=1011 0
V(12)=1110
V(11)=0011
V(10)=0101
V(9)=0110
V(8)=1001
V(7)=1010
V(6)=1100
V(5)=0001
V(4)=0010
V(3)=0100
V(2)=1000
V(1)=0000
0
Fig. 8. Usefulness of the test vector components in detection of functional faults for AND_2,2/NOR2 gate.
3. SOFTWARE TOOLS For the organization of automatic solution of the above described software FIESTA (Faults Identification and EStimation of TestAbility”) was developed. Input data for these software tools are output text files (ASCII) generated by Cadence™ Layout Editor, and which contains the description of conductive layers of gate layout. Now FIESTA is able to solve automatically the following tasks: a) processing of output Cadence™ files and formation of the own model of gate layout conductive layers; b) formation of the model of critical area for shorts with determined matrix of critical area subdivision S CrAr ; c) determination and estimation the probability of occurrence of shorts for the type of functional fault identification; d) formation of the vector of subdivision of probability between types of functional faults caused by shorts; e) determination of the components of test vector for detecting certain functional types of faults; f) estimation of the effectiveness of the test vector components for the detection of faults resulting from shorts; g) estimation of the usefulness of test vector components for the detection of faults resulting from shorts. The FIESTA was developed using C programming language and works under Solaris operation system for SUN workstation. Graphical User Interface (GUI) was developed using Tcl/Tk 8.2. Figure 9 demonstrates the example of GUI of software FIESTA during analysis of
The results obtained in this work show that there are significant differences between probabilities of various types of faults, and they depend strongly on physical design of a logic gate. Obtained results indicate that the effectiveness of components of test vector for detecting short faults is determined not only by the logic function of a gate but also by its physical design. This information may be used for the development of the VLSI circuits tests.
ACKNOWLEDGEMENTS This work was financially supported by the grant for international cooperation provided by the Polish State Committee for Scientific Research (KBN Nr134/E365/S/99) and by the INCO-Copernicus project VILAB (INCO 977133) funded by the European Union.
THE AUTHORS Dr. Mykola Blyzniuk and Dr. Mychajlo Lobur are with the Computer Faculty, State University "Lvivska Politechnika", 12, S.Bandery st., Lviv, 290646,Ukraine. E-mails:
[email protected];
[email protected]. Prof. Wieslaw Kuzmicz and Dr. Witold Pleskacz are with the Institute of Microelectronics and Optoelectronics, Warsaw University of Technology, Koszykowa 75, 00-662 Warsaw, Poland. E-mails: {wbk,wap}@imio.pw.edu.pl.
REFERENCES [1]. W.A.Pleskacz, W.Kuzmicz. Estimation of the IC layout sensitivity to spot defects. Electron Technology, 1999, Vol.32, No.1/2,pp.182-190. [2]. Dennis V.Heinbuch. CMOS3 Cell Library. Addition-Wesley Publishing Company, 1988.,p.721 [3]. Phil Nigh, Wojciech Maly. Layout-Driven Test Generation. ICCAD, 1989, pp154-157. [4] Wieslaw Kuzmicz. Design for manufacturability in analogue domain. Analogue CMOS IC Design Course.
Warsaw University of Technology, Institute of Microelectronics and Optoelectronics, ADEC, March 15-18, 1999, Warsaw, Poland, p. 77. [5] M.Blyzniuk, W.Pleskacz, M.Lobur, W.Kuzmicz ”Estimation of Probability of Different Functional Faults Caused by Spot Defects in VLSI Circuits”, Proc. TCSET 2000 Conference, Slavsko, Ukraine, 2000, pp47-49. [6] M.Blyzniuk, W.Pleskacz, M.Lobur, W.Kuzmicz ”Estimation of Probability of Different Functional Faults Caused by Spot Defects in Standard Gates”, In Journal “Radioelectronics and Telecommunications”, State University “Lvivska Polytehnika”, Lviv, Ukraine, 2000 / in Ukrainian /.
