Field Programmable Gate Array Based Speed Control of BLDC Motor

Field Programmable Gate Array Based Speed Control of BLDC Motor Rajesh M Pindoriya1

S Rajendran2 & P J Chauhan3

Student Member, IEEE Dept. of electrical engineering Marwadi Education Foundation’s Group of Institutions, Rajkot, Gujarat, India1, 3 [email protected]

Dept. of electrical engineering Indian Institute of Technology Gandhinagar Gujarat, India2 [email protected], [email protected] 3

Index Terms -- Brushless DC (BLDC) motor, field programmable gate arrays (FPGAs), intelligent power module (IPM) and speed control.

I.

INTRODUCTION

Due to fast progress of very large scale integration technology and electronic design automation techniques the industrial motor speed control applications are widely using electronic devices, such as microcontrollers and DSP [1]. These devices are designed with fixed hardware, leaving software as the only method for designers to update designs and limiting the development of application specific functions [2]. Field programmable gate arrays (FPGAs) give designers the freedom to create custom functions completely adapted to their specific application requirements by enabling both hardware and software customization. It provides the capability to implement functions in hardware, accelerating performance and simplifying the software porting effort. These additional freedom opens up new avenues of enhanced system performance, especially for motor speed control and energy efficiency. FPGAs technology is used in many applications such as wired & wireless telecommunications [1] and image processing, etc. Finally, the motor speed control systems are also of great interest because of an ever increasing level of expected performance while at the same time reducing the cost of the control systems. Indeed, FPGAs have already been used with success in many different electric system applications such as power converter control (pulse width modulation (PWM) as an inverters [4], soft switching, STATCOM and electrical machines control). New generations of equipment must have higher performance parameters such as better efficiency and reduced electromagnetic interference [5].

System flexibility must be high to facilitate market modifications and to reduce development time. All these improvements must be achieved while, at the same time decreasing the system cost. Brushless DC motor technology makes it possible to achieve these specifications. Such motor combine high reliability with high efficiency. II.

CONTRIBUTIONS AND LIMITATIONS OF FPGAS USED IN ELECTRICAL SYSTEM CONTROLLERS

First introduction of FPGAs to the market was in 1985 by the Xilinx company. FPGAs hardware technologies have attracted an increasing interest and have significantly disrupted the early digital development process trends. It allows the development of hardware architectures within a flexible programmable environment [2] [6]. These features gives the designer an additional degree of freedom compared to software implementation based on microcontrollers and DSPs [1]. This is because of FPGAs are outperforming software solutions by exploiting the inherent parallelism of the algorithm. The tradeoff DSP and FPGA domain is shown in fig. 1. It is illustrates in a qualitative way the reasons of such a choice. The xaxis of fig. 1 represent timing constraints of the algorithm. These constraints mainly rely on the type of data dependence. The higher this dependence is the more sequential the algorithm. (c) Algorithm complexity (d)

Abstract—This paper demonstrates the Field Programmable Gate Arrays (FPGAs) of design methodologies with a focus on motor drive applications. Motor is the heart of many industrial automation and motion/drive control applications, but major problem arise in controlling the speed of the motor. Brushless DC (BLDC) motor is new and reliable motor because it has high efficiency, high torque to power ratio, lower maintenance due to brushless architecture and compact size, etc. This work presents FPGAs implementation for PWM based speed control of inverter-fed BLDC motor. The proposed methodology is first simulated for open loop and closed loop speed control. These simulation results are further verified through lab scale experimental set up. It has been observed that FPGAs based closed loop method improves the transient and steady state response in speed control of BLDC motor.

(a):- High data dependency

(b):- High level of parallelism of the algorithm (c):- Homogenous functions (d):- Heterogeneous functions

DSP

FPGA

(a) Algorithm timing constraints (b) Fig. 1. DSP and FPGAs domains of use

Development is made according to the design methodology. FPGAs based controller design methodology is shown in fig. 2. The particularity of this methodology consists in providing a topdown design process that start from the

preliminary system specification to the final experimental validation [6]. Preliminary system specification

Algorithm development Modular partitioning Continuous time functional validation Digital realization Algorithm optimization Discrete time & fixed point validation

major problem face an industry is how to effectively control speed of the BLDC motor. A proportional and integral (PI) controller can be used to modified the speed error and dynamically adjust the PWM duty cycle for closed loop speed control. For low cost and low resolution speed control requirements, the hall sensor can be used to measure the speed for feedback signal [10]. An equivalent circuit for speed control of BLDC motor is shown in fig. 3. The back electro motive force (EMF) vs. speed relation is expressed as follows, ݀߆ሺ‫ݐ‬ሻ ‫ܧ‬௕ ሺ‫ݐ‬ሻ ൌ ‫ܭ‬௕ ൬ ൰ ൌ ‫ܭ‬௕ ߱ሺ‫ݐ‬ሻሺͳሻ ݀‫ݐ‬

FPGA architecture design Architecture optimization & design Architecture VHDL/Verilog coding Architecture function simulation Design synthesis and time/area performance analysis FPGA physical implementation process Fig. 3. Equivalent circuit for speed control of BLDC motor

Experimentation Hardware in the loop validation Experimental validation Fig. 2. FPGAs based controller design methodology [6]

Some of the most significant benefits are the cost, the power consumption and the application performance. Presently the two main hardware solutions are available for implementing a controllers like DSPs and FPGAs. Therefore, according to the nature of the algorithm to implement, the designer has to choose between these two possibilities [7]. Motor control is a nonlinear and time-varying parameter application. Many of today’s microcontroller and DSPs devices implement motor control using a simplistic software control loop and a generic one size fits all PWM block. However, this kind of system architecture cannot provide the optimal power, performance and integration needed for efficient motor control applications. Using FPGAs device offer advantages in power efficiency, performance, safety, reliability, system cost, system integration and implementation flexibility [6][8]. A PWM technique controls the power converter transistor states to meet the time average value of the voltage command. This techniques can reduce losses in the motor and power converter while optimizing the voltage utilization of the DC bus. The true advantage of using FPGAs is the ability to customize what was previously fixed generic hardware in microcontroller or DSPs. III.

BLDC MOTOR AND IT’S SPEED CONTROL

BLDC motor is one of the types of motor which is rapidly gaining popularity in many applications. It is used in industries such as appliances, automotive, aerospace, consumer, medical, industrial automation equipment and instrumentation [9]. But

݀‫ܫ‬௔ ሺ‫ݐ‬ሻ ൰ ൅ ‫ܧ‬௕ ሺ‫ݐ‬ሻሺʹሻ ݀‫ݐ‬ మ ௗ ௵ሺ௧ሻ ௗ௵ ܶ௠ ሺ‫ݐ‬ሻ ൌ ‫ ܬ‬ቀ మ ቁ ൅ ‫ ܤ‬ቀ ቁ ൌ ‫ܫ ்ܭ‬௔ ሺ͵ሻ

‫ܧ‬௔ ሺ‫ݐ‬ሻ ൌ ܴ௔ ‫ܫ‬௔ ሺ‫ݐ‬ሻ ൅ ‫ܮ‬௔ ൬ ௗ௧

ௗ௧

Eqs. (2) & (3) can be derived from KVL and Newton’s law. Transfer function of BLDC motor speed with respect to the input voltage can be written as, ‫்ܭ‬ ߱ሺ‫ݏ‬ሻ ൌ ሺͶሻ ‫ܩ‬ሺ‫ݏ‬ሻ ൌ ‫ܧ‬௔ ሺ‫ݏ‬ሻ ሺ‫ܮ‬௔ ‫ ݏ‬൅ ܴ௔ ሻሺ‫ ݏܬ‬൅ ‫ܤ‬ሻ ൅ ‫ܭ‬௕ ‫்ܭ‬ As the armature inductance is very small in practices hence, the transfer function of BLDC motor speed to the input voltage can be simplified as, ‫ܭ‬௠ ߱ሺ‫ݏ‬ሻ ൌ ሺͷሻ ‫ܧ‬௔ ሺ‫ݏ‬ሻ ‫ ߬ݏ‬൅ ͳ Where,  ୫ ൌ  ɒ ൌ 

୏౐ ୖ౗ ୆ା୏ౘ ୏౐ ୖ౗ ୎

ୖ౗ ୆ା୏ౘ ୏౐

is the motor gain

is the motor time constant

The schematic layout for speed control of BLDC motor is shown in fig. 4. It is mainly consists of 3 phase power supply, rectifier & inverter (six IGBT switches) circuits, BLDC motor, data acquisition cum dashboard, FPGAs board, isolation and driver circuit. Here three hall sensors are used for sensing the rotor position of the motor, which is given as feedback signal for closed control system. Mostly used hall sensor for the sensing the speed of BLDC motor. Because of his output response is good and very easy to implement circuit on side of non-rotating part of motor. The flow chart for speed control of BLDC motor is shown in fig.

5. It is an indicated the speed of BLDC motor can be controlled by two topologies, (1) open loop and (2) closed loop. Rectifier

BLDC

motor

3 Ø s u p p l y

Hall sensor

In this technique, a high frequency chopper signal with specific duty cycle is multiplied by switching signals of voltage source inverter [11]. Therefore, it is possible to adjust output voltage of inverter by controlling duty cycle of switching pulses of inverter. PWM signals are generated from the Spartan-3A processor by writing verilog hardware description language program to control gate pulse for the inverter switches. An average output voltage is controlled through duty cycle of PWM. The relationship between average output voltage, duty cycle and input voltage is, Vavg = DVinput. V.

Isolation & driver PC

FPGA kit

Fig. 4. Schematic layout for speed control of BLDC motor

IV.

CONTROL STRATEGY

PWM technique is one of the most popular techniques for speed control BLDC motor.

SIMULATION RESULTS & EXPERIMENTAL VERIFICATION

The aforementioned control strategy was first implemented through MATLAB simulink model. This has been done using variation of PWM duty cycle according to error signal. Thereafter, the verification of the same is done by hardware setup for speed control of BLDC motor using FPGAs. Table I & II shown the experimental parameters and sensors signals, respectively. Table II depicts three hall sensor and six switches sequence. HA, HB, HC, is three hall sensors and S1 to S6 is six switches. Simulation model of speed control of a BLDC motor using input DC voltage source and PI controller for error reduction [11] is shown in fig. 6. The simulation results are shown in fig. 7 and fig. 8 depicts the stator current and back EMF waveform of BLDC motor, respectively. Three phase stator currentsሺ‫ܫ‬௔ ǡ ‫ܫ‬௕ ǡ ‫ܫ‬௖ ) and back EMFsሺ‫ܧ‬௔ ǡ ‫ܧ‬௕ ǡ ‫ܧ‬௖ ሻ are 120q phase shifted with respect to each other. Back EMFs is constant for each 60q interval.

Start Set value Closed loop

Table I Experimental parameters

No

If open loop

Actual speed calculate

Terminal voltage Rated current No. of poles Rated torque Resistance

Yes Check hall sensor signals Reference value & carrier value Compare reference value & carrier Value PWM pulses output

PI controller

Inductance Rotor inertia IPM module Spartan 3A Kit Voltage constant Torque constant Auto transformer current rating

Error = (set speed – actual speed)

PI output & generate PWM pulses

BLDC motor End Fig. 5. Flowchart for speed control of BLDC motor

Nm Ohms mH kgm PEC16D5M01 FPGAs V Nm

310 4.52 4 2.2 3.07 6.57 1.4 - 1.8

5 0.49

A

4

Table II Clockwise sensor and drive Sensor

3 phase Inverter

V A

Clockwise direction

HA

HB

HC

S1

S2

S3

S4

S5

S6

0 0 0 1 1 1

0 1 1 0 1 1

1 0 1 0 0 1

0 1 1 0 0 0

0 0 0 1 0 0

0 0 0 1 1 1

1 0 1 0 0 0

1 0 0 0 1 0

0 1 0 0 0 1

Fig. 8. Back EMFs of BLDC motor when‫ܭ‬௉ ൌ ͲǤ͵,‫ܭ‬௜ ൌ ͵

Fig. 6. Simulink diagram of BLDC motor speed control

Fig. 9 shown the rotor speed of BLDC motor at a rated torque; gain value of ‫ܭ‬௣ ൌ ͲǤ͵&‫ܭ‬௜ ൌ ͵, that time speed is 1000 RPM up to one second and then 1 to 2 second speed is 1500 RPM. It has been observed that closed loop speed control effectively follows the set speed. This has been further verified through experimental setup, as shown in fig. 10. The inverter was built using power IGBT modules, rated at 50 A, 600 V, with a switching frequency of 5 to 10 kHz, dead time is 5μsec. The rectifier was built using six diode switches rated at 60 A, 1.2 kV. Gate signals were generated in the FPGAs controller. A FPGAs platform used for controlling the BLDC motor is Spartan 3A family (Spartan 3A DSP kit), from Xilinx. Reference speed value was set digitally and speed loop was used to compare the actual speed and the reference speed and based on error to determine the duty cycle for the next period [9] [11]. Speed control of BLDC motor scheme used 1047 slice flip flop and 1582 logic gates.

Fig. 9. Rotor speed of BLDC motor when‫ܭ‬௣ ൌ ͲǤ͵,‫ܭ‬௜ ൌ ͵

IPM module

FPGA kit

BLDC motor

Fig. 10. Experimental setup of BLDC motor speed control

Fig. 11 and fig.12 is the representation open loop speed control response. Fig. 11 shown rotor speed of 1173 RPM at duty cycle 28% in forward to reverse direction and fig. 12 shown rotor speed is of 2065 RPM at duty cycle of 50 % in reverse to forward direction. Mostly, all motors are rotating in forward, reverse and braking operation mode. Fig. 7. Stator current of BLDC motor when‫ܭ‬௉ ൌ ͲǤ͵,‫ܭ‬௜ ൌ ͵

Fig. 11. Rotor speed of 1173 RPM at duty cycle of 28% (forward to reverse)

Fig. 14. Actual (981 RPM) and set speed (1000 RPM) (forward to reverse) Table III Summary of the experimental results Sr. No 1 2 3 4 5

Reference speed (rpm) 550 1000 2000 2500 3000

Actual speed (rpm) 553 993 2002 2542 3005

Summary of the experimental results are shown in table III. It has been observed that FPGAs platform is relatively better for controlling speed of BLDC motor, because less time taken for steady state response and transient’s response is fast enough to decay. Fig. 12. Rotor speed of 2065 RPM at duty cycle of 50% (reverse to forward)

The speed control response in closed loop with reference and actual speed in both directions are shown in fig. 13 and fig. 14. Fig. 13 is shown in actual speed is 993 RPM and set speed of motor is 1000 RPM in reverser to forward direction and fig. 14 is shown in actual speed 981 RPM and set speed of motor is 1000 RPM in forward to reverse direction. This response is nearly closed to reference (or set) speed and it has very less transient period, meaning that a speed control response of motor is within few seconds and it has less overshoot and undershoot time period. Using FPGAs platform, the speed control of BLDC motor is very fast and require very minimum time period for direction change.

VI.

This work demonstrates the use of an efficient and lower cost controller based on FPGAs programming to control the speed of BLDC motor. The advantages of digital hardware are very high speed and easily adjusted to comply with software. The use of FPGAs in digital control can be easily adapted to analog control. The simulation results verified through lab scale experiments. The effectiveness of PWM technique for speed control of BLDC motor and its practical applications it has been demonstrated. Using FPGAs platform drives are easily controlled, least time consuming, real time control action, parallel processing and transient response is fast compared to microcontroller based approach. VII. [1]

[2]

[3]

Fig. 13. Actual (993 RPM) and set speed (1000 RPM) (reverse to forward)

CONCLUSION

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