FPGA based neural network position and speed estimator ... - wseas.us

Proceedings of the 7th WSEAS International Conference on CIRCUITS, SYSTEMS, ELECTRONICS, CONTROL and SIGNAL PROCESSING (CSECS'08)

FPGA based neural network position and speed estimator for switched reluctance motor drive JAKUB TALLA, JOSEF STEHLIK Department of Electromechanics and Power electronics University of West Bohemia, Faculty of Electrical engineering Univerzitni 14, Plzen CZECH REPUBLIC

Abstract: - This paper presents the design and implementation of the sensorless control system for the Switched Reluctance Motor (SRM) drive without a position sensor. The SRM has been receiving attention for industry applications due to its low cost in mass production, reduced maintenance requirements, rugged behavior and large torque output over very high speed range. On the other hand, torque ripple, acoustic noise and rotor position sensor requirements are the main disadvantages. This work has been supported by the Czech Ministry of Education – project: Modern Control of the Switched Reluctance Motor Drives - 913/2008/G1. Key-Words: - Switched reluctance motor, Position estimation, Resistance estimation

1 Introduction The common solution of the movement control consists of a relatively expensive position sensor connected to the phase commutation controller therefore this work tried to search for an alternative method for non-direct position estimation. The fundamental principle used in the position estimation is the extraction of the rotor position information from the stator circuit measurements or their derived parameters. Flux linkage is a function of the rotor position and the current flowing through the phase winding (Figure 1). Unfortunately, the relationship between the current, the flux and the rotor displacement features a high nonlinearity which is also temperature and measurement quality dependent. It leads to complicated and inaccurate models. Therefore, the artificial intelligence based on an online trained neural network estimation approach was investigated and implemented into the FPGA. A prototype of the SRM consisting of 6 stator poles and 4 rotor poles is shown in the Figure 2. Proposed algorithms presented in this paper have been implemented into the modern and powerful Altera’s Cyclone II Field Programmable Gate Array (FPGA) for a high speed digital signal processing. Mathematical description of the switched reluctance motor drives:

u = R *i +

u = R *i +

dΨ[υ ,i]

di

di + K [υ ,i ] * ω dt

(3)

Fig. 1 Flux linkage as a function of the position and current

(1)

dt dΨ[υ ,i ]

u = R * i + L[υ ,i ] *

*

di dΨ[υ ,i ] dυ + * dt dυ dt

ISSN: 1790-5117

(2) Fig. 2 Fully unaligned and aligned position of the 6/4 SRM

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2.1 Asymmetric bridge power converter

2 System description

The switched reluctance motor with six stator and four rotor poles is powered by the three phase asymmetric bridge converter which is shown bellow.

U, I

Fig. 5 The asymmetric bridge converter Turning on the two power switches each phase will circulate a current in that phase of the SRM. If the current rises above the commanded value, the switches are turned off. The energy stored in the motor phase winding will keep the current in the same direction until it is depleted. The most frequently used current regulators for the SRM are hysteresis or delta modulation controllers. The reason is the nonlinearity of the phase impedance and robustness of these control variants. The waveforms for unipolar and bipolar switching strategies of hysteresis controller can be seen in figure 6.

Fig. 3 Basic scheme The power converter is controlled by the FPGA based system controller which consists of a three phase hysteresis current regulator and a commutation controller. For proper commutation is necessary to know relative position between rotor and stator poles exactly. Position is primarily estimated by neural network estimator which uses computed value of the flux linkage based on measured phases currents and voltages. In that case, estimation error depends on derivation

dΨ[υ ,i] dυ

of

the flux linkage and thus cannot be used alone for some range of degrees and small values of current where the derivation of flux linkage is small (Figure 1). Therefore, the estimation of the average speed based on the flux linkage derivation

dΨ[υ ,i] dυ

peaks is implemented.

Estimated average speed is used for the secondary position estimation. These two values together form the resulting position. Knowledge of speed is also used for the speed regulator to function.

Fig. 6 Bipolar and unipolar switching strategies

2.2 Flux linkage based position estimation The flux likage is computed by the discrete time integration algorithm:

Ψ = ∫ (u − Restim * i ) ∗ dt

(4)

Where u is the phase voltage, R is estimated winding resistance and i is the phase current. The waveforms of the measured and computed values for the bipolar switching strategy are shown in figure 7.

Fig. 4 Control scheme

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2.4 Artificial Neural Network based estimator The estimator of the position is based on the three layer artificial neural network with twelve neurons in a hidden layer. Neural network works like an adaptive function approximator, which stores expected values of the position for the different current and the flux linkage values. The neural network estimator is trained off-line by the Levenberg-Marquardt algorithm on a mathematical model of the SRM and for better accuracy online tuned by the gradient backpropagation algorithm (with the IRC position sensor) which is implemented in the FPGA. After starting this identification (training) process once, the SRM drive works without the position sensor. This pre-trained strategy has better and faster convergence to the desired values and it’s not necessary to implement advanced training algorithms. The scheme of the neural network can be seen below.

Fig. 7 Flux linkage computation

2.3 Winding resistance estimation The winding resistance estimation strategy is based on a run-time correction of the resistance value. Because of the inaccurate resistance, integration error appears as a remnant of flux linkage after the numeric integration (equation no. 4). The expected value of the flux linkage for the zero current is also zero, therefore we can increase or decrease estimated value of the resistance for better flux linkage accuracy in the next step. The waveforms are shown below. Fig. 9 Artificial neural network

υ = V1 ∗ tanh (W1 ∗ Ψ + W2 ∗ i + b1 ) + + V2 ∗ tanh (W3 ∗ Ψ + W4 ∗ i + b2 ) +

(5)

+ ...V12 ∗ tanh (W23 ∗ Ψ + W24 ∗ i + b12 ) + c1

2.5 Speed estimation and position correction The speed of rotation is computed from the estimated position of the neural network. Since the estimation error depends on derivation of the flux linkage (

dυ

) and

actual values of the current (i) and the flux linkage (ψ) it is better to compute the speed, when the estimation error is the lowest (usually around -23° for each active phase so twelve times per rotation for our 6/4 SRM drive). Then we can compute another value of position by a numeric integration. From these two values of position we can estimate the final position with better accuracy by the weighted average algorithm. The weights for this algorithm are determined from the value of speed (higher speed – higher weight) for the estimated value of position from speed and the weight for the estimated value of the ANN estimator from derivation of the flux

Fig. 8 Winding resistance estimation

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dΨ[υ ,i ]

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linkage (

dΨ[υ ,i ] dυ

based on a high speed CMOS and monolithic air core transformer technology which provides throughput of data up to 150 Mbps. For the current and voltage measuring, three current transducers LA 55-P (LEM) and voltage transducer LV 25-P (LEM) connected to the capacitor of the power converter are used. Transducers are based on the Hall effect and thus provides galvanic isolation between the power circuit and the motor control interface board. Data communication with PC is provided by the FTDI USB-RS232 controller, which emulates virtual serial port with data rates up to 920 kbit/s. The scheme of the motor control interface is shown below.

) and actual values of the current (i) and

the flux linkage (ψ).

Fig. 10 Position correction

3 Hardware description As a hardware platform, the FPGA based Altera Cyclone II DSP board with a connected motor control interface board was used. This solution provides high computing power especially for parallel computing (neural networks), and high flexibility. The biggest disadvantage is a more difficult design than with MCU or DSP based systems.

3.1

Fig. 11 Motor control interface

3.3

Altera Cyclone II DSP board

The Altera Cyclone II DSP board is a development kit with Cylone II FPGA EP2C70 (70 000 logic elements, 150 embedded 18x18 multiplicators, 100 Mhz clock,… ) designed for high speed digital signal applications (for more information see www.altera.com ).

3.2

VHDL design

The VHDL code of the controller was designed in Matlab Simulink by using Altera DSP Builder blockset. This blockset enables us to program, to test the VHDL design in the Simulink (cosimulation, HIL testing …), or to configurate the FPGA. The main scheme of the most important blocks can be seen below.

Motor control interface

The motor control interface was designed as the universal motor controller which provides inputs and outputs commonly used in power electronics. Eight PWM outputs and eight analog inputs as well as the general IO for other communication purposes are placed on the board. All inputs and outputs provide galvanic isolation in order to protect Altera control board in a case of its malfunction or inductive noise. The motor control interface consists of two AD7367 dual 14 bit analog to digital converters that feature throughput rates up to 1MSPS (2 A/D converters in one chip each with 2 multiplexed inputs). Converters can accept true bipolar analog input signals (max ±10 V range). Galvanic isolation between the motor control interface and the Altera development kit form several four channel ADUM344x digital isolators. These are

ISSN: 1790-5117

Fig. 12 VHDL design The most of the processes work paralelly and independently on the other processes and are synchronized by the finite state machine timing and dataflow controller.

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3.4

Data communication

The FPGA is connected to a PC via the FTDI USBRS232 controller. Data communication is packet based. Message consists of the Start byte, Length byte, Data bytes and one CRC control byte (exclusive or of all bytes in the message). Data flow is directed into the Matlab Simulink for a further processing or real-time data acquisition. Communication is bidirectional thus allows tuning of chosen parameters online.

Fig. 13 Data message sending Fig. 16 Estimated position directly from ANN

Fig. 14 Byte sending

4 Measurement The measurement results show the flux linkage as a function of the real position (measured by the IRC) for the flowing current of 12 Amperes. When the rotor is near to a fully unaligned position (-45°), the flux linkage is relatively constant and small. Thus, it’s not possible to estimate the position directly from the values of the current and the flux linkage. The neural network estimator works best around -28° to 0°, when the estimated position has the smallest error. After the speed correction in the middle range of the rotation speeds estimation error is much lower (mainly around -30°). For the near zero speed operations the weight of the estimated position from the speed is much lower and the corrected estimation looks similar to the non-corrected (υestimNN).

Fig. 17 Estimated position after speed correction

Fig. 18 Error in position estimation after and before speed correction Fig. 15 Computed flux linkage

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5 Conclusion This paper presents the improved neural network estimation of the position for the Switched Reluctance Motor drive with the resistance estimation and the speed correction of the estimated position. The online adaptive resistance estimation improves the flux linkage accuracy and the speed correction improves the accuracy of the estimated position (mainly in the middle and high speed operations). The knowledge of the position is necessary for the proper electronic commutation and the continual rotation of the switched reluctance motor drive. The improper commutation causes higher power consumption of the drive and thus decreases the overall power efficiency and increases the torque ripple. The proposed algorithms were implemented into the FPGA. The measurement results show that the error of the corrected position for the middle speed operation (the speed is computed twelve times per rotation) is much lower then the non-corrected value from the neural network estimator.

Fig. 20 Photo of the Altera Cyclone II Dsp board with the motor control interface

References: [1] Miller, T.J.E., Switched reluctance motor and their control, Magna Physics Publishing, Oxford, 1993 [2] Krishnan, R., Switched reluctance motor drives, CRC press, 2001 [3] Vas, P., Artificial-Intelligence-Based Electrical Machines and Drives, Oxford University Press, Oxford, 1999 [4] C C. Elmas, S. Sagirogiu, I. Colak, and G. Bai, Modeling of a nonlinear switched reluctance motor drive based on artificial neural networks, in Proc. IEE PEVSD, 1994, pp. 7–12. [5] T. Frenz and D. Schroder, Learning unknown nonlinearities using a discrete observer in combination with neural networks, in Proc. IEEE Power Electron. Spec. Conf., 1995, pp. 1800–1806.

Fig. 19 Photo of the laboratory with the switched reluctance motor drive (under the desk), with the FPGA based controller (in the middle of the desk) and with the power converter (on the left side of the desk)

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