FPGA Digital Down Converter IP for SDR Terminals

FPGA Digital Down Converter IP for SDR Terminals G. Girau

M. Martina

A. Molino

A. Terreno

F. Vacca

∗

CERCOM (Center for Multimedia Radio Communications) Dipartimento di Elettronica, Politecnico di Torino Corso Duca degli Abruzzi 24 - 10129 Torino - Italy

Abstract During the past years, software platforms have proved a superior scalability with respect to hardware solutions. However, wireless communication rates can not be faced resorting only to software. Software Defined Radio paradigm will try to push reconfigurable blocks as near as possible to the antenna. The first block suitable in this implementation is the Digital Down Converter, needed to adapt higher antenna’s data rate to Intermediate Frequency ones. In this paper a fully reconfigurable IP of a CIC filter, an economical class of multiplier–less filters, is proposed. FPGA implementation has lead to very satisfactory results: 135 MHz on a XCV100E.

1

Introduction

In the last years, telecommunications techniques have achieved a wide popularity, mainly due to the huge diffusion of cellular phones and wireless devices. The request for more complex and complete services, such as high speed data transmission, multimedia content streaming and ubiquitous infotainement, has moved many research groups in the electronic field towards the study of new and efficient algorithms, codes and modulations. In the near future second generation (2G) standards, such as GSM, will share the network and the existing infrastructures with third generation (3G) ones, as UMTS [1]. This transition can be particularly critical in the E.U. countries wherein ∗

This work has been partially supported by CERCOM (Center for Multimedia Radio Communications), Politecnico di Torino, ITALY.

the GSM system has gained a widespread diffusion. One of the main difference between 2G and 3G systems is the channel access technique: while GSM is basically a TDMA oriented system, 3G wireless terminals will be strongly based on CDMA [2]. In this scenario the availability of reconfigurable platforms both for the base stations and mobile terminals will be of great concern. This will enable the possibility to reconfigure the receiver while the user is moving, leading to ubiquitous access to services. In this research work a reconfigurable Digital Down Converter (DDC) architecture is presented. In particular the sample rate conversion block has been implemented resorting to an economical class of multiplier–less filters [3], generally known as Cascaded Integrator Comb (CIC).The designed IP is to be intended as the first block of a completely reconfigurable receiver system. The paper is organised as follows. In section 2 the basic ideas behind Software Defined Radio are introduced, while section 3 is devoted to give a brief overview of Cascaded Integrator Comb filters. In section 4 the proposed IP architecture is dealt with and experimental results from the implementation are given; finally in section 5 the conclusions are drawn.

2

Software Defined Radio

To make the transition from 2G to 3G as smoother as possible, the common domain for the implementation of new system architectures will become the Software Defined Radio (SDR) paradigm [4]. Wireless is a continuously changing environment, wherein the innovation rate is very

high: it would be hopeful to achieve as much flexibility as possible exploiting software solutions. In fact, observing the past years, software platforms have proved superior scalability capabilities with respect to completely hardware solutions. However, the rates involved in mobile wireless communications and the bandwidth requirements can not be faced yet only resorting to software [5]. A possible solution can come from in-field programmable devices (CPLDs and/or FPGAs), able to reach hardware performance with the typical flexibility of software [6]. Currently the trend is to move software boundaries as near as possible to the antenna (i.e. as near as possible to the beginning of the transmitter/receiver chain): a terminal that exploit this strategy is usually classified as Software Defined Radio (SDR) based. SDR approach will let the user the freedom of choosing the most suitable radio front-end in a ”plug-and-play” fashion. This will open the possibility of ubiquitous wireless fruition as well as nomadic access to the Net. In figure 1 a possible receiver scheme is depicted. In particular it is important to note how, even if this scheme has been conceived for a generic CDMA–based system (note the presence of the Rake Receiver), it can be easily adapted to any other channel access mode. Looking at figure 1, different blocks can be identified: the first suitable for a Software Defined Radio implementation is the Digital Down Converter (DDC) one. This block is particularly critical from the implementation point of view because of its main goals. DDC is devoted to filter the input signal at the analog to digital converter rate, and to reduce this high rate to an intermediate one. The former can be performed by the means of digital filtering while the latter can be reconduced to a downsampling. Even if the filter step could be carried out with traditional FIR filtering techniques, the high rates involved seriously compromise the FIR design, making this approach hardly practicable. From some detailed implementation analysis the main system bottleneck seems to be located in the multiplier stages. These disadvantages can be overcome by an eco-

nomical class of filters [7], [3] usually referred in the literature as Cascaded Integrator Comb or, more briefly, CIC.

3

CIC Filters Foundamentals

A CIC filter [3] can be employed to implement either an interpolator or a decimator stage simply changing its building blocks connections (see figure 2). For instance, the basic CIC building blocks are integrators, combs and a downsampling/upsampling stage. It must be noted also how the downsampling stage can be found in the literature also referred as rate compressor (as appear in figure 2). From an hardware perspective an integrator: Hi (z) =

1 1 − z −1

can be simply implemented by the means of an accumulator block. It is worth noticing that, since the integrator exhibits a single pole in the z–plane in z = 1, it is intrinsically unstable [3]. This fact can be observed even in hardware implementation as the necessary one–bit data growth for each integration step. On the other hand, the comb block can be represented in the z–domain as: Hc (z) = 1 − z −RM The comb block can be thought as a discrete– time differentiator and it can be implemented as a digital programmable delay chain followed by a subtracter. In particular, the length of the delay chain can be controlled by the means of the M parameter, called differential delay, while the R value is the desired rate downsampling factor. For a given N –stages CIC filter, the complete transfer function will become: N

HCIC (z) = HI (z)HC (z) =

(1 − z −RM )

(1 − z −1 )N

or more compactly: HCIC (z) =

³ RM X−1 k=0

z −k

´N

.

Figure 1: System architecture

N

N x[n]

I

I

I

fs

Rate compressor

C

C

C

fs/R

C

y[n]

fs/R

decimator CIC

N x[n]

C

N

C

Up− sampler

I

I

I

y[n]

fs

interpolator CIC

Figure 2: CIC filter block scheme

From this last relation can be easily note where the main CIC filters advantage lays with respect to traditional filters: their structure is completely multiplier–free.

4

Proposed IP

4.1 Architecture In figure 4 the complete CIC architecture is depicted; the IP interface and parameters are reported in figure 3. From the reconfigurability point of view it is important to note the two different types supported by this architecture: “on– line” and “off–line” reconfigurability. The former can be directly supplied from the upper network layers to the CIC core without the need for a dedi-

cated system re–initialisation phase; the latter are provided as VHDL generic parameters and their change will be reflected in hardware only after a successive logical synthesis step. This strategy not only enables the possibility of a traditional “design and reuse” IP methodology, but even opens new client–server SDR perspectives. It is forecastable that, in the near future, the need for the “off–line” re–synthesis can be covered by the employment of dedicated “server farms” devoted to on–demand IPs customisation. 4.2

Implementation and results

The complete FPGA design flow has been carried out on a XILINX Virtex-E device

Figure 4: Decimation CIC filter architecture entity CIC Decimator 1 i s generic ( num bit in : positive ; num bit ext : integer ; size log2R : positive ; size R : positive ; Nmax : positive ; : positive ; num bit out Mode Bit Out : i n t e g e r ; SatPos : integer ; SatNeg : integer ); port ( : in s t d l o g i c Data in : in s t d l o g i c r in M : in s t d l o g i c RST, ck : in s t d l o g i c Data out : out s t d l o g i c DV : out s t d l o g i c ); end CIC Decimator 1 ;

v e c t o r ( n u m b i t i n −1 downto 0 ) ; v e c t o r ( s i z e l o g 2 R −1 downto 0 ) ; ; ; v e c t o r ( num bit out −1 downto 0 ) ;

Figure 3: Interface signals and parameters in proposed architecture

(XCV100E) resorting to Synplicity SynplifyPRO and XILINX ISE 4.2. The high number of changeable parameters in the architecture makes not convenient an exhaustive design space exploFigure 1: Cic filters for decimation and interpolation ration to evaluate performance and resources impact. Then a reduced but significant set of imReferences plementation patterns has been carried out, and [1] Tuttlebee W.H.W., “Software-defined radio: facets of a developing technology,” Communications, 6, pp.shown 38–44, April thePersonal obtained resultsvol.are in1999. the following. Filter

Introduction,”

July

bit out

Reg.

12 12 16 24 24

10 12 8 20 16

694 805 808 1045 1041

LUTs 558 642 642 810 810

(23%) (26%) (26%) (33%) (33%)

clk (MHz) 142 135 135 121.6 121.6

Table 1: Synthesis reports: area and frequency varying input and output data width

The first set of results (table 1) deals with the maximum clock frequency and the expended area in Virtex device; the effect of the data in/out width is shown, while the other parameters are fixed to be Mode Bit Out=1, nbit ext=2, size R=15, size log2 R=4, Nmax=7 In table 2 are exposed the results obtained when the parameter Nmax (the number of supported steps) is changed; for these synthesis we assume that nbit in = 16, nbit out = 12, Mode Bit Out = IEEE 1, nbit ext = 2, size R = 15, size log2 R =

[2] M. Cummings and S. Haruyama, “FPGA in the Software Radio ,” IEEE Communications Magazine, vol. 37, pp. 108–112, Feb. 1999. [3] Matthew P. Donadio, “CIC URL:http://users.snip.net/ donadio/.

bit in

2000,

[4] Hogenauer E.B., “An economical class of digital filters for decimation and interpolation,” IEEE Trans. Acoustic, Speech and Signal Processing, vol. 29, pp. 155–162, April 1981.

Nmax 1 2 3 4 5 6 7

Reg. 155 245 342 436 552 677 812

LUTs 150 (6%) 215 (8%) 288 (12%) 363 (15%) 449 (18%) 542 (22%) 642 (26%)

clk (MHz) 145.1 144.9 142.8 140.8 138.8 136.8 135

Table 2: Synthesis reports: area and frequency varying Nmax

4. It is important to note that the parameter MODE Bit Out represent the behavior of the aritmetic units: 1 → truncation, 2 → rounding, 3 → saturation with truncation, 4 → saturation with rounding. Regarding the power consumption needed to carry out the computation, the biggest contribution comes from the FPGA static consumption. In fact, working at 100 MHz, the total power requirement is 404 mW (360 mW static + 44 mW dynamic): these values has been obtained using XILINX XPower tool on post place–and–route results. It is important to note how this term is nearly unaffected by small variation of the architecture parameters. As far as experimental results and performance are concerned, the scalability of the proposed core opens a wide set of possible design implementations. Taking into account current analog to digital converters resolution and system performance, a reasonable configuration can be obtained when num bit in = 16, num bit out = 12, Nmax = 7 and Mode Bit Out = 4 (saturated additions with rounding).

5

Conclusions

In this paper a reconfigurable DDC architecture has been proposed. Very promising results have been obtained after the logical synthesis resorting on an high performance Virtex-E FPGA, from XILINX. Further investigations will be pursued basically following two different research di-

rections: • In order to completely characterise the proposed IP, a complete power analysis should be carried out, in order to experimentally validate the power estimations obtained with XPower. • The architecture should be ported on a ultra low–power CPLD in order to explore the possibility of a power consumption reduction. Acknowledgements The author would like to thank Dr. Mario Nicola form Politecnico di Torino for his precious tutorials on CDMA principles, CIC filters and Digital Down Conversion.

References [1] “URL:http://www.3gpp.org,” . [2] Viterbi A.J., CDMA: principles of spread spectrum communications, Addison-Wesley Publishing Company, 1995. [3] Hogenauer E.B., “An economical class of digital filters for decimation and interpolation,” IEEE Trans. Acoustic, Speech and Signal Processing, vol. 29, pp. 155–162, Apr. 1981. [4] Buracchini E., “The software radio concept,” IEEE Communications Magazine, vol. 38, pp. 138–143, Sept. 2000. [5] Tuttlebee W.H.W., “Software-defined radio: facets of a developing technology,” IEEE Personal Communications, vol. 6, pp. 38–44, Apr. 1999. [6] M. Cummings and S. Haruyama, “FPGA in the Software Radio ,” IEEE Communications Magazine, vol. 37, pp. 108–112, Feb. 1999. [7] Matthew P. Donadio, “CIC Filter Introduction,” July 2000, URL:http://users.snip.net/ donadio/.