Hardware Implementation of Linear Systems

Hardware Implementation of Linear Systems: An Overview Dr Abdelkrim Kamel OUDJIDA Centre de Développement des

Technologies Avancées (CDTA) April 5th 2018

A.K. OUDJIDA, [email protected], CDTA, April 5th 2018

Hardware Implementation of Linear Systems: An Overview Keywords

IC Digital-Design: ASIC, FPGA, SoC, IP, Embedded Systems,

High-Speed, Low-Power, Circuit Optimizations, …

Mathematics: Logic, Computer Arithmetic, Binary Arithmetic, Number Theory, Probability, Algorithmic optimizations, …

Applications: Digital Signal Procesing, Image Processing,

Cryptography, System Control, …


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Hardware Implementation of Linear Systems: An Overview Partners National:

− LRPR Laboratory, USTHB − LMCS Laboratory, ESI International: − ALGOS, INESC-ID, Lisbon − Univ. Kassel, Germany − Disc Team, FEMTO-ST, Besançon

− LIP6, Univ. Jussieux, Paris − LIP, ENS, Lyon − Nanyang University, Singapore


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Hardware Implementation of Linear Systems: An Overview Team Members Dr Abdelkrim Kamel OUDJIDA Ahmed LIACHA Mohamed Lamine BERRANDJIA Dr Chahinaz CHAOUCHI

Naziha Ali-SAOUCHA Fatiha LOUIZ Dr Mohammed BAKIRI Ryma BELLAL Belkacem KHITER


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Hardware Implementation of Linear Systems: An Overview Circuit Optimization

Benefits:

− Speed − Power − Area

− Cost A.K. OUDJIDA, [email protected], CDTA, April 5th 2018

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Hardware Implementation of Linear Systems: An Overview

IP Creation for Linear Systems (IPLS, Jan. 2014) Motivation Objective

Startup in IP VLSI Development of a new binary arithmetic for an efficient VLSI implementation of LTI systems.

IP: Intelectual property; CAS: Circuits and Systems; LTI: Linear Time Invariant; VLSI: Very Large Scale Integration; TSMC : Taïwan Semi-Conductor Manufacturing Company; DSP: Digital Signal Processing; IP: Image processing A.K. OUDJIDA, [email protected], CDTA, April 5th 2018

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Hardware Implementation of Linear Systems: An Overview Outline Preliminaries in Digital Design Problem Statement Our Solution Signal Processing (FIR filters)

Control Systems (PID, LQG with Kalman Filtering) Crypto-Systems (ECC, PRNG) Conclusions and Future Works


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Hardware Implementation of Linear Systems: An Overview Preliminaries in Digital Design: Linearity

4 Bits adder

Hardware Complexity: − Adder O(N) − Multiplier O(N2) A.K. OUDJIDA, [email protected], CDTA, April 5th 2018

5 Bits multiplier Slide 8/49

Hardware Implementation of Linear Systems: An Overview Preliminaries in Digital Design: Approximate Computing

Image/Video Compression (DCT & IDCT)

Approximate Adder_1 (16 Trs)

Approximate Adder_2 (14 Trs)

Exact Adder (24 Trs)

Source:V. Gupta , IEEE-TCAD, 2013 Approximate Adder_3 (11 Trs) A.K. OUDJIDA, [email protected], CDTA, April 5th 2018

Approximate Adder_4 (11 Trs) Slide 9/49


Exact Adder

Approx. Adder_1

Approx. Adder_2


Approx. Adder_3

Approx. Adder_4

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PS ≈ 60%

PS ≈ 50%

Self Correcting Logic ?!

Self Correcting Circuit A.K. OUDJIDA, [email protected], CDTA, April 5th 2018

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Problem Statement


Hardware Implementation of Linear Systems: An Overview Problem Statement

Computational Model of Linear Systems

xk 1  A xk  B uk 

xk 1  Ak  xk   Bk  uk 

yk   C  xk   D  uk 

yk   C k  xk   Dk  uk 

LTI: Explicit discrete time-invariant

LTV: Explicit discrete time-variant

x : state vector, xt  n y  : output vector, yt  q u  : input vector, ut   p A : state matrix, dimA  n  n B : input matrix, dimB  n  p

C  : output matrix, dimC   q  n D : feedthrough matrix, dimD  q  p A.K. OUDJIDA, [email protected], CDTA, April 5th 2018

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Hardware Implementation of Linear Systems: An Overview Problem Statement  Y1   C11 C12  C1n   X 1  Y  C  X  C  C 2 21 22 2 n     2                  Ym  Cm1 Cm 2  Cmn   X n 

C , C 1i

2i

, C3i , , Cmi   X i

Formulation of LTI Systems

SCM Example

45  X j  1011012  X j  X j  25  X j  23  X j  22  X j 45  X j  U  22  U with U  X j  23  X j

SCM/MCM is conjectured to be an NP-hard problem

MCM Example A.K. OUDJIDA, [email protected], CDTA, April 5th 2018

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Hardware Implementation of Linear Systems: An Overview Problem Statement N 1

N is the filter length

y  n    hi  x  n  i  i 0

hi is the ith filter coefficient x(n-i) is the ith previous filter input with 0≤i≤N-1

Transposed Form of a FIR Filter


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Hardware Implementation of Linear Systems: An Overview Problem Statement Metrics in SCM/MCM Upper-bound (Upb): For each N-bit constant Ci , corresponds Ai additions for the implementation of Ci  X . Upb  max  Ai  .

Adder-Depth (Ath): Let Di be the number of adders that we pass through along any path i from the input to any of the outputs in the constant multiplication logic circuit. Ath  max Di  .

Average (Avg): For each N-bit constant Ci , corresponds Ai additions for the 2N implementation of Ci  X . Avg   A  / 2 N , where 2N is the total number of  i   i 1  constants.


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Our Solution


Hardware Implementation of Linear Systems: An Overview Radix-2r Arithmetic (Sam & Gupta 1990)

Y  y N 1 y N 2  y2 y1 y0 N 2

  yN 1 2 N 1   y j 2 j j 0



N 1 1 r

  yj 2j j 0

  y j 0



N 1

N 1 1 r

 j 0

r 1 r 2 2  y 2  rj  r 1 rj  r  2

Q j .2rj

 yrj  2 22  yrj 1 21  yrj 20  yrj 1  2rj

Q j  DS  2r   2r 1 ,


,0,

, 2r 1

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Hardware Implementation of Linear Systems: An Overview Radix-2r Arithmetic

1951: Booth, Radix-21, signed multiplication 1961: Mc Sorley, Radix-22, critical path

1990: Sam & Gupta, Radix-2r, critical path 2011: Oudjida et al., Radix-2r, recursivity, SCM/MCM, Metrics, Crypto, Variants, …


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Hardware Implementation of Linear Systems: An Overview Our Solution


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Hardware Implementation of Linear Systems: An Overview Our Solution

Main Features of Radix-2r MCM Radix-2r is the generalization of CSD (CSD = Radix-22) Optimal in speed and near-optimal in area, best in power Sublinear O(MxN/r) Fully-predictable at adder and bit levels

Highly reconfigurable (2r) Simple and easy to be used Hard to compete with it

Ci  X  A u  X , v  X   2l1  u  X   2l2   v  X 

RADIX-2r is one of the leading MCM heuristics


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Signal Processing (FIR filters)


Hardware Implementation of Linear Systems: An Overview Signal Processing (FIR filters) N is the filter length

N 1

y  n    hi  x  n  i 

hi is the ith filter coefficient

i 0

x(n-i) is the ith previous filter input with 0≤i≤N-1 D

x(n)

h0

x

h1

+

y(n)

D

x

D

x

h2

+

h3

+

D

x

D

x

h4

+

x

h5

+

(a) Multiplier block

x(n)

h0

y(n)

x

+

h1

D

x

+

x

h2

+

D

h3

D

x

+

x

h4

D

+

x

h5

D

(b)

FIR filter implementations. (a) Direct form. (b) Transposed form A.K. OUDJIDA, [email protected], CDTA, April 5th 2018

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Hardware Implementation of Linear Systems: An Overview Signal Processing (FIR filters)


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Tranposed Form of a FIR Filter


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Hardware Implementation of Linear Systems: An Overview Signal Processing (FIR filters) www.cdta.dz/products/mcm/


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Hardware Implementation of Linear Systems: An Overview Signal Processing (FIR filters) Filter specifications (N, wp , ws , δP , δs)

Determining filter coefficients and quantization Multiplierless implementation using RADIX-2r

RTL (Verilog) code generation

Hardware implementation (TSMC 0.18 µm)

Post place/route timing & power analysis


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Control Systems (PID, LQG with Kalman Filtering)


Hardware Implementation of Linear Systems: An Overview Control Systems (PID)

t     1 de t  u t   K p  et    e   d  Td   Ti dt  0   PID equation A.K. OUDJIDA, [email protected], CDTA, April 5th 2018

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PID cores. (a) Commercial PID with constant coefficients (b) Commercial PID with time varying coefficients A.K. OUDJIDA, [email protected], CDTA, April 5th 2018

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−

−

Partitioning of a 16-bit Y operand with r = 8 Architecture of the commercial PID

Serial/Parallel implementation of the multiplier, with r varying from 1 to N

Optimized DMAC architecture for r = 4 A.K. OUDJIDA, [email protected], CDTA, April 5th 2018

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15 cm Setup of temperature regulation 1: FPGA evaluation board; 2: Electronic device; 3: Tube containing a fan and a lamp; 4: PC display screen A.K. OUDJIDA, [email protected], CDTA, April 5th 2018

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Floating point PID

Fixed point PID with Qni.nf = Q8.8



Effect of the setpoint fractional-length on the temperature regulation


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PID [21], IEEE-TIE


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Hardware Implementation of Linear Systems: An Overview Control Systems (LQG + Kalman Filtering)

FTG-100 microgripper General scheme of the LQG controller with Kalman filter


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Hardware Implementation of Linear Systems: An Overview Control Systems (LQG + Kalman Filtering) 29 x 23 +

313 +

Qni.nf = Q5.16

101 +

68%

Standard methodology for an optimized hardware integration of LTI systems: from Matlab functional model to HDL synthesizable code A.K. OUDJIDA, [email protected], CDTA, April 5th 2018

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Hardware Implementation of Linear Systems: An Overview Control Systems (LQG + Kalman Filtering)

x10−5

The noisy and filtered forces (Fc) of the actuated arm


The difference between the floating-point and the fixed-point filtered forces (Fc)

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Crypto-Systems (ECC)


Hardware Implementation of Linear Systems: An Overview Crypto-Systems (ECC)

Elliptic Curve y  x  a  x  b 2

3

ECC versus RSA: bit-size of the key k

Scalar multiplication A.K. OUDJIDA, [email protected], CDTA, April 5th 2018

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Hardware Implementation of Linear Systems: An Overview Crypto-Systems Rapid and Memory-Efficient Algorithm for Scalar Multiplication in Elliptic Curve Cryptography Fastest windowing algorithm with low memory consumption Guided by exact analytic formula to optimize ADD perations Recodes and evaluates the key on-the-fly from LR and RL 35% Saving in ADD operations over NAF for NIST GF(2m) 56% Saving in ADD operations over NAF (Upper-bound) Very easy-to-be-usedd Highly reconfigurable, allowing speed-memory trade-off Resilient to side-chanel attacks (timing and power)


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Hardware Implementation of Linear Systems: An Overview Crypto-Systems

Hardware Pseudo Random Number Generator Based on Chaotic Iterations One of the best hardware chaotic PRNGs (technology independent) One of the highest Throughputs (12 Gbps) Passed all tests battery including the hardest ones (TestU01) Can be integrated in any SoC based on AXI-Bus Generation of 1 Million Boolean Functions Based on the Suppression Hamiltonian Cycles (TestU01) Analytically Proven Cryptographically Secure for Industrial Applications


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Conclusions & Future Works


Hardware Implementation of Linear Systems: An Overview Conclusions & Future Works Conferences: − IEEE-FTFC

Publications: − JOLPE

− IEEE-PATMOS

− IET-CDS

− IEEE-SMACD (Price)

− IEEE-TCAS

− IEEE-NEWCAS

− IEEE-TII

Future Research-Works: − Exact and approximate computing for the optimization of linear systems − Lightweight cryptography


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Hardware Implementation of Linear Systems: An Overview Deliverables: Software Platforme for Algerian Universities


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Hardware Implementation of Linear Systems: An Overview Deliverables: Software Platforme of IP-VLSI for Algerian Universities


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Hardware Implementation of Linear Systems: An Overview Deliverables: Software Platforme of IP-VLSI for Algerian Universities Benefits Ready-to-be-used IP codes for Master/PhD Students Provides competitive IPs: ease of publication Comprises the most commonly used IPs in DSP, IP, Crypto., Control,… Built in Compliance with standard IP Design Rules (codes, doc., demos.,…)

Self-enriched Platforme (Master/PhD projects) Creates a real dynamic in digital design Sustains the Algerian National Network in Microelectronics


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Thank You “Simplicity is about subtracting the obvious and adding the meaningful.” − John Maeda


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Hardware Implementation of Linear Systems

Hardware Implementation of Linear Systems

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