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Hardware-Software Codesign and Coverification Methodology for Dynamically Reconfigurable System-on-Chips1 ! ᅜറӼǵᄃדঢ়ǵමדᇬǵ݅ۘ࠶ǵഋϡঅǵߋ߷ᆡ! ୯ҥύ҅εᏢၗૻπำᏢ Pao-Ann Hsiung , Chih-Feng Liao, Chih-Hao Tseng, Shang-Wei Lin, Yuan-Hsiu Chen, Kuan-Lun Chiu National Chung Cheng University, Chiayi, Taiwan E-mail:
[email protected]
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optimize the large number of parameter values of SIPs. As a solution to the above issues, a methodology for the co-design and co-verification of reconfigurable SoC is proposed. The overall codesign flow is shown in Figure 1, which consists of five different loops, namely A: System Verification Loop, B: System Layout Evaluation Loop, C: System Design Loop, D: IP Layout Evaluation Loop, and E: Tuning Loop.
Abstract Dynamically reconfigurable system-on-chips can change its hardware as well as software functionalities during run-time. Such system designs need more than what traditional design and verification techniques can provide. For example, partitioning is complicated by spatial placements in FPGA while OS needs more transparent handling between hardware and software tasks. We propose a hardware-software codesign and coverification methodology for dynamically reconfigurable SoC. We also applied the proposed methodology to a self-designed SoC supporting two systems: MMDS (Modular Mobile Dispatch System) and PSMS (Wireless Physiological Signal Monitoring System), which illustrate the feasibility of our approach.
We have segregated our research work into the following three parts: (i) We are proposing a unified hardware-software specification method for reconfigurable SoCs and the mapping to formal models such as hierarchical FSM and SDF graphs. (ii) We are applying the function architecture co-design methodology to reconfigurable SoC and perform system evaluation both for reconfigurable functions and for system layout (with the help of subproject 3).
1. Introduction Reconfigurable SoCs differ from conventional ones mainly in its capability to dynamically change the functionalities of both system hardware as well as software. Hardware circuits can be reprogrammed in an embedded FPGA and software modules relinked in an operating system kernel. Some issues encountered in such a complex design process include how to design efficient Configurable System Logic (CSL) using FPGA [1-5], how to re-use Silicon Intellectual Property (SIP), how to apply platform-based tuning techniques to a reconfigurable system, and how to
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(iii) Co-synthesis, co-emulation, and co-verification: Co-synthesis includes hardware synthesis, software synthesis, and interface synthesis along with the synthesis of CSL by programming FPGA. Co-emulation focuses on how to adapt platform tuning to a reconfigurable system. For SoC co-verification, we are proposing a novel semi-formal verification methodology which integrates the
This work was support in part by a research project grant NSC-92-2218-E-194-009 from the National Science Council,
Taiwan.
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conventional simulation and testing methods with formal methods such as model checking such that we obtain the advantages of both methods. By applying the proposed methodology to our target MMDS/PSMS SoC, we illustrate its feasibility and benefits.
analysis and optimizations. This step can also be divided into partitioning and scheduling. Third, the hardware and software tasks obtained from the previous step are cosynthesized and coverified. System Specification
2. Related work Pre-design
We classify several related works on the design of dynamically reconfigurable SoC into the following categories.
Analysis
SW IP
Architecture
(i) Survey [6]: This explores the hardware aspects of reconfigurable computing machines, and also focuses on the software for these machines.
HW IP
Design
A
(ii) Modeling [7]: SystemC is used to model reconfigurable hardware.
I
Interface IP
System Verification
B
(iii) Partitioning [8-11]: These work propose partitioning techniques for dynamically reconfigurable systems using network flow optimization, random, simulated annealing, genetic algorithm, and clubbing.
Verification IP
System Layout Evaluation
(iv) Scheduling [12-14]: These work propose both static and dynamic scheduling methods. Static methods include list scheduling with priorities determined either randomly or dynamically. Dynamic methods include online scheduling, EDF, and multi-context scheduling.
Output Software
Output CSL
Output Hardware
Specifications
Specifications
Specifications
C
Process Design
D
Feedback
E
(v) Co-synthesis [15]: A three-step design process for energy efficient application synthesis using reconfigurable SoC is proposed.
System Tuning
(vi) Implementation [16, 17]: Mignolet et al. in [16] propose relocating hardware task into software and vice-versa. Horta et al. in [17] propose dynamic hardware plugins that can aid partial run-time reconfiguration.
Reconfigurable SoC
Figure 1. Co-Design and Co-Verification Flow for Reconfigurable SoC with Tuning
(vii) Case Study [18]: This is a case study on a reconfigurable Web Camera that can download and reprogram its hardware/software through the web.
A: System Verification Loop, B: System Layout Evaluation Loop, C: System Design Loop, D: IP Layout Evaluation Loop, E: Tuning Loop , I: Coverification 3.1 RSoC Model
3. Codesign and Coverification Methodology
A reconfigurable SoC is modeled using SystemC as in Figure 3. The architecture and the data flow in this architecture are described in the following using the MMDS and PSMS systems as illustration examples.
A co-design and coverification methodology is proposed for dynamically reconfigurable SoC (RSoC). The codesign flow in this methodology is illustrated in Figure 2. First, we model a given application system using Unified Modeling Language (UML) [19] and the architecture of a reconfigurable SoC using SystemC. Second, the UML application is mapped to the SystemC SoC architecture using a function architecture codesign methodology, which includes decomposition, refinement, abstraction, and data framework
In the architecture of an RSoC, there is an embedded microprocessor such as NIOS in Altera FPGA chips or PowerPC 405 in Xilinx FPGA chips. There is a data block that collects and processes input data such as that from sensor modules. There is a communication block that
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interfaces with the outside world such as wireless connections including either Bluetooth or IEEE 802.11b/g protocols. The microprocessor has various I/O devices wired to it such as LCD, buttons, alarm. Memory blocks can also be attached to microprocessor including ROM and RAM. Reconfiguration is designed mainly for the data block and the communication block. Sensor driver modules can be dynamically reconfigured in the data block depending on the needs of a system. For example, MMDS needs GPS sensor while PSMS needs both GPS sensor as well as health sensors such as temperature, blood pressure, and heartbeat. Communication interface modules can also be dynamically reconfigured in the communication block. For example, if the PSMS is used in a hospital environment then it might need Bluetooth to communicate with the medical center in the hospital. However, if the patient goes outside of the hospital, then Wi-Fi or GPRS might be needed for communication with the same medical center.
domain. In this project, the three UML diagrams are restricted and enhanced, and accompanied by guidelines for designers to follow in specifying synthesizable and verifiable system models. UML/SystemC
Application Model
RSoC Model
System Partitioning
Scheduling
Hardware Tasks
The data flow within such an RSoC architecture model is as follows. First, the sensor data are collected and processes by the data block and the microprocessor. Then, the microprocessor sends a message to a remote control center using some kind of configured communication interface in the communication block. Users can configure some settings for an RSoC system such as the attribute of PSMS using the button device. Messages from the system can be displayed on the LCD. Alarms can warn users of error or dangerous conditions.
Software Tasks
Cosynthesis
Coverification
Figure 2. Codesign Flow for Reconfigurable SoC
SystemC, a system-level language, besides being very efficient in describing such an architecture, is also suitable for design space exploration and validation for RSoC due to its inherent simulation capabilities.
ROM
RAM
FPGA GPS
3.2 Application Model
Temperature sensor
Data Block
Microprocessor
Communication Block
Bluetooth 802.11b
Blood Pressure sensor
An application such as MMDS or PSMS can be described using a system-level design language. We adopt UML [16], which is one of the most popular modeling and design languages in the industry. It has become the de facto standard in the industry. After scrutiny of all diagrams in UML, we have chosen three diagrams for a user to input as system specification models, namely class diagram, sequence diagram, and statechart. These diagrams were chosen such that information redundancy in user specifications is minimized and at the same time adequate expressiveness in user specifications is preserved. UML is a generic language, and specializations of it are always required for targeting at any specific application
Heartbeat sensor
LCD
Button
Alarm
Figure 3. Block Diagram for Wireless Physiological Signal Monitoring System The class diagrams were enhanced with deployment information as shown by the dotted arrows in Figure 4, which is the class diagram specified by a user for designing the PSMS application example. This diagram consists of 8 software classes which are deployed on 10
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Figure 4. Class Diagram with Deployments for PSMS hardware classes. The UML statecharts were enhanced by allowing more complex temporal behavior specification such as multiple unsynchronized clocks, and clock checking and resetting. Another addition to the standard statecharts is the set of keywords associated with time-triggered methods, namely start, stop, and reset, which starts, stops, or restarts a time-triggered method, respectively. Figure 5 illustrates the timed statechart for the Controller Class in our PSMS example. Eight statecharts, one for each of the eight classes (Figure 4), are omitted due to space constraints. Sequence diagrams were enhanced to include control structures, such as for concurrency, conflict, and composition. Another enhancement to the standard sequence diagrams is the state-marks that are inserted into the life axis of an object. They aid in user comprehension of the sequence diagrams
Figure 5. Timed Statechart for the Controller Class in PSMS
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for further maintenance and also in the scheduling process of PSMS.
controller sends the message Controller_Send_Actuator_SIG() only when it is in the Send_Actuator state.
Figure 6 illustrates one of the five sequence diagrams for PSMS, which depicts an abnormal scenario where a user is in a dangerous physiological state. A state-mark Send_Actuator on the Controller object life axis indicates that the
As far as mapping, partitioning, scheduling, and cosynthesis design phases are concerned, work is still undergoing and we plan to finish it within the following year.
Figure 6. A sequence diagram for PSMS 5
[6]
K. Compton and S. Hauck, “Reconfigurable computing: a survey of systems and software,” ACM Computing Surveys, Vol. 34, No. 2, pp. 171-210, June 2002
[7]
A. Pelkonen, K. Masselos, and M. Cupak, “System-level modeling of dynamically reconfigurable hardware with SystemC,” in Proceedings of the 10th Reconfigurable Architectures Workshop (RAW), an IPDPS’03 workshop, pp. 174, IEEE CS Press, April 2003. H. Liu and D. F. Wong, “Circuit Partitioning for Dynamically Reconfigurable FPGAs,” in Proceedings of International the ACM/SIGDA 7th Symposium on Field Programmable Gate Arrays, pp. 187-194, ACM Press, February 1999
4. Application Example We validated our proposed codesign and coverification methodologies by applying it to the PSMS/MMDS RSoC to be developed in collaboration with other subprojects. The methodology itself was implemented by integrating several of our tools, such as VERTAF for embedded software synthesis, ICOS for embedded hardware synthesis, SGM for formal and semi-formal verification, and other scheduling-based tools for real-time software analysis and synthesis. The end-result of this project is that we have a complete environment for the design of reconfigurable SoC.
[8]
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