High-density nano-pillar SiOx-based resistive switching memory using nanosphere lithography to fabricate a one diode - one resistor (1D-1R) architecture Y. F. Chang 1, L. Ji 1, Y. C. Chen 3, F. Zhou 1, T. M. Tsai 4, K. C. Chang 4, M. C. Chen 4, T. C. Chang 4, B. Fowler 2, E. T. Yu 1, and J. C. Lee 1 1 MRC, ECE, The Univ. of Texas at Austin, TX 78758 2 PrivaTran, LLC, Austin TX 78746 3 Institute of Electronics, Nat. Chiao Tung Univ., Hsinchu 300, Taiwan 4 Dept. of Mater. & Optoelectron. Sci. and Dept. of Phys., Nat. Sun Yat-Sen Univ., Kaohsiung, Taiwan Phone: +1 512-221-6910, Fax: 512-471-5625, Email:
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ABSTRACT A highly compact, one diode - one resistor (1D-1R) nano-pillar device architecture has been demonstrated using nano-sphere lithography (NSL) to fabricate SiOx-based resistive switching (RS) memory. The intrinsic SiOx-based resistive switching element and Si-based PN diode are self-aligned on the epitaxial silicon wafer using NSL and a deep-Si-etch process without using conventional photolithography. The DC electrical performance, an AC pulse response in the 50 ns regime, capability for multi-bit operation, and high readout margin immunity for sneak path issue demonstrate good potential for high-speed nonvolatile memory (NVM). The NSL fabrication process is an efficient, economical approach to enable large-scale patterning of 1D-1R architectures while providing excellent NVM performance for future applications. Keywords: Nano-pillar, ReRAM, and Nano-Sphere Lithography.
INTRODUCTION Resistive random access memory (ReRAM) has become a promising replacement technology beyond 20 nm due to its potential scalability [1]. Many materials such as transition metal oxides have been studied for use in ReRAM [2], whereas our work has focused on intrinsic SiOx-based materials [3]. In this work, a one diode - one resistor (1D-1R) configuration using intrinsic SiOx-based ReRAM was fabricated using nano-sphere lithography (NSL) to demonstrate a nano-pillar (NP) type of architecture. Key achievements include: 1) Implementation of a novel NSL process using deep Si etch (DSE) to realize high-aspect-ratio 1D-1R structures, resulting in efficient large-scale patterning at low cost without conventional photo masks; 2) Comprehensive investigations of electrical characteristics by varying device structure; and 3) Demonstration of multi-bit operation and excellent readout margin immunity.
EXPERIMENTAL, RESULTS AND DISCUSSION Fig. 1 illustrates the NSL process flow for a 1D-1R SiOx-based ReRAM with sequential SEM images of the evolving structure. The process begins with 60 nm SiOx e-beam evaporation on a P++/N-/N++ epitaxial Si wafer (P++ thickness 0.3 um, concentration 5×1019 cm-3; N- thickness 0.6 um, concentration 5×1016 cm-3; N++ substrate, concentration 1-7×1019 cm-3). The SiOx layer is the 1R memory element and the hard mask during self-aligned 1D NP fabrication. The SiOx layer is exposed to oxygen plasma to get a hydrophilic surface. Then the substrate was slowly immersed in a glass vessel filled with DI water and 200-nm-diameter polystyrene NSs, and an ordered monolayer of NS with dense hexagonal packing was reproducibly formed by slowly lifting the substrate vertically out of the DI water [4]. The polystyrene NSs were isolated from each other by reactive ion etching (RIE) in oxygen-plasma. The NS pattern was transferred into the SiOx layer by SiOx RIE to form a 1R array. The NS layer was removed by sonication in water for 15 min, followed by a DSE process in Bosch mode [5] to form the NP array. The average NP height and diameter is 1.3 μm and 130 nm, respectively
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(Figs. 1e and 1f). A tungsten (W) probe tip (~10 μm radius) was used as top electrode and a vacuum probe chamber was used for electrical test. Thus, each probe tip contacts ~ 7800 nano-pillars. Since the ReRAM operates through a single filament, except for HRS current, the measurement results (i.e. V set, Vreset, Ion, VEF) reflect the characteristic of a single NP. Fig. 2 and Fig. 3 show the electroforming process with backward scan effect [6] and 10 resistive switching (RS) cycles in a 1R element. Overall, the NP device electroforming voltage is less than the 18 V typically required to electroform MOSCAP devices [6], possibly due to a plasma-induced weakening of the SiOx layer during DSE (inset of Fig. 3). The I-V response is largely independent of device area and architecture, but larger device area results in a decrease in reset voltage (Fig. 4). Fig 5 demonstrates the AC pulse response for set and reset in the 50ns regime and multi-level programming capability where the HRS/LRS resistance ratio is at least one-order of magnitude during 104 switching cycles (not show here). Fig. 6 shows I-V curves of 30 1D1R switching cycles. The switching voltage values for Set and Reset in 1D-1R are larger than in 1R configuration. Also, the 1D-1R switching transitions are more gradual (Fig. 6) as compared to the sharp 1R transitions (Fig. 3), possibly due to the series 1D-1R connection of the integrated structure. Compared to previous work (Fig. 7), the HRS current reported here is larger than in MOSCAP structures [6], possibly due to the multiple parallel leakage paths in the NP array. By controlling the reset stop voltage, HRS current can be controlled and multi-bit operation as well as good non-volatile retention properties are demonstrated (Fig. 8 and Fig. 9). The 10% readout-margin can allow for 1Gbit array due to the low reversecurrent and large LRS/reverse-current ratio. The array allowance decreases while readout voltage reducing (Fig. 10).
CONCLUSIONS We have demonstrated capability to fabricate high-density, largearea 1D-1R NP arrays of intrinsic SiOx-based ReRAM. Basic RS performance, AC pulsed switching speed in the 50 ns regime, and multi-bit operation are demonstrated and indicate good potential for high-speed NVM. The demonstrated NSL fabrication process has great potential not only for maskless electronics, but also provides a fast and economical solution for wafer-scale 1D-1R ReRAM applications.
ACKNOWLEDGMENT This work was partially supported by the Judson S. Swearingen Regents Chair in Engineering at the University of Texas at Austin.
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B. Govoreanu et, al., IEDM, 729 (2011). R. Waser et. al., Adv. Mater. 21, 2632 (2009). Y. F. Chang et. al., DRC 71th, 135 (2013). L. Li et al., J. Mater. Chem., 21, 40 (2011). F. Lars, et. al., IEEE Electron Device Lett. 34, 1226 (2013). Y. F. Chang et. al., Appl. Phys. Lett. (2013). (Accepted)
FIGURE 1. Nano-pillar (NP) 1D-1R process flow and sequential SEM images using nano-sphere (NS) lithography: (a) NS deposition. (b) Oxygen plasma shrinking. (c) Hard-mask patterning. (d) DSE. (e)-(f) are the statistical distribution of 1R diameter and NPs height.
FIGURE 2. Electrical soft-breakdown and electroforming processes.
FIGURE 5. Pulsed switching property with fixed reset pulse width (DC set) and fixed set pulse height conditions (DC reset).
FIGURE 8. Electrical characteristics (HRS, LRS and Vset) as a function of reset stop voltage in NPs-type 1D-1R configuration.
FIGURE 3. 10 times I-V resistive switching behavior of 1R (inset: VForming distribution).
FIGURE 4. I-V curves and set/reset voltage versus device active area for a range of ReRAM device architectures.
FIGURE 6. I-V resistive switching behavior in NPs-type 1D-1R configuration (inset: diode behavior and simulation result).
FIGURE 7. HRS/LRS versus device active area for MOSCAP and NPs-type 1R structures.
FIGURE 9. Retention measurement results of a series of reset stop voltage.
FIGURE 10. Normalized readout margin as a function of the number of word/bit lines for different readout voltage.
