T. Temel A new current-mode multi-input looser-take-all minimum circuit is presented. The circuit has very compact and simple architecture with only three transistors per input. It is shown that the proposed circuit exhibits better performance and is more robust to parametric variations compared to its previous counterparts.
Introduction: Minimum (MIN) and maximum (MAX) are two key operations to determine the position and magnitude of the smallest and largest inputs, respectively, to most nonlinear information processing systems which involve fuzzy logic, neural computation, pattern recognition, etc. Contrary to simple and direct implementations of MAX in current-mode, generally attributed to the winner-take-all (WTA) circuit described by Lazzaro et al. in [1], MIN has been implemented indirectly in different forms which can be classified into three main groups. The first group relies on the algebraic manipulation of mutual relationship between MIN and MAX, i.e. De Morgan duality: current-mode design in [2] implements MIN by using bounded-difference with simple current-mirrors, while [3] attempts the design problem through absolute-difference between inputs with cascoded current-mirrors. On the other hand, a direct design approach with the WTA-MAX circuit by using the logical-complement of the quantity of interest is introduced in [4]. Despite the well-established algebraic representation and architectural regularity, major problems of the first group are of high-level complexity, which mostly is of a polynomial in the number of inputs; degraded dynamic range owing to intermediate operations such as complement, and dependency on reference values. The second group tackles the design problem by exploiting the WTA paradigm within a reverse activation loop to yield a response corresponding to the minimum of the inputs, which is the so-called looser-take-all (LTA) operation: designs given in [5] employ currentcontrolled voltage-feedback to achieve this while the architecture in [6] relies on comparison of successive inputs providing a feedback signal to drive a WTA circuit. The implementation presented in [7] converts input currents into respective intermediate voltages which will then be applied to a WTA circuit. The main advantage of this group of studies is concurrent processing of inputs and modularity. However, the overall performance usually depends on the feedback structure [5, 6] and the gain/conversion factor on input currents [7] and output loop to reproduce the minimum of the inputs. The third and last group, e.g. [8], embarks on comparing currents of stacked inputs and coding the consequent output voltages for LTA-MIN operation. The major shortcoming of this approach is the restriction on the number of inputs limited by supply voltage and increased complexity as the number of inputs increases. In this Letter, we propose a new multi-input, current-mode CMOS LTA-MIN circuit with a very modular structure. The proposed design requires only three transistors per input. Simulation results indicate that the proposed circuit exhibits better characteristics in terms of speed, power consumption and robustness to design errors with smaller layout area than the previous designs. Description of proposed circuit: A multi-input LTA-MIN circuit can be formed as shown in Fig. 1. In the circuit, node U is common to the gates of transistors MiA. Current source Ib is used to provide a path between VDD and U. Transistor MOA functions as a voltage-controlled current source and its source is biased by MOC which also biases the gate of transistor MiC in input cells. In each cell, MiC converts the respective input current into a voltage at its drain. Source-to-gate voltages of MiBs compete at node U at which the maximum one corresponding to smallest input current is selected as the winner. It should be noted that owing to the source follower operation at node U, voltage variation at the drain of MiC is shifted to node U which forces the MiBs in loser cells to enter the triode region while the winner-cell MiB takes over Ib. The voltage shift at node U reduces the saturation voltage of MOA by almost the same amount and forces it to enter the triode region where it functions as a linear current source controlled by the voltage at node U because its source and drain are kept at almost fixed values. Therefore, the output current will follow the winning input current. Linearity in the transfer characteristics between output and inputs is determined by MiB of the
winner cell and the value of Ib. Transistor MiB in each cell is sized such that it operates with a small saturation voltage for a given Ib so that the output adapts itself to minimum input as closely and as fast as possible. The output current can be taken out via either a p-type mirror between O and VDD or MOC can be mirrored while node O is tied up to VDD. VDD O Ii
I1
In
MiA
M1A L1
MiB
M1C
U
MOA MnB
Ln
MiC
Iout
Ib
MnA
Li
M1B
MnC
MOC
Cell i Transistor W(mm)/L(mm)
MiA
MiB
0.6/0.24
2.16/0.24
MiC 1.32/0.24
MOA 2.44/0.24
MOC 1.44/0.24
Fig. 1 Proposed n-input LTA-MIN circuit
Simulation results: The proposed MIN architecture and its predecessors in [2, 5 – 8] were designed and simulated as three-input circuits for comparison by using TSMC HSPICE (level-49) parameters in full post-layout extraction with 1.8 V supply voltage. In all designs, bodybiased effects were included and transistors were sized for an optimum DC transfer characteristic. The bias currents, e.g. Ib , for this study and [7], and Io and Ip for the improved version in [5], were all set to the same value with suitable diode-connected transistors. Input currents were reproduced and directed as sourcing, if necessary, by using appropriate mirror circuits. In the proposed design, the circuits used for input sourcing were simple p-type mirrors with aspect ratio of W(mm)/L(mm) ¼ 1.44/ 0.24. To allow the reproduction of output current, a diode-connected PMOS transistor with aspect ratio of W(mm)/L(mm) ¼ 1.44/0.24 was used between node O and VDD. The bias current Ib was set to 1 mA and was produced by a diode-connected PMOS transistor with aspect ratio of W(mm)/L(mm) ¼ 0.36/1.08 between VDD and node U. Postlayout HSPICE transient simulation results are shown in Fig. 2 where the output is indicated with solid lines. 80 magnitude, mA
High-performance current-mode multi-input loser-take-all minimum circuit
I1
I2
I3
60 40
Iout
20
0
25
50
75
100 125 time, ns
150
175
200
Fig. 2 Transient simulation results of proposed MIN circuit for three inputs
Considered designs were also investigated concerning the discrepancies in linear transfer between inputs and output, which can be accounted for by random errors, mainly due to transistor mismatches or variations in design parameters such as aspect ratios and threshold voltages. For each design, I1 was incremented from 20 mA to 60 mA by 20 mA while I2 and I3 were both kept at 70 mA. For each value of I1 , a 100-iteration Monte-Carlo DC simulation using normal-Gaussian distribution which represents the relative variations in aspect ratios (W/L) with standard deviation sDW/W,DL/L ¼ 5% and variations in zero-body-bias threshold voltages (VTO) with standard deviation sDVTO ¼ 25 mV, respectively, was performed. Given a value of I1 for each design, standard deviation of the maximum value of absolute relative difference, d ¼ max(jIout 2 Iminj/Imin), where Imin ¼ min(I1 , I2 , I3), found at each iteration was calculated as an evaluation quantity. Results of the error analysis and some important characteristics of transient simulations are shown in Table 1 where the column ‘Number of transistors’ does not regard input reproduction transistors unless necessary in the relevant design.
ELECTRONICS LETTERS 5th June 2008 Vol. 44 No. 12
Table 1: Performance and design characteristics of proposed, (new), and previous three-input MIN circuits sd (%) (I1 ¼ 20/ Number of Average Average Layout Design 40/60 mA) transistors delay (ns) power diss. (mW) area (mm)2 New 13 1.7 0.19 3.8 2.8/2.4/2.3 [2] 21 2.6 0.30 5.3 3.8/3.4/2.9 [5] 18 2.4 0.26 5.1 3.4/2.9/2.6 [6] [7] [8]
18 14 19
2.5 2.2 2.6
0.23 0.23 0.25
5.0 4.6 5.3
3.4/3.1/2.7 3.2/2.8/2.5 3.6/3.3/3.0
Conclusions: A new, high-performance current-mode multi-input LTAMIN circuit is described. The circuit does not need any indirect, intermediate operations to fulfil the desired processing of inputs. It is of very simple and modular architecture, which allows easy cascading of similar stages. Simulation results indicate that the proposed circuit has better operational performance in terms of speed, power consumption with smaller layout area and it is more robust to parametric variations compared to previous designs. Acknowldgment: This work is supported by the Scientific and Technological Research Council of Turkey (TUBITAK) under project no. 107E059.
References 1 Lazzaro, J., Ryckebusch, R., Mahowald, A., and Mead, C.: ‘Winner-takeall networks of O(n) complexity’ in Touretzky, D. (Ed.): ‘Advances in neural information processing systems I’ (Morgan Kaufmann, San Mateo, CA, 1989), pp. 703–711 2 Sasaki, M., Inoue, T., Shirai, Y., and Ueno, F.: ‘Fuzzy multiple-input maximum and minimum circuits in current-mode and their analyses using rounded difference equations’, IEEE Trans. Comput., 1990, 39, (6), pp. 768– 774 3 Mesgarzadeh, B.: ‘A CMOS implementation of current-mode min-max circuits and a sample fuzzy application’. Proc. IEEE Conf. on Fuzzy Systems, Budapest, Hungary, 2004, Vol. 2, pp. 941– 946 4 Yakout, M.A., El-Masry, E.I., and Abd-El Fattah, A.I.: ‘Hardware realization of analog CMOS current-mode minimum circuit’. Proc. Nat. Conf. on Radio Science, Cairo, Egypt, 1998, D8/1– D8/7 5 Donckers, N., Dualibe, C., and Verleysen, M.: ‘A current-mode CMOS loser-take-all with minimum function for neural computations’. Proc. IEEE Int. Symp. on Circuits and Systems, (ISCAS), Geneva, Switzerland, 2000, Vol. 1, pp. 415–418 6 Asloni, M., Khoei, A., and Hadidi, K.: ‘Design of analog current-mode looser-take-all circuit’, IEICE Trans. Electron., 2006, E89-C, (6), pp. 819– 822 7 Huang, C.Y., Wang, C.J., and Liu, B.D.: ‘Modular current-mode multiple input minimum circuit for fuzzy logic controllers’, Electron. Lett., 1996, 32, (12), pp. 1067–1069 8 Dualibe, C., Jespers, P., and Verleysen, M.: ‘Embedded fuzzy control for automatic channel equalization after digital transmissions’. Proc. IEEE Int. Symp. on Circuits and Systems, (ISCAS), Sydney, Australia, 2001, Vol. 3, pp. 173– 176
# The Institution of Engineering and Technology 2008 25 April 2008 Electronics Letters online no: 20081174 doi: 10.1049/el:20081174 T. Temel (Engineering Faculty, Bahc¸es¸ehir University, Bes¸iktas¸, Istanbul 34100, Turkey) E-mail:
[email protected];
[email protected]
ELECTRONICS LETTERS 5th June 2008 Vol. 44 No. 12
