IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 25, NO. 8, AUGUST 2010
1975
Implementation and Performance Evaluation of a Fast Dynamic Control Scheme for Capacitor-Supported Interline DVR Carl Ngai-Man Ho, Member, IEEE, and Henry Shu-Hung Chung, Senior Member, IEEE
Abstract—The implementation of a fast dynamic control scheme for capacitor-supported interline dynamic voltage restorer (DVR) is presented in this paper. The power stage of the DVR consists of three inverters sharing the same dc link via a capacitor bank. Each inverter has an individual inner control loop for generating the gate signals for the switches. The inner loop is formed by a boundary controller with second-order switching surface, which can make the load voltage ideally revert to the steady state in two switching actions after supply voltage sags, and also gives output of low harmonic distortion. The load-voltage phase reference is common to all three inner loops and is generated by an outer control loop for regulating the dc-link capacitor voltage. Such structure can make the unsagged phase(s) and the dc-link capacitor to restore the sagged phase(s). Based on the steady-state and small-signal characteristics of the control loops, a set of design procedures will be provided. A 1.5-kVA, 220-V, 50-Hz prototype has been built and tested. The dynamic behaviors of the prototype under different sagged and swelled conditions and depths will be investigated. The quality of the load voltage under unbalanced and distorted phase voltages, and nonlinear inductive loads will be studied. Index Terms—Boundary control, dynamic voltage restoration (DVR), inverters, power quality, voltage sag.
I. INTRODUCTION LECTRONIC systems operate properly as long as the supply voltage stays within a consistent range. There are several types of voltage fluctuations that can cause the systems to malfunction, including surges and spikes, sags, harmonic distortions, and momentary disruptions. Among them, voltage sag is the major power-quality problem [1]. It is an unavoidable brief reduction in the voltage from momentary disturbances, such as lightning strikes and wild animals, on the power system. Although most of them last for less than half a second, this is often long enough for many types of loads to drop out. Typical
E
Manuscript received February 4, 2010. Date of current version June 25, 2010. This work was supported by a grant from the Research Grants Council of the Hong Kong Special Administrative Region, China, under Project CityU 112407. This paper was presented in part at the Applied Power Electronics Conference and Exposition 2007, Anaheim, CA, Feb. 25–Mar. 1. Recommended for publication by Associate Editor J. HR Enslin. C. N.-M. Ho is with ABB Corporate Research, Ltd., 5405 Baden-D¨attwil, Switzerland (e-mail:
[email protected]). H. S.-H. Chung is with the Centre for Power Electronics, City University of Hong Kong, Kowloon, Hong Kong (e-mail:
[email protected]). Color versions of one or more of the figures in this paper are available online at http://ieeexplore.ieee.org. Digital Object Identifier 10.1109/TPEL.2010.2044587
examples include variable speed drives, motor starter contactors, control relays, and programmable logic controllers. Such an unplanned stoppage can cause the load to take a long time to restart and can lead to high cost of lost production [2]. Dynamic voltage restorer (DVR) is presently one of the most cost-effective and thorough solutions to mitigate voltage sags by establishing proper quality voltage level for utility customers [3]. Its function is to inject a voltage in series with the supply and compensate for the difference between the nominal and sagged supply voltage. The injected voltage is typically provided by an inverter, which is powered by a dc source [4]–[7], such as batteries, flywheels, externally powered rectifiers, and capacitors. Voltage restoration involves determining the amount of energy and the magnitude of the voltage injected by the DVR. Conventional voltage-restoration technique is based on injecting a voltage being in-phase with the supply voltage [7]–[10]. The injected voltage magnitude will be the minimum, but the energy injected by the DVR is nonminimal. In order to minimize the required capacity of the dc source, a minimum energy injection (MEI) concept is proposed in [10]–[13]. It is based on maximizing the active power delivered by the supply mains and the reactive power handled by the DVR during the sag. Determination of the injected-voltage magnitude is based on a real-time iterative method to minimize the active power injection by the DVR. This can then enhance the ride-through capability. However, the operation of each phase is individually controlled. There is no energy interaction between the unsagged phase(s) and the sagged phase(s), in order to enhance the voltage restoration [14], [15]. Moreover, as the computation method is purely based on sinusoidal waveforms, the implementation is complicated in distribution network with nonlinear load. A sliding window over one line cycle of the fundamental frequency is proposed in [13] to determine the active and reactive power at the fundamental frequency. The lengthy computation time of the injected voltage phasor will cause output distortion after a voltage sag. Instead of using an external energy storage device, the methods in [16] and [17] take the active power for the inverter from the transmission system via a shunt-connected rectifier. The series inverter by its self has the capability to provide real-series compensation to the line. The rectifier-based source requires a separate service supply, while the battery-based source requires regular maintenance and is not environment friendly. A theoretical study of the capacitorsupported DVR for unbalanced and distorted loads is recently
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1976
IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 25, NO. 8, AUGUST 2010
a capacitor bank, formed by two capacitors. Each capacitor has the value of Cdc . The inverter shown in Fig. 1 is a halfbridge configuration. However, the operation is similar in the full-bridge configuration. The DVR is operated as a controllable voltage source vd,n , where n represents either phase a, b, or c. It is connected between the supply and the load. The relationship among the supply voltage vs,n , the load voltage vo,n , and vd,n is vd,n (t) = vs,n (t) − vo,n (t).
Fig. 1. utility.
Structure of the proposed interline DVR and its connection to the
proposed in [18]. No external source is required in the DVR. The required phase and magnitude of the inverter load-voltage phasor are derived by considering the energy balance between the supply and the load, but the advantage is offset by the lengthy digital transformation and inversion of symmetrical components and calculation of the power consumption. The waveshape of the load voltage will be distorted and will take a relatively long settling time. As the supply voltage is assumed to be sinusoidal in the calculation, the load voltage will be affected and distorted with nonsinusoidal supply voltage and load current [18]. A single-phase capacitor-supported DVR is proposed in [19]. The load voltage can ideally be reverted to the steady state in two switching actions after voltage sags. By extending the concept, an analog-based three-phase capacitor-supported interline DVR is presented. It features the following operational characteristics. 1) By extending the fast transient control scheme proposed in [19]–[21], the load voltage can ideally be restored in two switching actions after a voltage sag. This can assure near-seamless load voltage and power. 2) The load voltage balance and quality can be maintained, even if the supply is unbalanced and/or has harmonic distortion, and the load is nonlinear and/or unbalanced. 3) As the three inverters share the same dc link and the controller acts on the three inverters together, the unsagged phase(s) will help restore the sagged phase(s) during the voltage sag. A 1.5-kVA, 220-V, 50-Hz prototype has been built and tested. The steady-state and dynamic behaviors of the prototype will be provided. II. PRINCIPLES OF OPERATION Fig. 1 shows the circuit schematic of the DVR with threephase transmission system. It consists of inverters, output LC filters, and injection transformers. The dc side is connected to
(1)
Fig. 2 shows the phasor diagrams of vs,n , vo,n , vd,n , and the load current io,n in voltage sag and unbalanced conditions. Fig. 3 shows the control block diagram of proposed control scheme. The control scheme consists of two main loops. The first control loop, namely inner loop, is formed in each phase. It is used to generate the gate signals for the switches in the ∗ . inverter, so that vd,n will follow the DVR output reference vd,n This loop has fast dynamic response to external disturbances. Its operating principle is based on extending the boundary control technique with second-order switching surface in [19]–[21]. ∗ . The second loop, namely outer loop, is used to generate vd,n Based on (1) ∗ ∗ vd,n (t) = vs,n (t) − vo,n (t)
(2)
∗ where vo,n is the load-voltage reference and is generated by the phase-lock loop (PLL). The outer loop is used to regulate the dc-link voltage by adjusting the phase of the inverter load voltage with respect to the load current. Its bandwidth is set much lower than the line frequency. The purpose is to attenuate the undesirable signals, which are due to the ac component on the dc-link voltage and the load current, getting into the loop. Since the inner and outer loops have different dynamic behaviors, the controller will react differently in the voltage sags of short and long durations. If the duration of the voltage sag is short [22]–[25], typically less than 0.5 s, the inner loop will react immediately and maintain the waveshape of the load voltage. The outer loop is relatively inert during the period. The sagged phase(s) will be supported purely by the capacitor bank. The capacitor voltage will decrease. After the voltage sag, the outer loop will start reacting to the decrease in the capacitor voltage. The capacitor will be charged up from the supply by adjusting the phase angle of the inverter output. If the duration of the voltage sag is long, the inner loop will keep the waveshape of the load voltage and the outer loop will regulate the dc-link voltage. Thus, the sagged phase(s) will be supported by the dc link, while electric energy will also be extracted from the unsagged phase(s) through the dc link. In the steady-state operation, as the frequency response of the inner loop is very fast, the waveshape of the load voltage can be kept sinusoidal, even if there are harmonic distortions in the supply voltage and the load current. Moreover, with the interline energy flow in the outer-loop control, the output quality can be maintained, even if there is an unbalanced supply voltage. ∗ is fixed because the load At any time, the amplitude of vo,n ∗ has the same voltage is regulated at the nominal value. vo,n
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HO AND CHUNG: IMPLEMENTATION AND PERFORMANCE EVALUATION OF A FAST DYNAMIC CONTROL SCHEME
Fig. 3.
1977
Block diagram of the proposed controller.
where Vsm ,a , Vsm ,b , and Vsm ,c are the peak values of the supply voltages of the phases a, b, and c, respectively, and ω is the angular line frequency. III. REVIEW OF INNER LOOP The inner-loop control strategy is by using boundary control with second-order switching surface. The control concept has been well documented in [19]. A brief review will be given in this section. In one leg of the three-phase half-bridge inverter, which is shown in Fig. 1, as S1,n and S2,n are operated in antiphase and the output inductor current is continuous, two possible switching modes are derived, and their state-space equations are shown as follows. When S1,n is OFF and S2,n is ON 0 −1/L −1/2L 0 x˙ n = xn + un 1/C −1/RL ,n C 0 1/RL ,n C (4a) vd,n = [ 0
1 ]xn .
When S1,n is ON and S2,n is OFF 0 −1/L 1/2L x˙ n = xn + 1/C −1/RL ,n C 0
(4b) 0 un 1/RL ,n C (5a)
Fig. 2. Steady-state vector diagrams with different sagged conditions. (a) v s , a is changed from 220 to 120 Vrm s . (b) Unbalanced three-phase voltages with v s , a = 210 Vrm s , v s , b = 190 Vrm s , and v s , c = 240 Vrm s .
∗ frequency as vs,n , and the phase angle β between vo,n and vs,n is controlled by the signal vβ shown in Fig. 3. The supply voltages can be expressed as follows:
vs,a (t) = Vsm ,a cos ωt
(3a)
vs,b (t) = Vsm ,b cos (ωt − 120◦ ) ◦
vs,c (t) = Vsm ,c cos (ωt + 120 )
(3b) (3c)
vd,n = [ 0
1 ]xn
(5b)
where xn = [iL ,n vC ,n ]T , un = [vdc vs,n ]T , and RL ,n is the fictitious resistance showing the ratio between the load voltage and load current. Fig. 4(a) and (b) shows the equivalent circuits of the two modes corresponding to (4) and (5). By solving (4) and (5) with different initial values, families of state-plane trajectories shown in Fig. 5 can be derived. The solid lines are named as the positive trajectories, while the dotted lines are named as the negative trajectories. The positive trajectories show the trajectories of the state variables when S1,n is ON and S2,n is
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on estimating the state trajectory after a hypothesized switching action. As the switching frequency of the switches is much higher than the signal frequency, the load current io is relatively constant over a switching cycle. The gate signals to the switches are determined by the following criteria. For the sake of simplicity and without loss of generality, vc,n and vd,n in Fig. 1 are assumed to be equal [19]. A. Criteria for Switching S1,n OFF and S2,n ON S1,n and S2,n are originally ON and OFF, respectively. S1,n and S2,n are going to switch OFF and ON, respectively. Thus, according to [19], the criteria for switching S1,n OFF and S2,n ON are as follows: vd,n (t1 ) ≥ vd,n ,m ax −
1 L i2 (t1 ) 2C (vdc (t1 )/2) + vd,n (t1 ) C ,n (6)
and iC ,n (t1 ) ≥ 0. Fig. 4. Equivalent circuits of one phase in the inverter system. (a) S 1 , n is OFF and S 2 , n is ON. (b) S 1 , n is ON and S 2 , n is OFF.
(7)
B. Criteria for Switching S1,n ON and S2,n OFF S1,n and S2,n are originally OFF and ON, respectively. S1,n and S2,n are going to switch ON and OFF, respectively. Thus, according to [19], the criteria for switching S1,n ON and S2,n OFF are as follows: vd,n (t3 ) ≤ vd,n ,m in +
1 L i2 (t3 ) 2C (vdc (t3 )/2) − vd,n (t3 ) C ,n (8)
and iC ,n (t3 ) ≤ 0.
Fig. 5.
State-plane trajectories of the inverter.
∗ , the general Based on (6)–(9) and vd,n ,m in = vd,n ,m ax = vd,n 2 form of σ is defined as follows: 1 ∗ σ 2 [iL ,n (t), vd,n (t)] = vd,n (t) − vd,n (t) k vdc (t) + sgn[iC ,n (t)]vd,n (t) × 2
+ sgn[iC ,n (t)]i2C ,n (t) OFF. The negative trajectories show the trajectories of the state variables when S1,n is OFF and S2,n is ON. As discussed in [20] and [21], the tangential component of the state-trajectory velocity on the switching surface determines the rate at which successor points approach or recede from the operating point in the boundary control of the switches. An ideal switching surface σ i that gives fast dynamics should follow the only trajectory passing through the operating point [31]–[33]. Although σ i can ideally go to the steady state in two switching actions during a disturbance, its shape is loaddependent and requires sophisticated computation to determine the only positive and negative trajectories that pass through the operating point. A second-order switching surface σ 2 , which is close to σ i around the operating point, is derived. The concept is based
(9)
(10)
where k = L/2C. Fig. 5 shows the load line and the second-order switch2 ing surface (σ−127 V ) when the required output voltage of the DVR is −127 V. Fig. 6 shows the simulated state-plane trajectory of the DVR for compensating vs,n changing from 220 to 130 V. The states of the first and the second switching actions are labeled. The switching surface described in (10) is implemented with analog circuitry. IV. CHARACTERISTICS OF OUTER LOOP A. Steady-State Characteristics The function of the outer loop is to regulate vdc at the refer∗ . By applying the conservation of energy [26], ence value of Vdc the DVR will ideally have zero-average real power flow at the
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HO AND CHUNG: IMPLEMENTATION AND PERFORMANCE EVALUATION OF A FAST DYNAMIC CONTROL SCHEME
1979
TABLE I SPECIFICATIONS OF THE DVR
TABLE II PARAMETERS OF THE PLL AND TRANSDUCER GAINS
Fig. 6. 130 V.
Simulated state trajectory of the DVR for v s , n changing from 220 to
TABLE III COMPONENT VALUES OF THE DVR
steady state. Thus Ps,a + Ps,b + Ps,c = Po,a + Po,b + Po,c Pa + P b + P c = 0
(11) (12)
Ps,n = vs,n io,n cos(θn − β)
(13)
Po,n = vo,n io,n cos θn
(14)
Pn = vd,n io,n cos φn
(15)
where Ps,n , Po,n , and Pn are the input, output powers, and power transferred of the each phase, respectively, io,n is the load current of each phase, θn is the phase angle between vo,n and io,n , β is the phase angle between vs,n and vo,n , and φn is the phase angle between vd,n and io,n . Under supply-voltage interruption, the outer loop will adjust the value of β. The DVR will generate the required magnitude and phase of vd,n in each phase individually. The DVR will then absorb (deliver) electric energy from (to) the dc link. As the adjustment of β is common to the three phases, the sagged phase(s) will be supported by the capacitor bank and the unsagged phase(s). The corresponding equations of vo,n are as follows: vo,a (t) = Vom ,a cos (ωt − β)
(16a) ◦
vo,b (t) = Vom ,b cos (ωt − 120 − β)
(16b)
vo,c (t) = Vom ,c cos (ωt + 120◦ − β)
(16c)
where Vom ,n is the peak load voltage of phase n. Fig. 2 shows the steady-state phasor diagrams with one-phase sagged and three-phase voltage balancing, respectively. The parameters used are based on Tables I–III. In Fig. 2(a), vs,a is reduced to 120 V, while the other phases are at the nominal value of 220 V. By increasing the value of β, vd,a is established by the DVR and vo,a can be kept at 220 V. Thus, part of the energy supplied to phase-a load is supported by phases b and c.
In Fig. 2(b), all three phases are unbalanced, where vs,a = 210 V, vs,b = 190 V, and vs,c = 240 V. Again, by adjusting the value of β, vo,a , vo,b , and vo,c are regulated at 220 V. For the phase transformation between β and φn αn = −(β − φn − θn )
(17)
where αn is the phase difference between vs,n and vd,n . Based on Fig. 2(a) and by using (15) and (17), it can be shown that the steady-state power-transfer equation can be expressed as follows: 2 + v 2 − 2v Pn = io,n vo,n o,n vs,n cos β s,n −v cos β v s,n o,n . ×cosβ −θn +cos−1 2 2 vo,n +vs,n −2vo,n vs,n cos β (18) Detailed derivation of (18) is given in the Appendix. The values of vs,n , vo,n , io,n , and θn are different in each phase. Thus, the power flow of each phase inverter is different. β is controlled by the outer loop in order to achieve power equilibrium in the system, and thus, satisfy (11) and (12). B. Small Signal Modeling Fig. 7 shows the small-signal model of the outer loop. It consists of the transfer characteristics of the inner loop, inverter,
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Fig. 8.
Fig. 7.
5) PLL: The PLL consists of three components, including the phase detector (PD), loop filter (LF), and the voltagecontrolled oscillator (VCO) [27]. Based on [19], the small-signal model of the PLL is as follows:
Small-signal model of the outer loop.
PLL, and power-flow controller. As the inner loop has much faster dynamic response than the outer loop, the small-signal transfer function of the inner loop is unity. The transfer function of the inverter describes the small-signal behaviors between β and vdc . The functional blocks of power stage and controller are derived as follows. 1) Relationship Between vdc and pdc : The small-signal dclink voltage to dc-power-transfer function Tp (s) is as follows: Tp (s) =
2 ∆vdc (s) = ∆pdc (s) sCdc Vdc
(19)
where Vdc is the steady-state values of vdc . 2) Relationship Between Power Flow and the Phase of vd With Respect to io,n in Each Phase: The small-signal DVRphase-to-power transfer function Tr,n (s) equals ∆pn (s) = −Vd,n io,n (20) Tr,n (s) = ∆φn (s) where Vd is the steady-state values of vd . 3) Phase Transformation Between β and φ in Each Phase: The transfer function Tpt,n (s) representing the transformation between β and φ is Vs,n − Vo,n cos B Vs,n ∆φn (s) = ∆β(s) Vd,n V 2 + V 2 −2V V cos B o,n s,n o,n s,n (21) where Vs , Vo , and B are the steady-state values of vs , vo , and β, respectively. 4) Phase Transformation Between β and vdc in Inverter: The transfer function Tinv (s) of the inverter is as follows: Tpt,n (s) =
Tinv (s) =
2 ∆vdc (s) =− (Vs,a io,a cos αa ∆β(s) sCdc Vdc + Vs,b io,b cos αb + Vs,c io,c cos αc ).
(22)
Detailed derivation of (19)–(22) are given in the Appendix.
TC (s) =
Circuit schematic of the power-flow controller.
TPLL (s) =
Tvco (s)FC (s) ∆β(s) = ∆vβ (s) 1 − Tvco (s)Tp d (s)FL (s)
ωn2 (23) + 2ξωn s + ωn2 where A = −(Rl /Rc Kp d ), ξ = 1/2 τ Kp d Kl Kvco , and ωn = Kp d Kl Kvco /τ , K p d , Kl , Kvco are the constant gains of PD, LF and VCO, respectively. 6) Power-Flow Controller: The function of the power-flow ∗ , which controller is to regulate vdc at the reference voltage Vdc is determined by the voltage ratings of the capacitor and the switches. Charging or discharging the capacitor Cdc is achieved by adjusting φn in three phases individually. The regulation action is performed by the error amplifier shown in Fig. 8. The transfer function TC (s) can be shown in (24), at the bottom of the page. =A
s2
V. SIMPLIFIED DESIGN PROCEDURES The values of L, C, and Cdc in the inverter, R1 , R2 , C1 , and C2 in the power-flow controller are designed as follows. A. Design of L and C in the Inverter The values of L and C in the output filters are determined by considering the maximum voltage drop across the inductor vL ,D at the maximum line current Io,m ax , angular line frequency ω, maximum ripple current Iripple , and angular switching frequency ωsw . As most of the load current is designed to flow through L, the value of L is determined by considering that its voltage drop vL ,D is small at the maximum line current Io,m ax . Thus vL ,D ωLIo,m ax < vL ,D ⇒ L < . (25a) ωIo,m ax As the inverter output consists of high-frequency harmonics, the fundamental component of the ripple current through the filter is designed to be less than Iripple . For the sake of simplicity
∆vβ s2 + ((1/R2 C2 ) + (1/R2 C1 ) + (1/R1 C2 ))s + (1/R1 R2 C1 C2 ) . =− ∆vdc s (s + (C1 + C2 )/(R2 C1 C2 ))
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(24)
HO AND CHUNG: IMPLEMENTATION AND PERFORMANCE EVALUATION OF A FAST DYNAMIC CONTROL SCHEME
Fig. 9.
1981
Small-signal characteristics, T O L (s).
in the calculation, the load impedance at the switching frequency is assumed to be infinite. Thus 1 2vdc < Iripple π ωsw L − (1/ωsw C) ⇒C>
1 . ωsw (ωsw L − (2vdc /πIripple )
(25b)
The nominal switching frequency is chosen to be a few hundred times the line frequency. vL ,D is chosen to be 1% of the line voltage, and Iripple is chosen to one half of the peak of the line current. As shown in Table I, ωsw = 300 ω, vL ,D = 2 V, and Iripple = 2.6 A for the designed prototype. Based on (25) and stated criteria, the values of L and C in the output filters are determined. B. Design of Cdc in the Inverter The value of Cdc is determined by Cdc =
4 (vo,nor −vs,m in ) (io,a cos θa +io,b cos θb +io,c cos θc ) tres 2 vdc,ref − 8 (vo,nor − vs,m in )2 (26)
where vo,nor and vs,m in are nominal value of load voltage and minimum voltage of supply voltage in specification, respectively, tres is duration of restoration. Detailed derivation of (26) is given in the Appendix. C. Design of R1 , R2 , C1 , and C2 in the Power-Flow Controller The pole and zeros are designed as follows: ψ (27) 20 Detailed derivation of (27) is given in the Appendix. Typically, ψ = 20 is chosen, and the ratio of ωz 1 and ωz 2 is chosen to be at least 100, in order to avoid overlapping in the two zeros. Therefore log ωp = log ωz 2 −
log ωz 1 = log ωz 2 − 2.
(28)
Fig. 10. Waveforms at three sagged conditions. (a) v s , a is changed from 220 to 120 Vrm s . (b) v s , a , v s , b , and v s , c are changed from 220 to 150 Vrm s .
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Fig. 12. Dynamic behaviors of v d c in the three sagged conditions shown in Fig. 10. (a) Single-phase sag in Fig. 10(a). (b) Three-phase sag in Fig. 10(b).
Based on (29)–(31), R1 , R2 , C1 , and C2 are designed by putting a value into one of them. Fig. 9 shows the loop gain TOL (s), it is based on the specifications and designed component values listed in Tables II and III. The bode plot shows operation range, the frequency between ωcross,m in , and ωcross,m ax within the stable regions. VI. EXPERIMENTAL VERIFICATIONS
Fig. 11. Enlarged transient waveforms in the three sagged conditions shown in Fig. 10. (a) Single-phase sag in Fig. 10(a). (b) Three-phase sag in Fig. 10(b).
Based on (24), we have 1 1 1 + + ωz 1 + ωz 2 = R2 C2 R2 C1 R1 C2 1 ωz 1 ωz 2 = R1 R2 C1 C2 ωP =
C1 + C2 . R2 C1 C2
(29)
A 1.5-kVA, 220-V, 50-Hz prototype has been built and tested. The system is supplying to nonlinear inductive loads, P F (power factor) = 0.5. The specifications and the component values are tabulated in Tables I–III. The values of the components are designed by the procedures described in Section V. The prototype has been tested with four different types of voltage disturbances, including voltage sags, voltage swells, supply voltage distortion, and three-phase voltage unbalancing.
(30)
A. Voltage Sags
(31)
Voltage sags are programmed to occur during the supply voltage at the peak value in the following tests. Fig. 10(a) shows the
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1983
Fig. 14. Enlarged transient waveforms in the three swelled conditions shown in Fig. 13. (a) Single-phase swell in Fig. 13(a). (b) Three-phase swell in Fig. 13(b).
Fig. 13. Waveforms at three swelled conditions. (a) v s , a is changed from 220 to 260 Vrm s . (b) v s , a , v s , b , and v s , c are changed from 220 to 260 Vrm s .
waveforms of the DVR when there is a single-phase sag. vs,a is sagged from 220 to 120 V (45% sag). Fig. 2(a) shows the phasor diagram of Fig. 10(a) in steady state. Fig. 10(b) shows the waveform when there is three-phase sag. The three-phase voltage sources are changed from 220 to 150 V. Fig. 11 shows the
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Fig. 16.
Waveforms with all three phase voltages distorted.
Fig. 17. Fig. 16
Harmonic content of the distorted supply voltage and load voltage in
Fig. 15. Dynamic behavior of v d c in three voltage-swell conditions shown in Fig. 13. (a) Single-phase swell in Fig. 13(a). (b) Three-phase swell in Fig. 13(b).
enlarged load-voltage transients in the corresponding sagged. The transients should ideally settle into the steady state in two switching actions. However, as the second-order switching surface has discrepancies with the ideal switching surface [31], the transients require taking three to four switching actions before settling into the steady state. The transition times are 250 and 180 µs, respectively, in the aforementioned two cases. Nevertheless, the transition duration is shorter than some recently proposed control schemes [4], [6], [28]–[30] in similar voltagesag conditions. The responses of inner loop were evaluated in the aforementioned experimental results. Fig. 12 shows the dynamic responses of outer loop, power-flow controller, and the dc-link voltage variations in the two aforementioned cases. The voltage sags start at t1 . The capacitor bank releases energy to the load until t2 . Finally, vdc is regulated to 380 V at t3 . In Fig. 12, (t2 − t1 ) = 310 ms and (t3 − t1 ) = 3.8 s. In Fig. 12(b), (t2 − t1 ) = 250 ms and (t3 − t1 ) = 7.1 s.
is (are) changed from 220 Vrm s to 260 Vrm s . Fig. 14 shows the enlarged load-voltage transients in the two cases. The load voltage can be restored to the steady state in two switching actions, taking about 180 µs in the two cases. Fig. 15 shows the dc-link voltage variations in the two aforementioned cases. The voltage swells start at t1 . The capacitor bank absorbs energy from the grid until t2 . Finally, vdc is regulated to 380 V at t3 . In Fig. 15(a), (t2 − t1 ) = 170 ms and (t3 − t1 ) = 1.5 s. In Fig. 15(b), (t2 − t1 ) = 190 ms and (t3 − t1 ) = 2.7 s.
B. Voltage Swells
C. Harmonic Distortions
Fig. 13(a) and (b) shows the waveforms of the DVR in singlephase and three-phase swells, respectively. The swelled phase(s)
Fig. 16 shows the waveforms of the DVR, when vs,a , vs,b , and vs,c are seriously polluted which contain third-, fifth-, seventh-,
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HO AND CHUNG: IMPLEMENTATION AND PERFORMANCE EVALUATION OF A FAST DYNAMIC CONTROL SCHEME
1985
VII. CONCLUSION A control scheme for three-phase capacitor-supported interline DVR has been presented. By integrating a recently proposed boundary-control method with second-order switching surface (inner loop), the dynamic response has been minimized to two switching actions. The voltage sag, swell, and voltage harmonic distortion have been compensated by this DVR. Moreover, by using series bidirectional inverter as DVR, capacitor banks are used to support the dc link and the sagged phase(s) could be supported by the unsagged phase(s). Long-duration voltage sags, swell, and three-phase voltage unbalance could be overcome by the proposed power-flow controller (outer loop). The method has been verified with a 1.5-kVA system. The performances of the DVR have been demonstrated and evaluated with different power-quality disturbances. Experimental measurements are favorably verified with theoretical results. APPENDIX A. Derivation of (18) By using the cosine law, we have
Fig. 18.
2 2 2 = vo,n + vs,n − 2vo,n vs,n cos β vd,n
(A1)
2 2 2 = vd,n + vs,n − 2vd,n vs,n cos αn . vo,n
(A2)
Based on (A1) and (A2), we have
Waveforms with unbalanced three-phase voltages.
cos αn = and ninth-order harmonic components. The DVR acts as a series-type harmonic-voltage compensator to filter out the harmonic components and provide quality voltage at the output. The waveforms of vo,a , vo,b , and vo,c are all sinusoidal. Fig. 17 shows the harmonic contents of the supply voltage and the load voltage up to 19th harmonics. Even if the phase voltages have the total harmonic distortion (THD) over 42%, the THD of vo,a , vo,b , and vo,c are less than 6%. This confirms the function of the DVR for compensating the supply voltage distortion.
vs,n − vo,n cos β 2 vo,n
2 − 2v + vs,n o,n vs,n cos β
.
(A3)
By substituting (A1), (A3), and (17) into (16), (18) can be obtained. B. Derivation of (19) The energy EC stored in the dc capacitors is equal to 1 Cdc 2 v . (A4) 2 2 dc The power flow of the capacitors in the steady state is equal EC =
to D. Voltage Unbalance Fig. 18 shows the waveforms of the DVR, when three phase supply voltage are unbalanced. In this study, vs,a = 210 V (95%), vs,b = 190 V (86%), and vs,c = 240 V (110%). Fig. 2(b) shows the phasor diagram of the situation. The system is operating in the steady state and the load voltages are all regulated at the nominal value. All these results are in good agreement with the theoretical predictions. The proposed control scheme is for DVR supplying to at least one phase-inductive load, it is equally applicable for resistive load if the dc side of the inverter is powered by an external source for compensating the inverter energy loss. Moreover, the proposed method can be implemented by programming the switching function in the digital controller. Further research will be investigated into the digital implementation of the power-flow controller [35]. This will increase the flexibility of the proposed method.
dvdc 1 Cdc vdc . (A5) 2 dt By introducing small-signal perturbations into pdc and vdc , we have pdc (t) =
pdc (t) = Pdc + ∆pdc (t)
(A6)
vdc (t) = Vdc + ∆vdc (t)
(A7)
and
where Pdc and Vdc , are the steady-state values of pdc and vdc , respectively. By substituting (A6) and (A7) into (A5), it can be shown that d∆vdc 1 Cdc Vdc . (A8) 2 dt After taking the Laplace transformation of (A8), (19) can be obtained. ∆pdc =
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1986
IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 25, NO. 8, AUGUST 2010
C. Derivation of (20)
On the ac side of the inverter, the power flow pac is equal to the sum of power in each phase
By introducing small-signal perturbations into pn , vd,n , and φn , we have pn = Pn + ∆pn
(A9)
vd,n = Vd,n + ∆vd,n
(A10)
pac = pa + pb + pc ∆pac = ∆pa + ∆pb + ∆pc .
∆pdc = ∆pac (A11)
where Pn , Vd,n , and Φn are the steady-state values of pn , vd,n , and φn , respectively. By substituting (A9)–(A11) into (15) and taking the Laplace transformation, (20) can be obtained. D. Derivation of (21) ∗ As the PLL adjusts the phase angle β of vo,n , it results in varying φn . As depicted in Fig. 2(a), the phase relationship between β and φn can be shown to be
vo,n sin θn = vd,n sin φn + vs,n sin(θn − β).
(A12)
0 = sin φn
dvd,n dφn dβ + vd,n cos φn − vs,n cos(θn − β) . dt dt dt (A13)
By using cosine law, we have 2 2 2 vs,n = vd,n + vo,n − 2vo,n vd,n cos(π − φn − θn ).
(A14)
By using (A1) and (A14), we have vo,n = vs,n cos β − vd,n cos(φn + θn ).
(A15)
By differentiating (A15), we have 0 = − cos(φn + θn )
dvd,n dt
dφn dβ − vs sin β . dt dt By using (A13) and (A16), it can be shown that +vd,n sin(φn + θn )
dφn vs,n = cos(β − φn − θn ). dβ vd,n
The design of Cdc value is based on the restoration duration, load characteristics, and voltage rating of the DVR. The amount of energy delivered from the capacitors in tres is the difference between the three-phase total load energy and total supply energy. By using the conservation of energy, we have 1 Cdc 2 2 vdc,ref − vdc,m in 2 2 = [(vo,a − vs,a ) io,a cos θa + (vo,b − vs,b ) io,b cos θb (A23)
By considering the worst case, the three-phase supply voltages are sagged to the minimum voltage, as defined in the specification. Based on (1), in order to avoid generating distorted sinusoidal waveform at the output, when vdc is higher than the peak value of vd∗ . Otherwise, the situation will be similar to overmodulation in standard pulsewidth modulation (PWM) that gives distorted output [34]. vdc,m in is designed to be equal to the peak value of the injecting voltage, i.e., √ (A24) vdc,m in = 2 2 (vo,nor − vs,m in ) .
(A16)
G. Derivation of (27)
(A17)
As the transfer function of T1 (s) in load-dependent, it is necessary to design a controller that can ensure the stability within the operating range. According to Fig. 7, the loop gain TOL (s) of the control loop with power-flow controller is equal to
(A18)
where Vs,n , and B are the steady-state values of vs,n and β, respectively. By substituting (A3) into (A18), (21) can be obtained. E. Derivation of (22) By combining (20) and (A18), it can be shown that ∆pn (s) = −Vs,n io,n cos αn . ∆β(s)
F. Derivation of (26)
By combining (A23) and (A24), (26) can be obtained.
By considering the small-signal variations and taking the Laplace transformation, the transfer function of the phase transformation Tpt,n (s) is Vs,n ∆φn (s) = cos(B − Φn − θn ) Tpt,n (s) = ∆β(s) Vd,n
(A22)
and combining (19) and (A19), (22) can be obtained.
+ (vo,c − vs,c ) io,c cos θc ] tres .
By differentiating (A12), we have
(A21)
By using the conservation of energy, we have
and φn = Φn + ∆φn
(A20)
(A19)
TOL (s) = TC (s)T1 (s)
(A25)
where T1 (s) = TP L L (s)Tinv (s)KT (s) is the transfer function of the inverter and PLL in Fig. 7. KT (s) is the transfer function of the transducer shown in Fig. 7. In order to ensure TOL (s) has the phase margin of 30◦ within the designed operating range, the error amplifier is designed to have one pole at ωp and two zeros at the frequencies of ωz 1 and ωz 2 , respectively. The circuit schematic and TC (s) are shown in Fig. 8. By considering the upper bound of T1 (s), T1U (s), ωcross,m ax is chosen to be the frequency at which |T1U (jωcross,m ax )| ≈ 0 dB and lower than the line frequency. As the phase of TOL (s), φOL , at ωcross,m ax must be larger than −150◦ for achieving
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HO AND CHUNG: IMPLEMENTATION AND PERFORMANCE EVALUATION OF A FAST DYNAMIC CONTROL SCHEME
sufficient phase margin, it is determined by ◦
φOL = φ1 + φC + 360
(A26)
ωz 2 is chosen to be the frequency by φC (jωcross,m ax ) − φC (jωz 2 ) Phase Slope (A27) where the typical value of phase slope in bode plot is 45◦ /decade, and the phase at zero is 135◦ for controller shown in Fig. 8. L By considering the lower bound of T1 (s), LT1 (s), ωcross,m in is chosen to be the frequency at which T1 (jωcross,m in ) = −Ψ dB. By considering the phase characteristic of TC (s), the relationship among ωcross,m in , ωp , and ωz 1 is log ωz 2 = log ωcross,m ax −
ωz 1 < ωcross,m in < ωp
(A28)
ωp is determined by considering that |TC (ωp )| = Ψ dB. Thus, (27) can be obtained. REFERENCES [1] M. Bollen, Understanding Power Quality Problems, Voltage Sags and Interruptions. New York: IEEE Press, 2000. [2] M. Sullivan, T. Vardell, and M. Johnson, “Power interruption costs to industrial and commercial consumers of electricity,” IEEE Trans. Ind. App., vol. 33, no. 6, pp. 1448–1458, Nov. 1997. [3] N. Woodley, L. Morgan, and A. Sundaram, “Experience with an inverterbased dynamic voltage restorer,” IEEE Trans. Power Del., vol. 14, no. 3, pp. 1181–1186, Jul. 1999. [4] R. R. Errabelli, Y. Y. Kolhatkar, and S. P. Das, “Experimental investigation of DVR with sliding mode control,” in Proc. IEEE Power India Conf., Apr. 2006, paper 117. [5] S. Lee, H. Kim, and S. K. Sul, “A novel control method for the compensation voltages in dynamic voltage restorers,” in Proc. IEEE APEC 2004, vol. 1, pp. 614–620. [6] G. Joos, S. Chen, and L. Lopes, “Closed-loop state variable control of dynamic voltage restorers with fast compensation characteristics,” in Proc. IEEE IAS 2004, Oct., vol. 4, pp. 2252–2258. [7] P. Ruilin and Z. Yuegen, “Sliding mode control strategy of dynamic voltage restorer,” in Proc. ICIECA 2005, Nov./Dec., p. 3. [8] T. Jauch, A. Kara, M. Rahmani, and D. Westermann, “Power quality ensured by dynamic voltage correction,” ABB Rev., vol. 4, 1998, pp. 25–36. [9] C. S. Chang, S. W. Yang, and Y. S. Ho, “Simulation and analysis of series voltage restorer (SVR) for voltage sag relief,” in Proc. IEEE PES Winter Meeting, Jan, 2000, vol. 4, pp. 2476–2481. [10] C. Meyer, R. W. De Doncker, Y. W. Li, and F. Blaabjerg, “Optimized control strategy for a medium-voltage DVR—Theoretical investigations and experimental results,” IEEE Trans. Power Electron., vol. 23, no. 6, pp. 2746–2754, Nov. 2008. [11] S. S. Choi, B. H. Li, and D. M. Vilathgamuwa, “Dynamic voltage regulation with minimum energy injection,” IEEE Trans. Power Syst., vol. 15, no. 1, pp. 51–57, Feb. 2000. [12] D. M. Vilathgamuwa, A. A. D. R. Perera, and S. S. Choi, “Voltage sag compensation with energy optimized dynamic voltage restorer,” IEEE Trans. Power Del., vol. 18, no. 3, pp. 928–936, Jul. 2003. [13] K. Piatek, “A new approach of DVR control with minimized energy injection,” in Proc. PEMC2006, Aug., pp. 1490–1495. [14] D. M. Vilathgamuwa, H. M. Wijekoon, and S. S. Choi, “Interline dynamic voltage restorer: A novel and economical approach for multiline power quality compensation,” IEEE Trans. Ind. Appl., vol. 40, no. 6, pp. 1678– 1685, Nov./Dec. 2004. [15] D. Vilathgamuwa, H. M. Wijekoon, and S. S. Choi, “A novel technique to compensate voltage sags in multiline distribution system—The interline dynamic voltage restorer,” IEEE Trans. Ind. Electron., vol. 53, no. 5, pp. 1603–1611, Oct. 2006. [16] R. J. Nelson and D. G. Ramey, “Dynamic power and voltage regulator for an ac transmission line,” U.S. Patent 5 610 501, Mar. 1997. [17] A. van Zyl, R. Spee, A. Faveluke, and S. Bhowmik, “Voltage sag ridethrough for adjustable-speed drives with active rectifiers,” IEEE Trans. Ind. Appl., vol. 34, no. 6, pp. 1270–1277, Nov./Dec. 1998.
1987
[18] A. Ghosh, A. K. Jindal, and A. Joshi, “Design of a capacitor-supported dynamic voltage restorer (DVR) for unbalanced and distorted loads,” IEEE Trans. Power Del., vol. 19, no. 1, pp. 405–413, Jan. 2004. [19] C. Ho, H. Chung, and K. Au, “Design and implementation of a fast dynamic control scheme for capacitor-supported dynamic voltage restorers,” IEEE Trans. Power Electron., vol. 23, no. 1, pp. 237–251, Jan. 2008. [20] K. Leung and H. Chung, “Derivation of a second-order switching surface in the boundary control of buck converters,” IEEE Power Electron. Lett., vol. 2, no. 2, pp. 63–67, Jun. 2004. [21] K. Leung and H. Chung, “A comparative study of the boundary control of buck converters using first- and second-order switching surfaces,” IEEE Trans. Power Electron., vol. 22, no. 4, pp. 1196–1209, Jul. 2007. [22] D. O. Koval and M. B. Hughes, “Canadian national power quality survey: Frequency of industrial and commercial voltage sags,” IEEE Trans. Ind. Appl., vol. 33, no. 3, pp. 622–627, May/Jun. 1997. [23] A. El Mofty and K. Youssef, “Industrial power quality problems,” in Proc. IEE Conf. Electr. Distrib., Part 1: Contrib., Jun. 2001, vol. 2, pp. 139–139. [24] E. W. Gunther and H. Mebta, “A survey of distribution system power quality—Preliminary results,” IEEE Trans. Power Del., vol. 10, no. 1, pp. 322–329, Jan. 1995. [25] M. H. J. Bollen, “Voltage sags: Effects, mitigation and prediction,” Power Eng. J., vol. 10, no. 3, pp. 129–135, Jun. 1996. [26] B. M. Weedy and B. J. Cory, Electric Power System, 4th ed. New York: Wiley, 1998. [27] H. M. Berlin, Design of Phase-Locked Loop Circuits with Experiments, 1st ed. Indianapolis, IN: Sams, 1985. [28] H. Kim and S. K. Sul, “Compensation voltage control in dynamic voltage restorers by use of feed forward and state feedback scheme,” IEEE Trans. Power Electron., vol. 20, no. 5, pp. 1169–1176, Jan. 2005. [29] B. Wang, G. Venkataramanan, and M. Illindala, “Operation and control of a dynamic voltage restorer using transformer coupled H-bridge converters,” IEEE Trans. Power Electron., vol. 21, no. 4, pp. 1053–1061, Jun. 2006. [30] H. Awad, J. Svensson, and M Bollen, “Mitigation of unbalanced voltage dips using static series compensator,” IEEE Trans. Power Electron., vol. 19, no. 3, pp. 837–846, May 2004. [31] Y. Chiu, K. Leung, and H. Chung, “High-order switching surface in boundary control of inverters,” IEEE Trans. Power Electron., vol. 22, no. 5, pp. 1753–1765, Sep. 2007. [32] M. Ordonez, J. E. Quaicoe, and M. T. Iqbal, “Advanced boundary control of inverters using the natural switching surface: Normalized geometrical derivation,” IEEE Trans. Power Electron., vol. 23, no. 6, pp. 2915–2930, Nov. 2008. [33] S. Chen, Y. M. Lai, S. C. Tan, and C. K. Tse, “Boundary control with ripple-derived switching surface for DC–AC inverters,” IEEE Trans. Power Electron., vol. 24, no. 12, pp. 2873–2885, Dec. 2009. [34] M. Rashid, Power Electronics, Circuits, Devices, and Applications, 3rd ed. Englewood Cliffs, NJ: Prentice-Hall, 2004. [35] C. Ho, K. Au, and H. Chung, “Digital implementation of boundary control with second-order switching surface,” in Proc. IEEE PESC2007, Jun., pp. 1658–1664.
Carl Ngai-Man Ho (M’07) received the B.Eng. and M.Eng. double degrees and the Ph.D. degree in electronic engineering from the City University of Hong Kong, Kowloon, Hong Kong, in 2002 and 2007, respectively. From 2002 to 2003, he was a Research Assistant at the City University of Hong Kong. From 2003 to 2005, he was an Engineer at e.Energy Technology Ltd., Hong Kong. Since May 2007, he has been a Scientist at ABB Corporate Research, Ltd., BadenD¨attwil, Switzerland. His Ph.D. work focused on the development of dynamic voltage regulation and restoration technology. His current research interests include power electronics, power quality, modeling and control of power converters, and characterization of wide bandgap (WBG) power semiconductor devices and their applications. He holds two U.K. and one U.S. patents in the area of lighting applications. Dr. Ho was a Reviewer for the IEEE TRANSACTIONS ON POWER ELECTRONICS, the IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS, the IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS, and several conferences.
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1988
IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 25, NO. 8, AUGUST 2010
Henry Shu-Hung Chung (M’95–SM’03) received the B.Eng. degree in electrical engineering and the Ph.D. degree from Hong Kong Polytechnic University, Kowloon, Hong Kong, in 1991 and 1994, respectively. Since 1995, he has been at the City University of Hong Kong (CityU), where he is currently a Professor in the Department of Electronic Engineering and Chief Technical Officer of e.Energy Technology Ltd.—an associated company of CityU. His research interests include time- and frequency-domain analysis of power electronic circuits, switched-capacitor-based converters, random-switching techniques, control methods, digital audio amplifiers, softswitching converters, and electronic ballast design. He has authored or coauthored six research book chapters and more than 260 technical papers, including 120 refereed journal papers in his research areas. He holds 12 patents. Dr. Chung was IEEE Student Branch Counselor and was a Track Chair of the technical committee on power electronics circuits and power systems of IEEE Circuits and Systems Society in 1997–1998. He was an Associate Editor and the Guest Editor of the IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS–PART I: FUNDAMENTAL THEORY AND APPLICATIONS in 1999–2003. He is currently an Associate Editor of the IEEE TRANSACTIONS ON POWER ELECTRONICS. He was the recipient of the Grand Applied Research Excellence Award in 2001 from the CityU.
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