Implementation of a Mobile Phone Module with ... - IEEE Xplore

Implementation of a Mobile Phone Module with Redistributed Chip Packaging

Lakshmi N. Ramanathan, Beth Keser, Craig Amrine, Trung Duong, , Scott Hayes, George Leal, , Marc Mangrum, Douglas Mitchell, and, Robert Wenzel Freescale Semiconductor Inc., 2100 East Elliot Road, Tempe, AZ 85284 Abstract The Redistributed Chip Packaging is an embedded chip technology that eliminates the need for wirebonds and flip chip bumps. This technology enables smaller packages at a lower cost, while providing improved mechanical, electrical and thermal performance. The process involves producing panels placing the chip active face down along with an embedded ground plane (EGP) and screen printing encapsulant to embed the die. Subsequently alternate layers of dielectric and Cu metallization are built up and the packages are sawn into individual units. The use of wafer fabrication tools enables finer lines and spaces in the build-up layers. This paper will discuss process conditions during the panelization and the integration of the base function of an i.275 GSM/EDGE mobile phone into a single module measuring a maximum of 1 square inch. The design of the EGP and the role of simulations to achieve a robust, reliable package will also be discussed. The outputs included moisture sensitivity level (MSL) 3 testing, air-to-air thermal cycling (40C/125C) and unbiased highly accelerated stress testing (HAST). Testing of RCP packages will also be discussed. Introduction Increasing demand for smaller consumer products, like cell phones and MP3 players, is driving the need for enhanced integration of the underlying die operating these mobile devices. Functionalities like audio, video, voice, internet connectivity, email, and cameras are requiring the use and integration of a variety of analog, digital, RF, MEMS and power management die as well as associated passives. Furthermore, with each generation of these consumer products the expectation is that the cost will also be lower. To date Moore’s Law has delivered faster and smaller chips with increased functionality by shrinking the size of the transistor. However, at the system level traditional packaging methods such as flip chip and wirebonding have proven to be incapable of realizing the full speed, and capabilities of the underlying die. This is especially true at higher RF frequencies when parasitics become significant. Furthermore, integration of disparate die technologies, like Si, SiGe, GaAs, MEMS and accompanying passives, is forcing the industry to investigate alternative packaging technologies. In the last several years a variety of embedded chip packaging approaches have been shown to be capable of integrating a variety of die and passives in a more compact form factor at a lower cost [1-3]. These can be broadly classified as chips first, chips middle and chips last technologies [4], or in the case of Freescale, Freescale’s Redistributed Chip Package (RCP) [3]. In 2007 the basic process flow and advantages of RCP were published [3]. Compared to traditional PBGA and

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CBGA packages, RCP was shown to deliver greater integration density in a thinner package and smaller footprint with superior electrical as well as thermal performance at a lower cost. The other advantages of RCP included, lower mechanical stresses enabling packaging of brittle low-k die, being environmentally green, and extension to modules. The basic RCP process flow includes panelization followed by build-up of alternate layers of dielectric and Cu metallization. Panelization involves placing one or more active die face down, along with an embedded ground plane (EGP), onto a double sided sticky tape mounted on a carrier. Epoxy is then deposited and cured to produce the panel with the embedded die. The cured panel is ready for build-up process that involves spin coating a photoimageable dielectric layer, followed by patterning to generate the vias. Subsequently Cu metallization is deposited using a semiadditive method by electroplating Cu in a patterned photoresist spun onto a sputtered TiW/Cu layer. Enabling a module solution to fit in a one inch square size required existing Freescale GSM/EDGE baseband and power management devices being marketed in 13x13 280 I/O and 10x10mm 185 I/O BGA packages respectively to be shrunk to a smaller size. Packaging these devices in an RCP single chip package resulted in a 9x9mm 258 I/O 0.5mm pitch package for the baseband device and an 8x7mm 186 I/O 0.5mm pitch package for the power management device. Each package was routed from the die to the BGA pads using two metal routing layers and two via layers. The vias in RCP are landed directly on top of die redistribution layer (RDL) pads to create interconnections from die pads to metal 1 (M1) layer routing. This interconnect is repeated for second via layer which are landed on top of M1 capture pads to create connections to the M2 or BGA pads. In this paper the experiments done to investigate the effects of EGP thickness will be discussed. Outputs included moisture sensitivity level (MSL) 3 testing, air-to-air thermal cycling (-40C/125C) and unbiased highly accelerated stress testing (HAST). Simulations were done to predict reliability and to validate the results from reliability testing. Electrical testing of RCP packages will also be discussed. Process Flow The panelization process begins by mounting tape onto a substrate. The embedded ground plane (EGP) is then placed on the adhesive and the die and passives are picked and placed into openings in the EGP. Epoxy is then deposited and cured locking the EGP, die and passives into position. Front end fab tools are then used to apply the build up layers of dielectric and Cu metallization. The number of layers is dictated by factors such as number of I/O, die and package size, BGA ball size, ball pitch and count, number of ground, signal and power layers, and routing design rules.

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package type being developed. Any advanced package must meet industry standard levels of reliability. Designing RCP to first meet and then exceed those requirements is a critical consideration. The reliability standards have evolved to well known set of criteria for burn in, humidity exposure, thermal cycling and mechanical shock. New generation of packages respond with previously known and often newer failure modes that are unique to the package family. Thermal cycling analysis (-40 to 125 C) was done for predicting solder joint fatigue life for packages ranging from 9x9mm to 17x17mm RCP packages. The first time to failure predictions were well above the customer requirement.

Figure 1. RCP process flow (a) Place die and embedded ground onto tape (b) Release substrate (c) build up (d) place solder balls (e) singlulate into packages After the last metal layer a coating of dielectric is patterned to form the final solder mask layer. BGA balls are then placed or printed to form the joint to the next level of interconnection. The panel is then sawn into individual packages for shipment. The schematic for the flow is shown in Figure 1 [3]. The system design of the 25x25mm fully integrated radio module was based on a combination of existing Freescale i.250 and i.275 platform schematics optimized to take advantage of the tighter spatial integration offered by RCP technology. Throughout the system parts count and body sizes such as decoupling capacitors were reduced as compared to board-level designs due to the tight integration, for reasons such as closer proximity of power management to load circuits. Careful consideration of system partitioning allowed integration into RCP of both the new RCP-based subcomponents such as baseband processor and power management, as well as existing RF section modules and embedded bare die memory devices, and additional components such as crystals, SAW filter, chip resistors, capacitors and inductors. The routing design layout was performed for the module, consisting of a 2-sided RCP Memory Base having 4 routing (metal) layers on the top side and a single layer on the bottom side, and special RCP panel through-vias for top-to-bottom connectivity. Connections between the memory devices and the baseband processor were kept very short and confined since the embedded memory die were essentially face-to-face with, and directly underneath, the baseband processor its new 9x9mm miniaturized RCP package. Routing of RF lines were thus more easily partitioned from memory interface resulting in less potential for digital noise coupling into the RF signals. Designing an advanced package is not without challenges. Some of these challenges are unique to the new

Radio in Package The process to provide through-vias within the RCP module base involves providing means to drill through-vias, fill the vias with an electrically conductive material, and planarizing the filled vias to allow subsequent dielectric and metal build-up layers. Materials and processes for through-via development were adopted from the printed-circuit board (PCB) industry. Like PCB or substrate based products, RCP panels consist of an epoxy-based substrate with conductive through-vias that need to be co-planar with the top and bottom surfaces. RCP panels contain embedded die, however, and cannot be subject to the aggressive grinding/planarization processes that PCB panels undergo. As a result, special precautions were taken to protect the die during the via formation process. Through-vias were drilled using a laser. Most laser via drilling systems offer a choice of drilling patterns including percussion, trepanning, or spiral patterns. The preferred pattern for via-drilling largely depends on the panel material, via diameter, and power of the beam. Vias were then filled with a conductive via-fill epoxy. Several conductive via-fill epoxies are available that were originally developed for the printed-circuit board industry. After curing, the excess via-fill material is planarized to the level of the panel surface. The ground RCP panel is now sufficiently planar to allow subsequent addition of dielectric and metal build-up layers on both sides of the panel. To simplify assembly of the entire Radio in Package module, existing high density (HD) substrate packages of the RF Transceiver and PA modules were used. The baseband and power management devices were assembled in RCP packages. All RCP and HD substrate packages stacked on the Memory Base had NiAu pad finishes. The passive devices had normal tin termination for ease of assembly. The memory panel was stencil printed with 95.5Sn3.8Ag0.7Cu (SAC387) solder paste. The 4 packages, capacitors, crystals, and SAW filters were picked onto the panel using a standard pick and place tool according to height. The panel was then reflowed using a standard SAC387 solder paste reflow profile reaching a maximum of 250ºC. After reflow, the panel was then sawn using a package saw to separate the individual Radio in Package modules. Figures 2 shows the assembled module.

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Experiments A study was done to evaluate the influence of dielectric properties and EGP thickness on package reliability. Three different dielectrics (A,B and C) from evaluated from two suppliers. Dielectrics B and C were from the same supplier and had the same material base, with dielectric C modified for manufacturability. The properties of the final film from B and C dielectrics are the same. Two different EGP thicknesses (0.125mm and 0.25 mm) were evaluated. Packages with each of the dielectrics and EGP thicknesses were tested for reliability. The test vehicle package used for this evaluation was 9x9mm in size, had 2 metal routing layers, and 258 I/Os in a depopulated array at 0.5mm pitch LGA format. A daisy chain or stitched die 5.8x5.5mm in size was used in these packages to support continuity type testing. The reliability stresses included JEDEC moisture sensitivity level (MSL) 3 testing followed by air-to-air thermal cycling at -40C/125C and unbiased highly accelerated stress testing (HAST) at 130C/85RH/33.3PSIG conditions. A production level Automated Test Equipment (ATE) tester and associated handler was used to perform the continuity testing at timezero and after each stress readpoint to determine the pass/failing condition of each unit. Maintaining a flat panel is critical for manufacturability. However, RCP package contains organic and inorganic components with disparate coefficients of thermal expansion (CTE), which contribute to intrinsic stresses during panelization and build-up. The CTE of the Cu EGP at 17 ppm/C is significantly different from that of the dielectrics as well as the 3ppm/C for the Si die. Furthermore, the encapsulant used resulted in significant thermomechanical stresses, especially during temperature cycling. In addition to the disparate CTE values, upon cure the epoxy and dielectric layers shrink, which also contributes additional stresses during panelization and build-up. Since front end litho and metallization fab tool (designed for handling rigid Si wafers were adapted for RCP build-up processes), it is critical that the factors contributing to panel flatness be characterized. Flat panels are essential for robust handling well as for enabling solder print, and saw. Mechanical simulation was done to quantify the effect of EGP thickness on warpage. Ansys software was used to generate a finite-element based model with Shell 181 elements used to model the geometry .A quarter symmetry model was used to model the panel.

Effect of EGP (No heat spreader) 0 -20

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Figure 2: Topside view of assembled Module

Results and Discussion The success of the RCP process flow is dependent on the panels being flat after panelization, thru build-up, and upon final release of carrier. Factors that contribute to flatness include the die size, the thickness of the die, the ratio of die to package areas, number of build-up area, the amount of metal in each layer, as well as the thickness and design of the EGP. Apart from the thickness of the EGP all other factors are specific to the die being packaged. Thus, a general understanding and prediction of EGP thickness on warpage is critical for enabling large volume manufacturing. The results from mechanical simulations to investigate the effect of EGP thickness on the warpage of two 4-layer RCP packages is displayed in Figure 3. The negative warpage corresponds to a convex surface. One package is a 25mmx25mm package with 360 IO, while the other is a 29mmx29mm package with 783 IO. From Figure 2 it is seen that for all EGP thicknesses simulated the 29x29mm package has a slightly higher warpage than the 27mmx27mm package. This difference is postulated to be due to the larger package size. From Figure 3 it is also seen that for both packages eliminating the EGP increased warpage by about 60μ. However, for a given package over the range modeled the warpage is not significantly affected by the EGP thickness. Only one treatment combination using dielectric B, with 0.125mm EGP displayed one failure after 750 cycles of airto-air temperature cycles.

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Figure 3. Variation of warpage with thickness of EGP. As discussed earlier the packages with each treatment combination, namely, dielectric and EGP thickness, were subjected JEDEC MSL 3 preconditioning. The preconditioned parts were then passed 1000 air-to-air cycles between -40C/125C and to 144 hours of unbiased HAST. Conclusions The implementation of a radio in package using RCP technology was discussed. The importance of warpage during processing and the important factors contributing to it were discussed. Experiment was done to evaluate the effects of EGP thickness on the reliability of the package. The experimental results were complemented with simulations to

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understand the role of stresses on warpage. It was shown that package size plays a critical role on package warpage. Acknowledgments Thanks to Krishna Tunga for warpage modeling results. References 1. Manessis, S Dionysios, Yen, Shiu-Fang Yen, Ostmann, Andreas, Aschenbrenner, Rolf, and Reichl, Herbert, “Technical Understanding of Resin-Coated-Copper (RCC) Lamination Processes for Realization of Reliable Chip Embedding Technologies,” Proc 57th Electronic Components and Technology Conf, Reno, NV, May. 2007, pp. 278-285. 2. Embedded Chip Build-Up Using Fine Line Interconnect Fillion, Ray, Woychik, Charles, Zhang, Tan and Bitting, Don, “Embedded Chip Build-Up Using Fine Line Interconnect,” Proc 57th Electronic Components and Technology Conf, Reno, NV, May. 2007, pp. 49-53. 3. Keser, Beth, Amrine,Craig, Duong, Trung, Fay, Owen, Hayes, Scott, Leal, George, Lytle, William, Doug Mitchell, Doug, Wenzel, Robert, “The Redistributed Chip Package: A Breakthrough for Advanced Packaging,” Proc 57th Electronic Components and Technology Conf, Reno, NV, May. 2007, pp. 286-291. 4. Lee, Baik-Woo. Sundaram, Venky, Wiedenman, Boyd, Yoon, Chong K., Kripesh, Vaidyanathan, Iyer Mahadevan and Tummala Rao, R., “Chip-last Embedded Active for System-On-Package (SOP),” Proc 57th Electronic Components and Technology Conf, Reno, NV, May. 2007, pp. 286-291..

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