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Implementation of an algorithm to design resample filters to simultaneous and multirate data acquisition systems Ana Letícia G. Gonçalves1, Osamu Saotome1 1
Divisão de Engenharia Eletrônica – Instituto Tecnológico de Aeronáutica (ITA) – São José dos Campos, SP – Brasil
[email protected],
[email protected]
Abstract. To maintain the real time characteristics of a feedback system it is a premise that actuation is synchronous with acquisition signal. In digital systems, intermediate processing with various digital filters can interfere in this synchronism. This work presents a multirate digital filter design approach with constant group delay. Thus, synchronous condition in real time mode can be maintained. The presented method uses an iterative process to design the filters applied in simultaneous multirate data acquisition systems, such as in sensor network applications. When these applications requires joint data channels analysis to extract consistent information, if the time reference is modified, the system causality would be damaged generating incorrect results.
1. Introduction The present work is resultant of a data acquisition board development that integrates an aeronautical sensor network. This specific area tends to maximize the available bandwidth to transmit the acquired and processed input signals, making possible the implementation of a low cost network device with low transmission delay. To reach this specification, it is necessary to configure the sampling rate acquisition channels by reducing the number of samples to be transmitted. It influences the delay introduced in each channel due to the resample process executed by specific digital filters. A data acquisition system that operates with several sampling frequencies can or not be simultaneous. If an application uses some data channels with an analysis purpose, it is required the maximum synchronism between them under the risk of the analysis results become incorrect, such as in aerodynamic variable parameters identification applications. Finally, the design of such systems requires special care into the DSP blocks to avoid the real time characteristics loss. The lack of references that presents a method to work with multiple channels was the stimulus for the algorithm implementation to supply the resample process blocks arrangement in function of the constant lower delay introduced by the digital filters. The main purpose is to help DSP programmers given them a way to speed up the resample filters design time. At first, an initial concept about multirate systems followed by the algorithm description and application are presented. For the closure, some comments and conclusion complete this work-in-progress paper.
2. Multirate Systems A multirate system can be characterized by signals with different sampling rates where the aim is leaving all these signals to the same final sampling rate. In the decimation
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system schematized in Figure 1, the input signals xk(n) have different rates and they are resampled to the same rate Fs/2. In the approach shown in Figure 1a, the decimation process uses non-integer indexes (Mk) – an impracticable implementation, while in Figure 1b, it happens only with integer values.
(a) Resample with non-integer indexes
(b) Resample with integer indexes
Figure 1: Multirate acquisition system digital blocks
As shown in Figure 1a M3 is not an integer. This case requests interpolation followed by decimation to get the sampling rate Fs/2. However, the implementation of the structure presented are not ideal because the decimation indexes Mk are different, therefore the decimation filter orders are not equal resulting in different delay for each channel. Thus, the acquisition synchronism due to simultaneous sampling hardware is lost. An interesting approach described by [Crochiere and Rabiner 1983] is the decimation process application in progressive blocks to reach raised indexes: at channels 2 and 3, the decimation blocks could be split in 2 blocks with decimation indexes of 2, instead of a unique decimation block of 4. This alternative is known as decimation in multiple stages and must be considered into the system design to prevent the use of filters with abrupt transition band. Some methods as suggested in [Crochiere and Rabiner 1983] could be used to design the solution for the case presented but there is not a method that gives the distribution or number of stages to be followed to preserve the synchronism among channels.
3. Implementation of the algorithm The implemented algorithm supplies the solution to convert 4 acquisition channels sampling rate into a common rate, showing the number and the order of each processing stage – interpolation and / or decimation. This solution is obtained in function of the lower delay generated by the digital filters. The algorithm has 3 steps: a) Determination of the common multiple minor between the original and the final sampling rates; b) Determination of the decimation stages arrangement possibilities with the filter order calculation to get lower delay; c) Among available arrangements, select the one that presents the lower delay. At first, it is determined the common multiple minor between all sampling rates (inputs, outputs and intermediates). This is required to calculate the frequency for which
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the input channels will be interpolated to generate the initial frequency decimation step, named here of intermediate frequency. After interpolation, the iterative process is started to design the decimation blocks. In this step, the reduction sampling rate indexes of each channel (Mk) is determined, followed by the calculation of minimum filter orders (Nk) to reach the frequency response specified. The decimation stages distribution decision will be taken by the algorithm: it calculates all the possible distributions, limited in 4 stages with decimation index decrease sequence as recommended by [Ifeachor and Jervis 2002]. For each possibility, the filter delays are calculated and the solution arrangement with lower delay is indicated. The algorithm returns the number and order of interpolation and decimation stages as a final response. The filter applied by this algorithm is an Equirriple FIR – the most indicate for this purpose – with pass band ripple of 0.001, rejection band ripple of 0.01, end of normalized pass band of 0.2 and start of normalized rejection band of 0.5.
4. Simulation results of the algorithm application To illustrate the algorithm application it will be presented here 2 examples. The first one consists of a simple distribution: 4 acquisition channels with 15 sps, 20 sps, 30 sps and 60 sps will be decimated to a rate of 15 sps. It is important to empathize the maximum input signal frequencies in all channels cannot exceed 4 Hz. In the second example, the input sampling rates are not multiple between themselves and require a great number of iterations to determine the decimation structure: 4 acquisition channels with 10 sps, 30 sps, 40 sps and 100 sps will be resampled to 10 sps. The results of first example generated by the algorithm indicate as a solution the interpolation of 4, 3, 2 and 1 (I1=4, I2=3, I3=2, I4=1) for channels 1, 2, 3 and 4, respectively, and decimation in a single stage of 4 through a 35th order FIR filter (M=4, N=35). The output signal delay is 0.291667s for all channels keeping them synchronized in real time if they are acquired in synchronism. The choice was carried out between 2 possible solutions: a single stage of 4 or 2 stages with individual decimation indexes of 2. The second example result indicates as a better solution the interpolation for 60, 20, 15 and 6 for channels 1, 2, 3 and 4, respectively, and the decimation in a single stage for 60 through a FIR filter with order of 513 (M=60, N=513). The output signal delay is 0.4275s keeping all the channels synchronized in real time if they were already synchronized by hardware. The solution was chosen between 10 options. This example shows the diversity of options available to design a resample digital processing system and the simple use of the algorithm to speed it up. The results supplied by the algorithm to both examples can be seen in Table 1, where the bold options indicate the lower delay result.
5. Comments The references about decimation filters design recommend that decimation process must be done in a progressive way to avoid high filter orders that influence straightly in the accumulated amplitude error introduced by the digital processing. However, this indication does not result in a filter set that could keep the acquired channels
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synchronism. Thus, it is not applied to all acquisition data systems that must maintain the channels with zero group delay as illustrated by the examples: the solution with lower delay is not the one that presents the filter set with lower orders. Table 1. Example applications algorithm results
Example 1 CH1: 15sps / 15sps CH2: 20sps / 15sps CH3: 30sps / 15sps CH4: 60sps / 15sps
Intermediate Sampling Rate
Interpolate Index for each channel I1 / I2 / I3 / I4
60 sps
4 / 3 / 2/ 1
Decimation Arrangement Options Decimation Index M / Filter Order / Delay
4 / 35 / 0.291667 s
60 / 513 / 0.4275s
Example 2 CH1: 10sps / 10sps CH2: 30sps / 10sps CH3: 40sps / 10sps CH4: 100sps / 10sps
600 sps
60 / 20 / 15 / 6
20 / 559 / 0.4658333s 3 / 29 / 0.483333s 12 / 559 / 0.465833s 5 / 47 / 0.47s 15 / 585 / 0.4875s 2 / 39 / 0.4875s 2 / 19 / 0.475s 5 / 585 / 0.4875s 4 / 117 / 0.4875s 3 / 29 / 0.483333s
2 / 37 / 0.308333s 2 / 19 / 0.31667s 30 / 559 / 0.465833s 2 / 19 / 0.475s 15 / 559 / 0.465833s 4 / 37 / 0.4625s 10 / 559 / 0.465833s 6 / 57 / 0.475s 10 / 585 / 0.4875s 3 / 59 / 0.491667s 2 / 19 / 0.475s 5 / 603 / 0.5025s 3 / 121 / 0.504167s 2 / 41 / 0.5125s 2 / 21 / 0.525s
6. Conclusion During the development of data acquisition system for aeronautical sensor, it was necessary to use the algorithm implemented to design the resample blocks arrangement to achieve the distribution with lower delay, since the application of multiple stages is an iterative process. Appling this algorithm, the decimation embedded code implementation time was reduced significantly, making this task agile and flexible from the point of view of channel delays. In spite of the algorithm uses only 4 acquisition channels as inputs, it was implemented by a set of MATLAB instructions that can be converted easily to another platform, as C language functions, turning possible to embed it into a software that makes the complete resample system design: from the interpolation and decimation structure up to the coefficients filters determination independently from the number of channels of the system.
References Crochiere, R. E. and Rabiner L. R. (1983) “Multirate Digital Signal Processing”, Prentice-Hall, New Jersey, USA. Ifeachor, E.C. and Jervis B. W. (2002) “Digital signal processing: a practical approach”, Person Education Limited, England, 2nd Edition. Proakis, J. G. and Manolakis, D. G. (1996) “Digital Signal Processing: Principles, Algorithms, and Applications, Prentice-Hall, New Jersey, USA, 3rd Edition. “Remez FIR Filter Design - Signal Processing Blockset”, MATLAB 7.1 Help, The MathWorks Inc., USA. Vaidyanathan, P. P. (1993) “Multirate systems and filter banks”, Prentice-Hall, New Jersey, USA.
