Implementation of Gigahertz 1-bit Full Adder on SiGe FPGA K. Zhou1*, Channakeshav1*, J.R. Guo1, C. You1, J. Mayega1, B.S. Goda2 M. Chu1, Y.U. Yim1, J-W. Kim1, P.F. Curran1, R.P. Kraft1, and J.F. McDonald1 1
Rensselaer Polytechnic Institute, Troy, NY 12180 2 US Military Academy, West Point, NY 10996 E-Mail:
[email protected],
[email protected]
Abstract Gigahertz Field Programmable Logic Arrays (FPGAs) have always been a dream for circuit design engineers. CMOS FPGAs have greatly limited the range of applications because of its low speed, i.e. 10-220 MHz. With the introduction of Silicon Germanium (SiGe) Heterojunction Bipolar Transistors (HBTs), designers have been able to build circuits capable of operating in the gigahertz range. SiGe HBTs are high-speed devices with a cutoff frequency (fT) in excess of 100 GHz [1]. This paper will elaborate on the details of the implementation of a 1-bit full adder (FA) in the new SiGe FPGA. The 1-bit FA can be realized with only 3 Configurable Logic Blocks (CLBs). The propagation delays of the redesigned logic cell and a 1-bit FA are 85 ps and 214 ps respectively. IBM's 7HP design kit has been used for designing the circuits and Cadence 4.4.5 is used for simulation and layout.
I. INTRODUCTION Our Silicon Germanium (SiGe) Field Programmable Gate Array (FPGA) is bitwise compatible with the Xilinx 6200. Some detailed descriptions have already been published in [2][3][4][5]. Figure 1 shows the top-level architecture of a SiGe FPGA. Current Mode Logic (CML) is selected for the design of the logic cells because of its immunity to switching noise [6]. Figure 2 shows a CML buffer and its operation with waveforms.
Figure 1: Schematics of a logic cell – CLB & Routing Multiplexers
II. THE ADVANTAGE OF SIGE HBT SiGe HBTs are similar to normal Si bipolar transistors except that they have graded germanium in the base region. Figure 3 shows the band diagram of a typical SiGe HBT. Due to the graded base, there is a drift field in the base region which speeds up the carriers. This reduction in the base transit time allows SiGe HBTs to have better performance over Si BJTs. Some important effects are the increase in the current gain (β) and cutoff frequency (fT).
III. DESIGN DESCRIPTION Figure 2: A CML buffer with input and output waveforms
Figure 4 shows the Configurable Logic Block (CLB) structure in Xilinx 6200 [7]. There are 2 paths in the structure. They are, ______________________________________________________________________
*Both
these authors have contributed equally to this paper.
Zhou, Channakeshav
1. The sequential path that passes through the input multiplexers and then through the flip-flop. 2. The combinational path that involves only the input multiplexers.
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It requires two XOR gates and one 2:1 multiplexer. Both the XOR gate and the 2:1 MUX require one CLB. So a single 1bit FA can be implemented in 3 CLBs instead. Figure 7 shows the configuration of the CLB to operate as an XOR gate with a propagation delay of 49 ps.
Figure 3: Band diagram of SiGe HBT [8]
Figure 5: Redesigned CLB structure
Figure 4: Original Xilinx 6200 structure [7]
The Chip Select (CS) multiplexer selects the path based on the programming. The select bits for all the multiplexers come from the configuration memory. A simple implementation would be to design each component separately and then join them [2]. The power dissipation and the propagation delay of the original CLB were 10.8 mW and 100 ps respectively. Figure 5 shows a simplified version of the redesigned structure. The objective is to achieve the same logic using fewer trees in order to reduce the power and propagation delay. This structure can be implemented in just 5 trees (3logic with 2-emitter followers), whereas the original structure required 11 trees. This 55% reduction in the number of trees leads to at least a 55% reduction in power dissipation. Figure 6 shows the schematics of all the three blocks. Since the number of trees in both the combinational and sequential paths has been reduced, the propagation delay is also reduced. The power dissipation and propagation delay of the redesigned CLB are 5.04 mW and 46-50 ps respectively.
IV. IMPLEMENTATION OF THE 1-BIT FULL ADDER This paper mainly considers the implementation of a 1-bit Full Adder (FA) on a SiGe FPGA. A straightforward implementation of the 1-bit FA would use 10 CLBs [9]. The logic is as follows [10]: Sum = A ⊕ B ⊕ Cin (1) Cout = A ⋅ B + (A ⊕ B) ⋅Cin (2) This logic can be realized in a better way in terms of power and propagation delay if the logic is written in another form. X= A⊕B (3) (4) Sum = X ⊕ Cin Cout = X ⋅ B + X ⋅ Cin (5) Zhou, Channakeshav
Figure 6: Schematics of all three blocks in the new structure
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Figure 8 shows the configuration for a 2:1 MUX and its propagation delay is 50 ps. Figure 9 shows the configuration of the CLBs for the implementation of a FA with waveforms. Each block is a logic cell with its maximum propagation delay to be approximately 85 ps. The delay for the 1-bit full adder is 214 ps.
(a) Adder architecture implemented in the SiGe FPGA
Figure 7: CLB configuration of an XOR gate with waveforms
(b) The waveform of the 1-bit full adder Figure 9: CLB interconnection for a full adder with waveforms
Zhou, FigureChannakeshav 8: CLB configuration of a 2:1 MUX with waveforms
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V. CONCLUSION High speed FPGAs find applications in many research and military fields such as Digital Signal Processing, where digital filters need fast multipliers, adders, flip-flop, etc. [11]. They can also be used in applications that involve high-speed broadband networks [12], high-speed inline processing, rapid prototyping of microprocessors and in the area of image recognition.
REFERENCES [1] “BiCMOS 7HP Design Manual,” IBM Inc., April 2002. [2] B. Goda, J.F. McDonald, S. Carlough, T. Krawczyk, R. Kraft, “SiGe HBT BiCMOS for fast reconfigurable computing,” IEE Proceedings of Computers and Digital Techniques, vol. 147, no. 3, pp. 189-194, May 2000. [3] B. Goda, J.F. McDonald, R. Kraft, S. Carlough, T. Krawczyk, “Gigahertz Reconfigurable Computing using SiGe HBT BiCMOS FPGA,” 11th International Conference on Field Programmable Logic and Applications, pp. 59-69, May 2000. [4] Channakeshav, K. Zhou, R. Kraft, J.F. McDonald, “Gigahertz FPGAs with New Power Saving Techniques and Decoding Logic,” 4th NASA/DoD Workshop on Evovable Hardware, pp. 60-62, 2002. [5] K. Zhou, Channakeshav et al., “Gigahertz FPGAs with New Architectural Ideas,” 45th IEEE Midwest Symposium on Circuits and Systems, to appear soon, Aug. 2002. [6] H. Greub, J.F. McDonald, T. Yamaguchi, “High Performance Standard Cell Library and Modeling Technique for Differential Advanced Bipolar Current Tree Logic,” IEEE Journal of Solid-State Circuits, vol. 26, no. 5, pp. 749-762, May 1991. [7] “Xilinx Series 6000 User Guide,” Xilinx Inc., San Jose, CA., 1997. [8] J. Cressler, “SiGe HBT Technology: A New Contender for Si-Based RF and Microwave Circuit Applications,” IEEE Transactions on Microwave Theory and Techniques, vol. 46, no. 5, pp. 572-589, May 1998. [9] B.S. Goda, “SiGe HBT BiCMOS Field Programmable Gate Arrays for Fast Reconfigurable Computing,” Ph.D. dissertation, Rensselaer Polytechnic Institute, NY 12180. [10] M. Smith: Application Specific integrated circuits, Addison Wesley, Massachusetts, 1997. [11] B. Herzen, “Signal Processing at 250 MHz Using HighPerformance FPGAs”, IEEE Transactions on VLSI Systems, vol. 6, no. 2, pp. 238-246, June 1998. [12] J. McHenry, P. Dowd, et al., “An FPGA-Based Coprocessor for ATM firewalls”, IEEE Symposium on FPGAs for Custom Computing Machines, pp. 30-39, April 1997.
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