Int. J. of Recent Trends in Engineering & Technology, Issue. 1, Vol. 11, July 2014
Implementation of MRAM-Based Full Adder for Sleep Mode Applications A. Bhattacharya, and A. Islam Electronics and Communication Engineering Birla Institute of Technology, Mesra Ranchi, Jharkhand, India, Pin-835215
[email protected],
[email protected]
Abstract— Any memory can be used to build a logic circuit if the area overhead is tolerable. This paper presents implementation of logic circuit using memory bitcell, which is realized with only one NMOS and an MTJ (magnetic tunneling junction) for reducing area overhead. Since full adder is the most basic building block of arithmetic circuit of any processor, a one bit full adder is implemented using MRAM bitcell which is nonvolatile. As it stores data even if the power supply goes off, it can save power consumption drastically. Index Terms— Full adder, MTJ, CMOS, Spintronics.
I. INTRODUCTION Technology scaling results in reduction of the lateral and vertical dimensions of transistors. The supply voltage (VDD) is scaled down to reduce power dissipation and also to maintain device reliability (avoid oxide breakdown). The threshold voltage (Vt) is proportionally scaled down in order to maintain the performance. However, narrow oxide thickness and lowVt result in significant rise in gate leakage and sub-threshold leakage currents, respectively. Therefore, leakage power is now a significant contributor to the total chip power dissipation. Hence, both dynamic and leakage power reductions are equally essential for the nanoscale design. Therefore, innovative circuit level techniques must be investigated to reduce both of these power components to extend the battery life for portable applications. Numbers of techniques namely transistor sizing, dynamic voltage scaling, transistor stacking, dynamic body biasing, power gating have emerged to reduce power dissipation. Although standby modes are most often quoted for processors, they make more sense for peripheral devices like disks, wired and wireless interfaces, and input/output devices because all of them operate in a bursty fashion. For instance, a cellphone is in standby most of the time, and even when active, data is only transmitted periodically. If the wake-up delay and area overhead are tolerable then the power gating technique with the use of sleep transistor is the most effective to reduce power dissipation. However, the circuit-block to be put into sleep mode must be able to wake-up with its previous state. This implies that the circuit-block needs nonvolatile elements in its structure. This paper proposes a technique to realize 1-bit full adder using nonvolatile memory since full adder is basic building block in various circuits, especially in circuits which are used for performing arithmetic operations such as compressors, comparators, parity checkers, and so on [1], [2]. Researchers are looking for new devices or new methods for next generation computers, such as spintronics computing, single electron transistor (SET), molecular electronic RTD (resonant tunneling diode), and nano-CMOS [3]–[12], [13], [14]. Spintronics device based computing circuits are becoming very popular. Recently Magnetic tunnel junction
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(MTJ) based logic circuits have been studied due to its non-volatility, infinite endurance, high access speed, and easy integration with CMOS process. MTJ consists of three thin films (two ferromagnetic and one barrier layers) [15], [16]. Its resistance is dependent on the relative spin orientations of the two ferromagnetic layers. In standard applications, the magnetization orientation of one layer is fixed, it is called fixed layer while the other ferromagnetic layer can take two opposite orientations: either parallel (low resistance) or anti-parallel (high resistance) to the magnetization orientation of fixed layer (See Figure 1) [17]. One of the applications of MTJ is nonvolatile memory circuit like STT-MRAM circuit. The conventional memory like SRAM, DRAM and flash memories are not meeting the requirement of high speed and memory hungry processors. SRAM has excellent read stability and write-ability but it has a larger cell size due to its 6-transistor or 8-transistor structures. This larger cell size limits the amount of memory that can be integrated within the μP/SoC/NoC. The eDRAM with 1-transistor or 3-transistor structures is good alternative to SRAM because of its small cell size. Periodic refreshing needed by eDRAM makes it undesirable for portable electronics with limited battery life. Both SRAM and eDRAM need external power to retain stored data. Conversely, flash memories are non-volatile in nature. They do not require external power to store data. Moreover, they have high integration density and simple architecture. However, high voltage and slow write operations with limited read/write endurance go beyond its advantages [18]. STT-MRAM is answer to all previous memory technology because it has all desired memory attributes like nonvolatility, unlimited endurance, low-power, high-speed and density [18] and low leakage current. Moreover, the STT-MTJ can be fabricated on top of CMOS devices toreduce the area cost.
Figure 1. MTJ structure.
Therefore, STT-MRAM, which consists of only one NMOSFET and one MTJ, is used to realize 1-bit full adder that can wake-up with its previous state. Extensive simulations were performed in HSPICE in 16-nm predictive technology model to verify the results. The rest of the paper is organized as follows. Section II presents the operating principle of MTJ and MRAM bitcell. Logic circuit implementation using MRAM bitcell is discussed in section III. Section IV presents our proposed full adder circuit and its simulation result. Finally concluding remarks are provided in section V. II. OPERATING PRINCIPLE OF MTJ AND STT-MRAM BITCELL STT-MRAM bitcell consists of 1 NMOSFET, 1 MTJ, 1 Bitline (BL), 1 Source Line (SL) and 1 word line (WL) (See Figure 2). The spintronics device is connected at the bottom of the transistor with its pinned (fixed) layer connected to the source line (SL). The free layer is connected to the source of NMOSFET. Word line (WL) and bitline (BL) are connected to the gate and drain of transistor respectively. High resistance of MTJ is considered as a ‘1‘ stored in MRAM bitcell. Similarly, low resistance of MTJ is considered as a ‘0‘ stored in MRAM bitcell. In MTJ, magnetization flipping occurs when the switching current density exceeds a threshold value (the threshold value of switching current density is known as the ‗critical current density‘, JC). A. Storing Logic ‘1’ and Logic’0’ in MTJ MTJ works as a storing element, where logic ‗0‘ or ‗1‘ can be stored. For storing logic ‗1‘, a bias voltage (0.7 V) is applied to BL and SL is grounded (see Fig. 2). When WL is activated, current flows form BL to SL. If this current exceeds the switching threshold current in P to AP direction (ICPtoAP) then the resistance of the MTJ becomes high and this high resistance is encoded as logic ‗1‘. For storing logic ‗0‘, the voltage (0.7 V) polarity of BL is changed and SL remains grounded. When WL is activated current flows in opposite direction. If this current exceeds the switching threshold current in AP to P direction (ICAPtoP) then the resistance of the MTJ becomes low and this low resistance is encoded as logic ‗0‘. The principle of storing data in MTJ is shown in Table I. 397
Figure. 2. MRAM bitcell. TABLE-I. PRINCIPLE OF STORING DATA IN MTJ Condition of BL SL WL storing data From ‗1‘ to ‗0‘ -0.7 V 0V 0.7 V From ‗0‘ to ‗1‘ 0.7 V 0V 0.7 V
B. Model parameter of MTJ The physical and electrical behavior of MTJ is modeled in Verilog-A which describes all the static, dynamic and stochastic behavior of MTJ. The parameters of MTJ are tabulated below in Table II. TMR(0) Rp Rap ICPtoAP ICAPtoP Area
TABLE-II. MTJ MODEL PARAMETERS TMR with 0 voltage bias 150% Parallel state resistance 1.84 kΩ Antiparallel state resistance 4.5 kΩ (at 0 bias voltage ) 3.55 kΩ (at 0.7 bias voltage) Switching Current from 27.2 uA parallel to antiparallel state Switching Current from -19.2 uA antiparallel to parallel state Area of MTJ surface 40 nm × 40 nm × π /4
. III. LOGIC CIRCUIT IMPLEMENTATION USING MEMORY BITCELL This section presents implementation of any logic circuit with a memory block. Here a memory bitcell works as a storage element where data ‗1‘ or ‗0‘ can be stored. A 3-input logic circuit is shown in Figure 3. All the eight possible outputs are stored in memory bitcell. The detailed circuit diagram is shown in Figure 4. It can be observed from Figure 4 that it has one decoder, one memory block and one multiplexer. The decoder output depends on the input condition which is used to select one memory bitcell. Here MRAM bitcell is used as a storage element as discussed in section II. The output of decoder is connected with word line of MRAM bitcell. In the MRAM bitcells the outputs for each particular input condition is stored. It is fed to the input of multiplexer where 3 input lines works as select lines of multiplexer. For example, ―000‖ input patter of decoder will cause D0 to go high, which will switch on the NMOSFET related to bitcell M1, resulting in transferring the content of M1 to the output of 8:1 MUX. The detailed function is shown in Table III.
TABLE-III. DETAILED FUNCTION OF LOGIC CIRCUIT IMPLEMENTATION USING MEMORY
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Inputs A 0 0 0 0 1 1 1 1
B 0 0 1 1 0 0 1 1
C 0 1 0 1 0 1 0 1
Decoder Output
Memory bitcell
MUX output
D0 D1 D2 D3 D4 D5 D6 D7
M1 M2 M3 M4 M5 M6 M7 M8
O1 O2 O3 O4 O5 O6 O7 O8
Figure. 3. Block Diagram of Logic Circuit implementation using memory block.
Figure. 4. Detailed circuit diagram of logic circuit implementation using memory block.
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Figure. 5.Proposed Full Adder using MRAM
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IV. PROPOSED FULL ADDER AND ITS SIMULATION RESULT A. Proposed Full adder This section describes proposed 1-bit full adder (See Figure 5) circuit using MRAM bitcell. It can be seen from Figure 5 that MRAM bitcell stores the output of each input condition for sum and carry. The inputs are fed to the 3:8 decoder. The decoder output activates the MRAM bitcell where the output for each input condition has been already stored. From multiplexer final sum and carry is obtained. As MRAM is used as a memory bitcell so this full adder has the potential features like nonvolatility. It can save great power consumption as it stores the data even if the power supply goes off. If supply rails are disconnected from conventional memory such as latches and registers, all data stored in them are ultimately lost. But MRAM holds its data even if the supply rails are disconnected from it. The entire logic or memory blocks are not active at the same time in a large chip and hence power consumption can be saved greatly if the inactive module can be disconnected from supply rails. As MRAM retains its data so it can be done easily for our design. This is possible, if perfect ON–OFF switches are available. One option is to use sleep transistors switches as shown in Figure 6.
Figure. 6.Power Grating technique with sleep transistor.
Figure. 7.Input and output with loading in full adder block.
B. Simulation Setup As a 1 bit full adder is rarely used as a standalone circuit and is mostly used to form parallel adders by cascading, the inputs and outputs of the proposed full adder circuit are loaded with two inverters to simulate a real environment (see Figure 7). All the simulations are carried out using 16-nm predictive technology model of CMOS and MTJ model in HSPICE. The channel length (L), channel doping concentration (NDEP), oxide thickness (tox), and threshold voltage (Vt) are assumed to have independent Gaussian distributions with 3σ variation of 10% [19]. All parameters are estimated under the above simulation setup. C. Simulation Result Simulation results are shown in Table IV and Figure 8. Propagation delay (tp), power consumption (PWR), power-delay product (PDP) and energy-delay product (EDP) are reported in Table IV as they are important
performance metric of a full adder. The waveform shown in Figure 8 exhibits the functionality of our proposed full adder cell. TABLE-IV TP, POWER, PDP AND EDP CALCULATION OF PROPOSED FULL ADDER Full Adder tp(Sec) Power (W) PDP (J) EDP (J.S) MTJ based 9.4651E-10 6.4551E-05 6.1098E-14 5.7830E-23 full adder
Figure. 8. Output waveform of proposed full adder.
V. CONCLUSION This paper proposes a technique to realize any logic circuit using memory bitcell. The proposed technique is verified by implementing a 1-bit full adder cell. MTJ based MRAM bitcell is used as memory element for this study to reduce the area overhead. The technique is found to be effective to realize nonvolatile full adder cell. Therefore, the proposed full adder cell is a potential candidate for sleep mode applications. REFERENCES [1] H. T. Bui, Y. Wang, and Y. Jiang, ―Design and analysis of low-power 10-transistor full adders using XOR–XNOR gates,‖ IEEE Trans. Circuits Syst. II, Analog Digit. Signal Process., vol. 49, no. 1, pp. 25–30, Jan. 2002. [2] S. Goel, A. Kumar, M. A. Bayoumi, ―Design of Robust, Energy-Efficient Full Adders for Deep-Submicrometer Design Using Hybrid-CMOS Logic Style,‖ IEEE Trans. Very Large Scale Integr. (VLSI) Syst. vol. 14, no. 12 pp. 1309-1321, Jan. 2003. [3] R.P.Cowburn andM.E.Welland, ―Room temperature magnetic quantum cellular automata,‖ Science, vol. 287, pp. 1466–1468, Feb. 2000. [4] S. A. Wolf, D. D. Awschalom, R. A. Buhrman, J. M. Daughton, S. von Molnár, M. L. Roukes, A. Y. Chtchelkanova, and D. M. Treger, ―Spintronics: a spin-based electronics vision for the future,‖ Science, vol. 294, pp. 1488–1495, Nov. 2001. [5] G. A. Prinz, ―Magnetoelectronics,‖ Science, vol. 282, pp. 1660–1663, Nov. 1998. A. Ney, C. Pampuch, R. Koch, and K. H. Ploog, ―Programmable computing with a single magnetoresistive element,‖ Nature, vol. 425, pp. 485– 487, Oct. 2003. [6] A. Ney, C. Pampuch, R. Koch, and K. H. Ploog, ―Programmable computing with a single magnetoresistive element,‖ Nature, vol. 425, pp. 485–487, Oct. 2003. [7] W. C. Black, B. Das, M. M. Hassoun, and K. F. E. Lee, ―Nonvolatile Programmable Logic Devices,‖ U.S. Patent no. 6 542 000, Apr. 1, 2003. [8] H. Ahmed and K. Nakazato, ―Single-electron devices,‖ Microelectron.Eng, vol. 32, pp. 297–315, Sep. 1996. [9] I. Amlani, A. O. Orlov, G. Toth, G. H. Bernstein, C. S. Lent, and G. L.Snider, ―Digital logic gate using quantumdot cellular automata,‖ Science,vol. 284, pp. 289–291, Apr. 1999. [10] C. G. Smith, ―Nanotechnology: computation without current,‖ Science, vol. 284, p. 274, Apr 1999. [11] L. Chang, Y. K. Choi, D. Ha, P. Ranade, S. Xiong, J. Bokor, C. Hu, andb T. J. King, ―Extremely scaled silicon nano-CMOS devices,‖ Proc. IEEE, vol. 91, no. 11, pp. 1860–1873, Nov. 2003.
402
[12] F. Leonard and J. Tersoff, ―Multiple functionality in nanotube transistors,‖ Phys. Rev. Lett., vol. 88, no. 25, Jun. 2002. [13] K. K. Likharev, ―Single-electron devices and their applications,‖ Proc. IEEE, vol. 87, no. 4, pp. 606–632, Apr. 1999. [14] Y. K. Choi, D. Ha, T. J. King, and C. Hu, ―Nanoscale ultrathin body PMOSFETs with raised selective germanium source/drain,‖ IEEE Electron Device Lett., vol. 22, no. 9, pp. 447–448, Sep. 2001. [15] F. Leonard and J. Tersoff, ―Multiple functionality in nanotube transistors,‖ Phys. Rev. Lett., vol. 88, no. 25, Jun. 2002. [16] M. Jullière, ―Tunneling between ferromagnetic films,‖ Phys. Lett., vol. 54A, pp. 225–226, 1975. [17] Yi Gang ,W. Zhao , Klein, J.-O. , Chappert, C. , Mazoyer, P., ―A High-Reliability, Low-Power Magnetic Full Adder,‖ vol. 47, no. 11, pp. 4611 – 4616, Nov. 2011. [18] J. Li, P. Ndai, A. Goel, S. Salahuddin, and K. Roy, ―Design Paradigm for Robust Spin-Torque Transfer Magnetic RAM (STT MRAM) From Circuit/Architecture Perspective,‖ IEEE Trans. Very Large Scale Integr. (VLSI) Syst., vol. 18, no. 12, pp. 1710 – 1723, Dec. 2010. [19] R. Vaddi, S. dasgupta, and R. P. Agarwal, ―Device and circuit co-design robustness studies in the subthreshold logic for ultralow-power applications for 32 nm CMOS,‖ IEEE Trans. Electron Devices, vol. 57, no. 3, pp. 654–664, Mar. 2010.
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