Implementation of Low-cost Failure Detection System ...

Implementation of Low-cost Failure Detection System Using Resistance Spectroscopy Ashish Batra, Lee Fang, and J.H Constable Department of Electrical Engineering State University of New York at Binghamton Binghamton, NY 13902 Abstract The results are presented for the design and test of an instrument that makes high-resolution resistance measurements on the electrical interconnections of a package. This failure detection system has been achieved by using a low cost data acquisition card, custom designed circuit cards, and LabVIEW applications. The instrument has been used to measure interconnection resistance change measurements with resolution higher than 1 mΩ on daisy-chained flip-chip chip scale packages during thermal cycling. The recorded data is then analyzed to obtain the resistance change amplitude at the harmonics of thermal cycling frequency. Introduction Since the evolution of the electronics industry, it has set its goal in attaining higher speed, higher density, higher performance, and smaller size of its packages. But in attaining its goal, the industry has to address numerous reliability issues. These reliability issues grow more stringent as the electronics industry makes its presence felt in new and different environments. The environment for the electronic package can be quite severe, depending upon the applications e.g. military, and automotive applications. An electronic package typically includes the semiconductor chip mounted on a substrate via solder bumps or wire bonds. This substrate is encapsulated to seal the device from outside environment, and provides an electrical and mechanical connection from the printed circuit board to the chip. In this study, we design an instrument that makes high-resolution resistance measurement using a technique called “Resistance Spectroscopy” [1]. This instrument was used in our study to predict the reliability of a flip-chip chip scale packages (FCCSP), while they undergo accelerated thermal cycling. Theoretical Background Reliability of interconnects has always been a concern in the packaging industry. Integrity of interconnects has generally been detected through the change in its resistance. The common accelerated stressing techniques used for testing the reliability of interconnects can be broadly categorized into two types 1) Thermal cycling and 2) Isothermal mechanical cycling. In thermal cycling, electrical resistance is monitored and is used to detect failure. Whereas in isothermal mechanical cycling electrical and mechanical detection techniques have been used. The different failure criteria of the above two stressing techniques makes it difficult to compare results between them [2]. Between the two techniques, accelerated thermal cycling is generally considered a benchmark test for product reliability.

None of the various detection techniques used with accelerated stress testing have been completely reliable in accurately predicting the failure of an interconnect. In the following, we will discuss some of the reasons that lead to this conclusion. Lets say that the daisy chain resistance of a typical package is about 4 ohms. Then the change in resistance due to grain coursing can shown to be on the order of several micro-ohms, and that due to mechanical failure would be on the order of a few milli-ohms provided the two surfaces form a slight mechanical contact [1]. These values make you wonder why there is a need to design a new instrument when ohmmeters with a resolution of 1 micro-ohm are already available in the market. The answer is logical, the higher the temperature coefficient of resistance (TCR) of a material, the less accurately the resistance can be measured. Interconnects, are typically made of metals with a TCR value of about 0.4% per ºC. Hence for a daisy chained package with a resistance of 4 ohms, a temperature change of about 0.5C would produce an 8 mΩ resistance change. This magnitude of temperature variation is very common in either an environment chamber or in a laboratory. Hence it can be concluded from the above argument that the techniques, which do not compensate for the effects of temperature change, cannot be considered as reliable detection techniques. Even the change in the probe location (incase parts are probed) as well as contact resistance change can change the resistance reading on the order of 0.01 ohms. Failures are normally detected by using an event detector [3], which are typically set to monitor for an instantaneous resistance increase of more than 300Ω. The problems faced while using an ohmmeter are mostly overcome by using this instrument because the magnitude of the threshold change used is much greater than that caused by temperature variation or external noise. This magnitude of resistance change can be attributed to a momentary mechanical separation of the fractured surface during thermal cycling. As a fractured joint is heated or cooled, the two surfaces slide over one another. The fast response time of the event detector catches the resistance increase as it slides. But at the same time if the fractured interconnect maintains a strong spring contact, the sliding contact resistance might be lower than the threshold value and the failure could go undetected by the event detector for many more cycles. This is one of the drawbacks of using an event detector. An event detector can be set to catch events as short as 0.1 micro-second, but such short response time makes the system more susceptible to external noise. The event detector threshold can be as small asP EXWZLWKWKLVVHQVLWLYLW\WKHHYHQWGHWHFWRUZRXOG not be able to identify between the resistance increase due to

temperature variation or fatigue failure resulting in false events. In all the detection techniques discussed so far, actual mechanical or electrical failure is detected. But “Resistance Spectroscopy” (RS) is a measuring technique that has the potential to detect failure prior to actual mechanical failure. In other words, it can take less than 100 cycles to predict failure and identifies the incipient failure mechanism [4]. The RS technique can monitor the small resistance change associated with the atomic motion associated with fatigue. The RS technique uses a Wheatstone bridge to nullify the effects of temperature variation. Hence the change in resistance of the specimen, as monitored by the RS technique, directly relates to the stress induced during thermal cycling and any metallurgical changes in the interconnect. A unique feature introduced with RS is to measure the resistance while the sample is being cyclically stressed and then calculating the change in the resistance at the applied stress frequency and its harmonics. Areas of the electrical circuit that are not subjected to cyclic stress do not contribute to the detected signal, and hence random resistance variations are eliminated. Both AC and DC Wheatstone bridges have been used in past experiments. The noise floor in DC measurements was usually less than 1 micro-ohm [5]. Although AC bridges required both resistive and reactive balancing, they have a noise floor of a few nano-ohms, and are capable of monitoring both reactance and resistance changes. The periodic response resulting from fatigue cycling has been shown to be well suited for Fourier decomposition. The independent variable in this case is the temperature, this is linearly scaled so that the range of the variable was from –1 to +1, and then the parametric angle θ is taken as θ = arcsine (µ). Linear regression was then used to fit the experimental data to a sine/cosine Fourier series of the form: ∞

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Physical significance can typically be assigned to the various Fourier coefficients. The a0 data obtained from the Fourier analysis of the cyclic data was found to increase nearly linearly with thermal cycling for BGA packages. Time to failure can then be predicted by dividing the rate of increase into the threshold resistance for failure. All previous RS studies mentioned up-till now had one thing in common; the experimental set-up for monitoring the resistance change used a lock-in amplifier. This makes the entire set-up expensive and complicated. In this study, one of the main tasks was to design a new instrument that would aid in monitoring the resistance changes of the sample without using a lock-in amplifier. To understand the instrument design, the principles of a dual-phase lock-in amplifier are needed. Typically a lock-in amplifier is used to detect and measure very small AC signals i.e. even signals as low as nano-volts. The feature that makes it all the more attractive is that very accurate measurements can be made even if the signal is shrouded by noise sources many thousands of times larger. A lock-in amplifier is typically composed of three sections. First, notch filters at harmonics of 60Hz eliminate

power line frequencies, and a low pass filter to eliminate the alias frequency of the heterodyne amplifier. These filters cut down frequencies other than the reference frequency to prevent saturations in the later sections. Secondly, a phase sensitive detection system is used to single out the component of the signal at a specific reference frequency and phase. And lastly, a low pass filter that sets the overall bandwidth of the instrument The set-up used in the present study, makes use of a data acquisition (DAQ) card. The counter timer on the DAQ card and the custom designed circuitry detects the sinusoidal response from the experiment. By sampling this acquired signal by a trigger signal generated from the same source, we can calculate the “in-phase” and “out-of phase” components of the AC signal. This technique will be explained in the section on instrumentation design. Design Philosophy Currently there are three philosophies for failure detection systems represented by the Event Detector, LATEST Tester, and the RS Technique, which are all uniquely different and consequently will yield different results. To achieve the detection of events, which last only microseconds, the Event Detector has a sensor amplifier for each specimen that must have a high bandwidth. The high bandwidth allows all the noise to pass in this band, and limits the ultimate sensitivity. As mentioned earlier, the detection of events where the fracture surface slides eliminates the problem of resistance change with temperature, but increases the cost and limits its sensitivity to only these major events. The LATEST Tester monitors for a component of the resistance which has a non-linear I-V behavior. This occurs most often when there is a region of the circuit which has a constricted cross section. With sufficient current and the correct choice of frequency, this section will have an instantaneous temperature at the frequency of the applied power, which is at twice the frequency of the applied AC bias. The instantaneous temperature causes a corresponding change in resistance. Thus for a constant current bias, circuits with a restricted cross section will produce a resistance change at the second harmonic of the applied AC signal, which is detected as a failure. Because there are few mechanisms that generate a second harmonic signal, the sensitivity to this frequency can be made quite high. This device could in principle be switched between specimens yielding a lower cost tester than the Event Detector. The RS detector uses two essential components. The first is a Wheatstone bridge that is used to balance out the signal from the initial resistance, initial reactance, and temperature change. This balancing out of the initial signal during thermal cycling allows the instrument to have its full dynamic range devoted to the small resistance changes resulting from strain, fatigue, and crack initiation. The second component of the RS technique is Fourier series processing of the resistance change to obtain the components that change synchronously with the stress cycling frequency. For mechanical cycling these components can be associated with the crack area, strain, and energy dissipation per cycle, but for thermal cycling there is as yet no clear interpretation.

Instrumentation Design The heart of the RS Detector is the Wheatstone bridge, which is the circuit used to detect the change in the resistance of the daisy chained specimens, and is shown schematically in Figure 1. The reference arm of the bridge has a 200 ohm 25 W resistor in series with a temperature compensation network, R, located in the environmental chamber. See reference [1] for details of the design of the compensating network.

Figure 1. Schematic of the 16 channel-Wheatstone bridge circuit. Each of the 16 channels consists of a 200 ohm 25 W power resistor and a resistance associated with the daisychained specimen, which was about 0.27ohm for our test. The amplifier drives each of the 16-channels as well as the reference arm with a 20V 1.95kHz signal. Each channel is selected by a relay, and connects the channel to the A input of the differential pre-amplifier. The reference arm is connected to the B input of the differential pre-amplifier. Connecting the relay switch to one of the channels forms the Wheatstone bridge circuit as shown in Figure 2.

Figure 2. Wheatstone bridge circuit for one channel. The 200Ω 25W resistor in the reference arm and in each arm of the 16-channels provides a constant current to the temperature compensating network, and specimens. Most of the 20V AC drive is dropped across the 200Ω power resistors. The high wattage and low temperature coefficient of resistance or these resistors allow them to withstand the drive voltage with an insignificant resistance change. By adjusting the 10k resistors and 50pF capacitors across the 200Ω 25W power resistors, the bridge is balanced when the voltage across inputs A and B are equal. Often extra fixed resistors

and capacitors are also added in parallel. Fixed resistors and capacitors are added across the reference arm to allow balancing the specimen with the largest reactance. After this channel is balanced, the remaining channels are balanced. Once the bridges are balanced, the thermal cycling of the specimens is commenced. The temperature-compensating resistor, which is nothing but a non-inductive wound length of copper wire, is placed in close proximity to the specimens during the thermal cycling. Because the change in resistance of both the specimen and temperature compensating resistance are equal, they cancel each other out in the differential amplifier. The TCR value for the Wheatstone bridge output is typically reduced by a factor of about 100 by adding the compensation resistor, and then the only observed change in resistance is due to the 1% unbalanced signal, and the resistance change with strain and fatigue. The unbalance in the bridge produced by the strain and fatigue results in a voltage change in the A-input of the differential amplifier, which results a signal out of the amplifier resulting from the strain and fatigue. After recording the bridge output voltage using the data acquisition card, we plot the resistance and reactance change of the specimens with respect to time. The data acquisition card is also used to detect the 1.95kHz AC signal from the bridge so the amplitude of the AC can be recorded. The card also performs timing, and generates the 1.95kHz signal that is the input to the power amplifier. Figure 3 shows the overall bock diagram for the measuring system.

Figure 3 shows a block diagram of the entire measuring technique.

The data acquisition card (DAQ card) used in this work was a National Instruments PCI 1200 DAQ card. The first function preformed by the DAQ card was to generate the signal that after amplification was used to drive the bridges. A LabVIEW application was used to communicate with the 82C53 counter timers in group B on the DAQ card in order to generate the signal. The three counter timers in this group, B0, B1, and B2, plus an external circuit were used to generate two 1.956kHz square waves with an adjustable phase difference between them. Counter B0 is connected to the 2 MHz internal clock of the DAQ card, and it is setup in mode-3 so that it divides the input frequency by two resulting in the B0 output being a 1MHz square wave. The output is applied as a clock input to counters B1 and B2. Counter B1 is setup in mode-2, rate generator mode, with a count value of 128. The output of counter B1 is a negative pulse train at 7.81kHz (1MHz/128=7.81kHz). (Note that logically counters B0 and B1 could be combined but the internal wiring of the DAQ card prevented this.) The pulse train is applied to an inverter producing a positive pulse train, which is used as the clock input to flip-flops 1 and 2 on the external circuit card shown in schematically Fig. 4. These flip-flops are connected as synchronous counters, which divide the clock frequency by two and four to produce a square wave outputs at 3.9kHz and 1.98kHz.

Figure 4. External circuit to produce phase shifted 1.95kHz outputs. The phase shift circuitry shown in Fig. 4 uses the B2 counter to produce a delay in the triggering edge of 3.9kHz signal. The B2 counter is setup in mode-1, programmable one shot, and the trigger for this counter is connected to the 3.9kHz square wave that is produced by flip-flop 1. The counter B2 is programmed from 0 to 256 counts and uses the 7.81 kHz clock pulses to produce the delay after the trigger. This 3.9kHz pulse train with variable phase and duty cycle is inverted using a NAND gate and the output is applied to the clock of flip-flop 3 to produce a 1.95kHz square wave with shifted phase. Flip-flop 3 is synchronized with flip-flop 2 by wiring its J3 and K3 inputs to the Q2 and Q 2 outputs of flipflop 2 respectively. The phase change of the 1.95kHz square wave at the output of flip-flop 3 with respect to the 1.95kHz square wave at flip-flop 2 is determined by the programmable count value that is passed on to the counter-2 through the LabVIEW program, and can be varied from 0° to 180°. The

X-OR gate at the output of flip-flop 3 can switch the phase by another 180° allowing a full 360° of phase shift. The square wave signal from flip-flop 3 is sent through a limiter to stabilize the amplitude and then a band-pass filter to produce a 1.956kHz 0.8V sinusoidal signal. Lastly the signal is fed to the power amplifier to produce the 1.956kHz 20Vsine wave drive for the bridge circuit. The Wheatstone bridge measuring circuit consists of the 16 selectable bridges described above. A five-bit word is written to the digital output port of the PCI-1200 DAQ card by a LabVIEW application, which is the input to a 5 to 32-bit decoder whose output was used to energize each relay driver circuit. The output of the Wheatstone bridge is fed to the PCI 1200 DAQ card via a low-noise pre-amplifier with a bandpass around 1.95kHz, and a gain between 125 and 250. The analog to digital converter of the DAQ card is triggered by an external sequential circuit, and synchronously demodulates the 1.95kHz signal from the bridge. The synchronous sampling is illustrated in Fig. 5

Figure 5. Representation of synchronous sampling used to detect the 1.95kHz bridge signal. The analog to digital (ADC) converter of the DAQ card samples the bridge output signal four times during each cycle of the 1.95kHz signal. These four points allow the extraction of the in-phase amplitude of the AC signal as well as the outof-phase signal. Consider the two cases show in Fig. 5. In the first case (top trace), let the larger waveform (red) be the current through the specimen. Let the smaller waveform be the bridge output voltage. In this case, it is seen that the output voltage is in phase with the current. The triggering on the DAQ card is set up to trigger the ADC at points S1, S2, S3, and S4 on the current waveform. (The position of these points can be adjusted with the phase control.) Looking at this figure it is apparent that the amplitude of the voltage signal is equal to (S2–S4)/2.

The lower trace in Fig. 5 shows the case of an out-ofphase signal. Again, the current through the specimen is taken as the larger (red) curve, and the smaller (green) curve as the bridge output voltage. It is seen that the out-of-phase bridge voltage is drawn as leading the current signal by 90°. With the ADC set to sample the same four points as used in the upper case, the amplitude of the out-of phase amplitude, (S3-S1)/2. Also notice that the in-phase expression, (S2–S4)/2, yields zero in the lower case just as the out-of phase amplitude expression (S3-S1)/2 gave zero for the in-phase case. The two-channel output (in-phase and out-of-phase) of the ADC produces outputs where the in-phase channel is proportional to the resistance change and the out-of-phase channel is proportional to the reactance change. To produce the four ADC trigger signals at S1, S2, S3, and S4, a sequential circuit is used. The four inputs to the sequential circuit are the 1.95kHz and 3.9kHz non-phase shifted signals as well as the two request bits, P1 and P2 from the LabVIEW program identifying which of the four-phases, S1, S2, S3, and S4, are being stored. Figure 6 shows the circuit that was used to generate the ADC trigger signal.

Experimental Results Specimen Resistance and TCR. As mentioned in the previous sections, the specimen used for the thermal cycling portion of this study was a 64-I/O flip-chip chip scale package (FC CSP) with 12 mil pads. The daisy chain resistance of this package was about 0.27 Ohm. A 4-point resistance measurement was carried out on eleven flip-chip chip scale assemblies. The average resistance calculated was 0.276Ω, and the standard deviation was 0.021Ω. To calculate the temperature coefficient of resistance for the specimen, the fractional change in resistance (R-Ro)/Ro is plotted versus temperature. Figure 7 shows our experimental results. The temperature setting was changed in 20°C increments and the resistance measured during the ramp period and the dwell time giving the departure and catching up regions of the curve seen in the figure. The slope of this graph is the temperature coefficient of resistance (TCR) of the specimen, and was found to be 0.0037 while the temperature coefficient of resistance of copper is 0.00385 at 20°C. Because the TCR of the specimen was so close to copper, the temperature-compensating resistor was just a 0.28Ω length of #36 magnetic wire wound non-inductively on a ceramic core. 

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Figure 6. Sequential circuit for generating an external trigger for analog to digital conversion The LabVIEW program for the system runs in three different modes: balancing mode, measurement mode, and interrupt mode. In the balancing mode, the reference phase is initially set to zero. The channels are then stepped through individually and the output monitored using the rapid screen update. During this step we must adjust the balancing screws so that the magnitudes of the in-phase and out-of phase signals are close to zero. Now, we adjust the phase so that the “In-phase channel” is in phase with the resistance change, which is achieved by varying the resistance to produce a resistance unbalance of the bridge and then adjusting the phase to make the out-of-phase signal zero and in-phase signal maximum. After achieving this condition, the bridge is said to be electronically balanced for phase and ready for taking measurements. In the measurement mode, we obtain the in-phase and out-of phase signals for each of the 16-channels, while the samples are being thermally cycled. In our study, the chamber was programmed to run a cycle of 0° to 100°C with 20-minute ramps and 10 minute soaks (dwells), which results in a one-hour cycle. The interrupt mode is used to stop writing a file when the interrupt is set. The interrupt can be set when some specimen needs to be removed or the experiment stopped without losing data.





 











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Figure 7. Plot between fractional-change in resistance with temperature for the FC CSP sample. Instrument Calibration and Resolution. The bridge circuit was balanced for 8-channels. To verify the calibration we attached a 2.79 Ω resistor in parallel with the 0.35 Ω specimen plus lead wire resistance in one of the channels. The reading acquired by the DAQ card was recorded before and after attaching the resistor. The change in resistance calculated for the parallel combination of these two resistors is 0.039 Ω. The DAQ card output converted to resistance change using the known current and observed output was 0.034 Ω change. The resolution of the instrument depends upon the preamplifier gain, and the analog to digital converter (ADC) on the data acquisition card. The ADC measures the small voltage drop across the bridge circuitry after amplification in the range of 125 to 250. The DAQ card has a 12-bit ADC with full-scale values of +5/-5V. In other words, the smallest signal that this card could read is 2.44mV (10V/212).







 





    



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Data analysis Figure 8 is a plot of the resistance and reactance change observed in sample-1 during its 1st cycle. As is observed from the figure, the resistance variation during the cycle is much greater (about a factor of 10) than the reactance variation in the specimen during the same cycle.





 

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Figure 8. Plot of resistance and reactance variations observed in sample-1 during its 1st cycle. The data collected for all the samples behaved similarly. Replacing the curve by a line drawn through the center of the points yields the average slope of the data with temperature. The average slope of the curve for resistance change versus temperature suggests that our bridge was over compensated for temperature, because the average slope of the resistance curve has the form, R=R0 (1+α∆T), where α is the TCR and can be seen to have a negative value in Fig. 8. In the above expression, R is the measure resistance, R0 is the resistance at room temperature, and ∆T is the temperature change from room temperature. Now we mathematically adjusted our plots by adding a resistance of the form (b+aT) to this loop to make it symmetrical around the x-axis. The curve that results from adding a resistance of the form (b+aT) could have been obtained by adjusting the balancing resistance and the temperature compensation. Because the resistance and temperature balance was not achieved experimentally, this mathematical approach was used to eliminate the large variation with temperature. An adjusted resistance curve is shown in Fig. 8, which was obtained by adding (0.02+0.00081 T) to the original resistance curve in this

figure. Whereas the linear variation with temperature has been taken out, the remaining resistance change during the thermal cycle is much greater than expected from our previous work. To understand the results of the resistance change versus temperature, an experiment was conducted where a fixed 0.2Ω resistor with very low TCR replaced the specimen on channel-0. Because the 0.2Ω resistance did not change resistance significantly during the 0° to100° thermal cycle, the bridge output voltage should just be the resistance change of the temperature-compensating resistor. The plot of the resistance change should be a straight line with negative slope, but what we observed was a hysteresis loop with a variation in resistance of up to 40mΩ. The resistance change of the temperature-compensating resistor was converted to the temperature change by dividing the measured change in resistance by the product of the initial resistance and the temperature coefficient of resistance. The temperature of the compensating resistor was then obtained by adding the temperature change calculated from the measured resistance change to the initial temperature of 22°C. Because the chamber controller temperature was used unsuccessfully to mathematically temperature compensate the resistance date in Fig. 8, the measured temperature at the controller is plotted with the temperature of the compensating resistor during one thermal cycle in Figure 9.  &RQWUROOHU 

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To test the resolution of our instrument, we placed a specimen with a fixed 0.2Ω resistor, and ran the experiment at room temperature. Because the bridge circuitry was balanced, the average output was 0 ohms with a standard deviation of 0.53mΩ. Now the current flowing through the resistor was kept constant at 0.0775amps. The voltage present at the input of the ADC of the DAQ card with a pre-amplifier gain of 250 for a 0.53mΩ variation would be 10.3mV. The 10.3mV standard deviation of the voltage variation at the input of the ADC is then 4.2 times larger than the digitizer step size. However, the temperature compensation resistor was in the circuit, and the measured resistance had a small TCR; consequently any small change in the room temperature would cause an input variation. The equivalent temperature change corresponding to 0.00053Ω is about 0.4°C. Thus some of this variation was likely due to variations in the room temperature.

     













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Figure 9. Chamber controller temperature, compensating resistor temperature, and the difference between these. Figure 9 shows the temperature in the compensating resistor lags the controller temperature. Also plotted in Figure 9 is the difference between the compensating resistor temperature and the controller temperature. As can be seen, the temperature of the compensating resistor lags by as much as +/- 21° C, and explains the large variation of resistance seen in Fig. 8 for the mathematically compensated resistance versus temperature plotted. Although the need for mathematical compensation can be eliminated by adjustment of the experimental parameters, the measured temperature is the independent variable used in the Fourier decomposition of the observer resistance change as a function of temperature and time. The DAQ card has now been changed to read the temperature of a thermocouple located at the specimens, which has eliminated most of this temperature difference. However, at the writing of this article, the fatigue test of the

64 I/O flip-chip chip scale package has not been completed, and consequently it is not known if enough of the resistance change amplitude has been balance out to be able to reliably see the resistance change with fatigue. The initial tests have shown that good balance can be obtained and therefore any needed improvements should be relatively minor. Conclusions The goal behind the project was to implement a low-cost instrument to make the high-resolution resistance measurements required to implement the RS technique. This was achieved by using a data acquisition card, custom designed circuit cards, and a LabVIEW application. A current project is underway to implement this same design on the current generation low cost 16-bit DAQ card to provide more dynamic range so the higher harmonics of the Fourier series can be reliably observed. Implementation of the RS technique is low cost primarily because the material properties that contribute to the interconnection resistance being measured are stationary over the period of seconds. Consequently when the voltage samples are take to obtain the in-phase and out-of-phase amplitudes, they do not need to be taken on the same cycle of the sine wave. One sample can be taken and its amplitude stored, and then the computer can come back and get the next sample on the sine wave. This flexibility permits the use of the slowest DAQ cards allowing the use of a low cost DAQ card, and computer. Acknowledgments This research was supported in part by the Integrated Electronics Engineering Center (IEEC) at the State University of New York at Binghamton. The IEEC receives funds from the New York State Science and Technology Foundation and a consortium of industrial members. References 1. J. H. Constable, William Butler, Chung-che Huang, and James M. Pitarresi, “CSP Fatigue Life Predictions Based on Electrical Resistance Change”, in Advances in Electronic Packaging, ASME InterPack'01 Proceedings, Kauai, Hawaii, pp 1-7, July 2001. 2. James H. Constable,"A Comparison of Interconnect Fatigue Damage Indicators", in Advances in Electronic Packaging 1999 Vol. 2, pp. 1893-1900, ASME InterPack'99 Proceedings, Maui, Hawaii, June 1999. 3 Analysis Tech, also known as Anatech, is a manufacturer of electronic reliability testing products for the electronic packaging industry, Wakefield, MA 01880. Company website:http://www.analysistech.com/Event_Detector_ Introduction.htm. 4. Butler, W., J. Constable, J.M. Pitarresi, “Resistance Spectroscopy Applied to Accelerated Life Testing of Solder Joints”, Soc. Exp. Mech., Orlando, FL, pp. 316319, June, 2000. 5. J.H. Constable, "Use of Interconnect Resistance as a Reliability Tool", in Proceedings 44th Electronic Components & Technology Conference, pp 450-457, May 1994.