Implementation of Optimal PID Control for Chaos Synchronization by FPGA Chip Her-Terng Yau, Cheng-Han Wu, Qin-Cheng Liang
Simon C. Li,
Department of Electrical Engineering National Chin-Yi University of Technology Taichung 411, Taiwan E-mail:
[email protected]
Department of Electrical Engineering National University of Tainan Tainan 700, Taiwan E-mail :
[email protected]
Abstract—This paper is concerned with the design of a FPGAbased digital proportional-integral-derivative (PID) controller for synchronization of a continuous chaotic model. By using the EP algorithm, optimal control gains in PID controlled chaotic systems are derived such that a performance index of integrated absolute error (IAE) is as minimal as possible. To verify the system performance, basic electronic components containing OPA, resistor and capacitor elements are used to implement the chaotic Sprott circuits and the proposed digital PID controller is implemented by the FPGA technology. Finally, numerical and experimental results exemplify the synchronization procedure. Keywords—Evolutionary programming (EP), PID, Sprott circuits, Chaos synchronization, FPGA.
I.
INTRODUCTION
Chaos synchronization has gained a lot of attention among scientists from variety of research fields over the last few years [1]. Chaos synchronization can be applied in the vast areas of physics and engineering science, especially in secure communication [2]. The idea of synchronizing two identical chaotic systems was first introduced by Carroll and Pecora [3]. In the most synchronization approaches used for the continuous-time chaotic systems, master-slave or driveresponse formulism is employed. Let us call a particular chaotic system the master (drive) and another one the slave (response). The goal is to synchronize the slave (response) system behavior to the master (drive) one. In order to achieve the synchronization, a nonlinear controller that obtains signals from the master and slave systems and manipulates the slave system should be designed. Recently, many control methods have been developed to achieve chaos synchronization between two identical chaotic systems with different initial conditions [1]. However, in the above-mentioned works, none discusses how to obtain optimal or near optimal digital controller to synchronize continuous chaotic systems according to a specified performance index by FPGA chip. On the other hand, Evolutionary programming (EP) algorithms have been considered both availability and promising techniques for global optimization of complex functions, and also have been applied to solve difficult control problems in engineering [4-5]. Generally, the EP algorithm for global optimization contains four parts: initialization, mutation, competition, and reproduction. Furthermore, in the work of Cao (1997) a quasi-random sequence (QRS) is used to generate
978-1-4244-8452-2/11/$26.00 ©2011 IEEE
the initial population for EP to avoid formulating clusters around an arbitrary local optimal. In fact, the implementation of such technique on digital electronic devices such as field programmable gate array (FPGA) may play a very important role for the rapid prototype development of circuits which can be used for control, real time simulation, and many more [6]. The FPGA comprises thousands of logic gates, some of which are grouped into as a configurable logic block (CLB) to simplify higher-level circuit design. The simplicity and programmability make it the most favorable choice for prototyping a chip design. The main objective of this work is to develop an EP-based digital PID control scheme to solve the synchronization problem of chaotic systems on FPGA. By using the EP algorithm, optimal control gains in PID controlled chaotic systems are derived such that a performance index of integrated absolute error (IAE) as minimal as possible and then, synchronization of the master and slave chaotic systems is achieved, after that the optimal architecture for digital controller will be implemented and simulated by using the very high-speed description language (VHDL) and the ModelSim. Subsequently, the developed architectures for each component will be implemented and tested under the Xilinx Spartan-3 FPGA. Finally, both simulation and experimental results are given to verify the proposed EP-based digital PID scheme’s success in the chaos synchronization. II.
SYSTEM DESCRIPTION
Firstly, we consider two single-input single-output (SISO) master and slave systems described by the following differential equations: Master System㧦 x m (t ) = f (t , x m ) ® ¯ y m (t ) = Cx m
(1)
x s (t ) = f (t , x s ) + Bu(t ) ® ¯ y s (t ) = Cx s
(2)
Slave System㧦
FPM 2011 56
where xm(t) = [xm1, xm2,...,xmn]∈Rn and xs (t) = [xs1, xs2,...,xsn]∈Rn are the state vectors of Master and Slave systems, respectively. f : R× Rn → Rn is a given nonlinear function. ym(t ) ∈ R and ys (t )∈ R are the outputs of the master and slave systems, respectively. B ∈ R n×1 and C ∈ R1×n are the system matrices. u(t) ∈ R is the control input and added in the slave system (2) to achieve synchronization between master and slave systems. Generally many chaotic systems can be expressed by (1). For examples [1], the Sprott circuit, modified Chua’s circuit, Duffing-Holmes system, Lorenz system and Lu system all belong to the class defined by (1). Let the error states be e1 =xm,1−xs,1,e2 =xm,2−xs,2,",en =xm,n−xs,n. The objective of this paper is that for different initial conditions of systems (1) and (2), the two coupled system to be synchronized by designing a simple but effective PID controller u(t) based on EP algorithm such that lim x m (t ) − x s (t ) → 0 .
(3)
t →∞
The procedure to determine the PID controller u is to first define the output error signal y e = y m − y s , then the continuous-form of a PID controller, with input y e (⋅) and output u (⋅) , is generally given as ª 1 u (t ) = K p « ye (t ) + Ti ¬
³0 ye (t )dt + Td t
º. d ye (t )» dt ¼
(5)
Where u (k ) is the kth samping output data of PID controller, is the error sum, and T is the samping time constant. Therefore, Eq.(6) can be rewritten as S (k ) = ¦ ye (k )
u (k ) = K p ye (k ) + K i S (k ) + K d [ ye (k ) − ye (k − 1)]
where K i = K p 1 Ti
is the integral gain constant
(6)
and K d = K p Td T
is
the derivative gain constant. In general, for a controller design, the performance criterion or objective function can be defined according to our desired specifications. Two kinds of performance criteria usually considered in the EP algorithm are the integrated squared error (ISE) and the integrated absolute error (IAE). In this study, the IAE index is used as the objective function (OF), which is given as
(7)
k =1
where E (k ) = [e1 , e2 , " , en ] and ⋅ is the Euclidean norm of a vector, and k is referred to as the sampling time point and k f is the total numbers of sampling. In the following, based on using EP algorithm, we will develop a tuning method for the digital PID controller with optimal gain parameters to minimize the objective function score (7). III.
AN EVOLUTIONARY PROGRAMMING (EP) ALGORITHM TO SOLVE THE OPTIMIZATION PROBLEM
Since the EP algorithm has been considered as an available and promising technique for the global optimization of complex functions, we introduce the EP algorithm to solve this problem. The EP-based PID control system consists of master and slave chaotic systems to be synchronized, a PID controller and an EP algorithm, as shown in Fig. 1. ym is the output of the master system, ys is the output of the slave system, and u is the control input generated by the PID controller as defined in (5). The PID troller is proposed with the optimal parameters derived from the EP algorithm such that the value of IAE in (7) is minimized as possibly.
ym
ye(t)
ye(k)
(4)
Where K p is the proportional gain constant, Ti is the integral time constant, and Td is the derivative time constant. In order to implement this controller by FPGA chip, the continuous type PID controller (4) is rewritten as a digital type PID controller as shown below. º. ª T 1 u (k ) = K p « ye (k ) + S (k ) + d [ ye (k ) − ye (k − 1)]» Ti T ¼ ¬
kf
OF = IAE = ¦ E (k )
u(k)
ys
K p K i Kd
Fig. 1. Blocks diagram of chaos synchronization system. In this section, an extended EP algorithm is proposed to obtain the digital PID controller with optimal gain parameters to minimize the following objective function (OF) score (6). Let g be the continuously differentiable matrix-valued function
{
}
3 defined for g ∈ S , where S = g ∈ R 0 ≤ gi ≤ Mi , i = 1,2,3 ,
M i is the searching space and is bounded. The optimization problem involves finding g * = [k *p , ki*, kd* ] ∈ S such that the
OF performance index of the system is minimized. More accurately, the optimization problem (P1) is stated mathematically as (P1): To find g* ∈ S such that kf
OF = IAE = ¦ E (k ) , for g* ∈ S
(8)
k =1
is minimized.
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Based on the results shown in [4], an extended EP algorithm for solving the above optimization problem is described as following steps: step1:
Generate an initial population P0 = [ p1, p2,!, pN ] of size N by randomly initializing each 3-dimensional solution vector p i ∈ S , i = 1,2, " , N , according to the quasi-random sequence (QRS).
such that the OF performance index of the system is minimized as possibly. Otherwise, return to Step 3. IV.
Master㧦
step2:
xm,1 = xm,2
Calculate the fitness score (objective function) fi = f ( pi ) for every pi , i =1, 2,!, N , where kf
f i ( p i ) = OF = ¦ E ( k )
(9)
k =1
SIMULATION AND EXPERIMENTAL RESULTS
In this section, we illustrate the EP-based digital PID controller design for synchronization of Sprott circuits, which are typical chaotic systems that have been thoroughly studied [7-9]. Now consider the following Sprott circuits:
xm,2 = xm,3
Mutate every pi , i = 1,2, " , N , based on the statistics to p double the population size from N to 2N, and generate i + N in the following f · § p i + N , j = p i , j + N ¨¨ 0, β i ¸¸, ∀j = 1,2,3 , f ¦¹ ©
(10)
where pi, j denotes the jth element of the ith individual, f N (0, β i ) represents a Gaussion random variable with a f¦ f mean zero and variance β i , f ¦ is the sum of all fitness f¦ f scores, and β is a parameter to scale i . f¦
step4:
Calculate the fitness score fi + N for every pi + N , i = 1,2,", N by using equation (9). By the stochastic competition process, p i , i = 1,2, " , N competes with p j , j = N + 1, " ,2 N randomly each against the other. If
fi < f j , pi is the winner and survives; otherwise, p j is the winner and pi is replaced by p j . After the competition process, we select the N winners for the next generation and let the individual with the minimum objective function in the winners be p1 . step5:
If the value f¦ converges to a minimum value, then g* = p1 is the global optimum value and g * = [k *p , ki*, kd* ]
(11)
,
(12)
xm,3 = −1.2 xm,1 − xm, 2 − 0.6 xm,3 + 2 ⋅ sign (xm,1 )
Slave㧦 x s,1 = xs, 2
x s, 2 = xs ,3 + u (t )
step3:
.
x s,3 = −1.2 xs,1 − xs, 2 − 0.6 xs ,3 + 2 ⋅ sign (xs,1 )
where xm and xs denote the derivative of xm and xs with respect to time t, respectively. The initial value conditions [xm,1(0), xm,2 (0), xm,3(0)] = [0.1 0.1 0.1] and [xs,1(0), xs,2(0), xs,3(0)] = [−1-1-1] are used in this example. We solved the optimization problem (P1) with N=30 and β=0.001 by using the control toolbox of Matlab and Simulink. According to the proposed EP algorithm, we generated P0 = [p1,p2, . . .,p30] according to the QRS. After a series of EP algorithm manipulations, the convergence curve of IAE value versus iteration is depicted in Fig. 2. It can be easily observed from Fig. 2 that it converges after about 170 iterations and its final value of IAE is f g * = 0.7592 . Correspondingly, the PID control gains are g * = [ K *p , Ki*, K d* ] = [20 0.0018 20] . The
( )
trajectories of Kp, Ki, and Kd during the evolutionary procedure are also shown in Fig. 3. For reference, the output response using the resulting PID control gains z* is then shown in Fig. 4. The simulation results show that the proposed PID controller via EP algorithm is viable for synchronization of Sprott chaotic systems. In order to verify the proposed PID controller in practical system, an electronic circuit implementing Eqs. (11) and (12) is shown in Fig. 5 [8], shows the experimental results when these circuits are connected in a master/slave configuration. The controller was implemented by a Xilinx Spartan-3 FPGA and AD/DA converters with a sampling rate of 1289 kHz and shown in Fig 6. From Fig. 7, it can be seen that the slave circuit response is synchronized to the master circuit response after the control is action at t=20 second. The experimental results of error dynamics in Fig. 7(d) show a convergence to a very small synchronization error. V.
CONCLUSIONS
Based on FPGA chip, a simple and successful digital PID controller has been proposed for synchronizing two chaotic systems by the evolutionary programming algorithm. An EP algorithm is derived such that three PID controller gains can be directly obtained by solving specified optimization problems as
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25
20 kp ki kd
15 Control gains
defined above. Moreover, the proposed EP-based PID scheme is then successfully applied to a chaotic circuit system. The simulation and experimental results verify that the methods are correct and practical. Compared with the existing reports for chaotic synchronization, the proposed FPGA-based optimal PID controller is not only effective but also simple in design to implement.
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REFERENCES
[4] [5]
[6]
[7] [8]
[9]
0
50
100
150 Iteration
200
250
Fig.3 Iteration response of
300
k p , ki , k d
5 xm1 xs1
4
← control in action 3 2
xm1• xs1
[3]
-5
1 0 -1 -2 -3 -4 -5
0
5
10
15
20 Time(sec)
25
30
35
40
(a) 5
0.94
4
0.92
3
0.9
2
0.88
1
xm2• xs2
[2]
0
G. Chen, X. Dong, 1998. From chaos to order: methodologies, perspectives and applications. World Scientific, Singapore. L. Kocarev, U. Parlitz, “General approach for chaotic synchronization with application to communication”. Phys Rev Lett 74: 5028 ̄ 5031, 1995. L. M. Pecora, T. L. Carroll, “Synchronization in chaotic systems,” Phys Rev Lett Vol. 64, pp. 821–824, 1990. Y. J. Cao, Eigenvalue optimization problems via evolutionary programming. Electronics Letters, 33, 642̄643, 1997. W. D. chang, J. J. Yan, “Optimum Setting of PID ControllersBased on Using Evolutionary Programming Algorithm,” Journal of the Chinese lnstitute of Engineers, Vol. 27, No. 3, pp. 439-442, 2004. Z. Zhou, T. Li, T. Takahahi and E. Ho, “FPGA Realization of a Highperformance Servo Controller for PMSM,” in Proceeding of the 9th IEEE Application Power Electronics conference and Exposition, vol.3, pp. 1604~1609, 2004 J. C. Sprott. “A new class of chaotic circuits,” Phys Lett A 266, pp. 19– 23, 2000. David I. R. Almeida, J. Alvarez, J.G. Barajas, “Robust synchronization of Sprott circuits using sliding mode control”. Chaos, Solitons & Fractals 30: 11̄18, 2006. H. C. Chen, J. F. Chang, J. J. Yan and T. L. Liao, “EP-based PID control design for chaotic synchronization with application in secure communication,” Expert Systems with Applications, Vol. 34, pp. 11691177, 2008.
0.86 IAE
[1]
0.84
-1 -2
0.8
-3
0.78
-4
0.76
-5 0
50
100
150 Iteration
200
250
← control in action
0
0.82
0.74
xm2 xs2
0
5
10
15
20 Time(sec)
25
30
35
40
300
(b)
Fig. 2 Convergence curve of IAE
59
u(t) -40 0 5 10
-30
15 20 Time(sec) 25 30
0 24
-10
-20
← control in action
35
error states e1 ,e2 ,e3 . (e) The control input. (The control u(t) is
(e)
Fig.4. Time responses using the EP-based PID controller. (a) x m,1 v.s. x s ,1 . (b) x m , 2 v.s. x s , 2 . (c) x m ,3 v.s. x s ,3 . (d) The VEE
8
R45 1meg
R35 1meg
6
4
C6 200pF
VEE
VEE
(b) Fig. 5. Electronic implementations of Sprott circuits. (a) master system; (b) slave system.
u (k )
ye (k )
VEE
VEE
7
R47 10k
R41 10k
22
20
VEE
VEE
VC C
U20 UA741 VCC
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VEE
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U18 UA741 VCC
R37 6k
R40 10k
23
xs3
21
VEE
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15
R32 1K 17
16
R33 10k D3 D4 1N4148 1N4148
VEE
18
VEE
VEE
VC C
U16 UA741 VCC
R31 40k
19
R38 10k
R34 10k
VEE
VEE
VC C
U21x UA741 VCC
R39 10k
8
5
3
R45 1meg
R35 1meg
R27 1meg
6
4
1
VEE
VEE
VCC
U19 UA741 VCC
C6 200pF
R42 10meg
VEE
VEE
VCC
U14 UA741 VCC
C5 200pF
R30 VEE 10meg
VEE
VCC
U12 UA741 VCC
R47 10k
R41 10k
xm2
2
22
20
VEE
VEE
VE E
VCC
U20 UA741 VCC
R46 10k
VEE
VE E
VCC
U18 UA741 VCC
R37 6k
R28 10k 13
23
xm3
21
R40 10k
VEE
VE E
VCC
VEE U15 UA741 VCC
VE E
VCC
U13 UA741 VCC
15
14
R32 1K
R29 10k
17
16
D3 D4 1N41481N4148
R33 10k
VEE
V2 12
V1 12
18
VEE
V EE
VCC
U16 UA741 VCC
R31 40k
19
R38 10k
R34 10k
VEE
VEE
V CC
U21 UA741 VCC
R39 10k
xm3 xs3
VCC
U19 UA741 VCC
R42 10meg
VCC
VCC
14
R29 10k
0
VEE
5
xs2
VEE U15 UA741 VCC
VEE
VCC
U13 UA741 VCC
-6
U14 UA741 VCC
40 13
-4
C5 200pF
VEE
V2 12
12K
12 R26
VCC
1
VC C
u(t) 12K
e1 e2 e3
R28 10k
xs1
(c)
U21 UA741 VCC
20 VE E
xm1
-3
R30 VEE 10meg
2
(d) VCC
-2
VCC
35 12R26
← control in action 40 U11 UA741 VCC
-1
VEE
30
35
U12 UA741 VCC
25 30
1
20 Time(sec) 11
← control in action
R13 10k
R12 10k
R27 1meg
15 25
VC C
6 20 Time(sec)
VEE
R25 10k
2
t)
3
R1 10k
10 3
10 15
V1 12
8 R24 10meg
-4
C4 200pF
5 10
11
0 5
R25 10k
-8 0
C4 200pF
-5
R24 10meg
VCC
0
U11 UA741 VCC
4
R23 10k
xm3• xs3 3
R23 10k
e1• e2• e3
5
4
(a)
2
-2
ys
40
ym
(a)
activated at t=20 sec.)
60
(b)
(b) Fig. 6. The Black diagram (a) and the photograph (b) of the proposed chaos synchronization system.
(c)
(a)
(d) Fig. 7. Experimental results of synchronization. (a) x m,1 v.s. x s ,1 . (b) x m , 2 v.s. x s , 2 . (c) x m ,3 v.s. x s ,3 . (d) The error states e1 ,e2 ,e3 .
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