micromachines Article
Improving ESD Protection Robustness Using SiGe Source/Drain Regions in Tunnel FET Zhaonian Yang * , Yuan Yang, Ningmei Yu and Juin J. Liou Shaanxi Key Laboratory of Complex System Control and Intelligent Information Processing, Xi’an University of Technology, Xi’an 710048, China;
[email protected] (Y.Y.);
[email protected] (N.Y.);
[email protected] (J.J.L.) * Correspondence:
[email protected]; Tel.: +86-029-823-12431 Received: 14 November 2018; Accepted: 9 December 2018; Published: 12 December 2018
Abstract: Currently, a tunnel field-effect transistor (TFET) is being considered as a suitable electrostatic discharge (ESD) protection device in advanced technology. In addition, silicon-germanium (SiGe) engineering is shown to improve the performance of TFET-based ESD protection devices. In this paper, a new TFET with SiGe source/drain (S/D) regions is proposed, and its ESD characteristics are evaluated using technology computer aided design (TCAD) simulations. Under a transmission line pulsing (TLP) stressing condition, the triggering voltage of the SiGe S/D TFET is reduced by 35% and the failure current is increased by 17% in comparison with the conventional Si S/D TFET. Physical insights relevant to the ESD enhancement of the SiGe S/D TFET are provided and discussed. Keywords: band-to-band tunneling (BTBT); electrostatic discharge (ESD); tunnel field-effect transistor (TFET); Silicon-Germanium source/drain (SiGe S/D); technology computer aided design (TCAD)
1. Introduction A traditional metal-oxide-semiconductor field-effect transistor (MOSFET) has a 60 mV/dec subthreshold swing at room temperature, which limits the application of this device in ultra-low power integrated circuits (ICs) [1,2]. The tunnel field-effect transistor (TFET) is a promising candidate for replacing the conventional MOSFET in low power ICs [3–5]. The TFET employs a band-to-band tunneling (BTBT) mechanism and is able to theoretically achieve a subthreshold swing smaller than 60 mV/dec. However, the TFET has a very low driving current compared with the MOSFET, which means it is difficult to realize a high-speed circuit using pure TFETs. Recently, the mixed TFET–MOSFET circuit design methodology was reported, by skillfully designing the circuits such as static random access memory (SRAM), level shifter, and even electrostatic discharge (ESD) protection circuits with two kinds of devices, where both high performance and low standby current can be achieved [6–9]. ESD protection is a very challenging reliability issue of modern integrated circuits (ICs), especially in advanced nanoscale technologies [9–14]. As mentioned in reference [9], TFET can be used to replace the traditional diodes in an ESD protection network to enhance the ESD robustness in nanoscale technology ICs. The ESD behavior of the TFET has been studied using experiments and technology computer aided design (TCAD) simulations [15–18]. However, these results show that the ESD robustness of TFET under positive ESD stress is low. It has been verified that using a silicon-germanium (SiGe) source in the TFET can increase the driving current compared with the silicon TFET [19–22]. This is because Ge has a narrower band-gap and lower carrier effective mass than Si, and these features increase the tunneling probability. The SiGe engineering has also been introduced in the ESD protection devices to enhance the ESD performance [12,13]. However, as for ESD protection applications, the physical processes mainly
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occur occuron onthe thedrain drainside sideofofthe theTFET. TFET.As Assuch, such,using usingaaSiGe SiGesource sourcedoes doesnot notbenefit benefitTFET’s TFET’sESD ESD characteristics [16]. characteristics [16]. InInthis thispaper, paper,we wepropose proposeaanew newTFET TFETwith withSiGe SiGeboth bothin inthe thesource sourceand anddrain drain(S/D) (S/D)regions regionsfor for ESD protection. The performance of the proposed device will be investigated using TCAD ESD protection. The performance of the proposed device will be investigated using TCAD simulations. simulations. The results simulation willboth showthe that both the voltage triggering and the failure current The simulation will results show that triggering andvoltage the failure current of the SiGe ofS/D the TFET SiGe S/D TFET are improved over those of the conventional Si TFET. The impact of various are improved over those of the conventional Si TFET. The impact of various technology technology the ESDofbehavior theTFET SiGe S/D also be given. parametersparameters on the ESDon behavior the SiGeof S/D will TFET also bewill given. 2.2.Basic BasicConcept ConceptofofElectrostatic ElectrostaticDischarge Discharge(ESD) (ESD)Protection ProtectionTunnel TunnelField-Effect Field-EffectTransistor Transistor (TFET) and theand Protection Network (TFET) the Protection Network TFETisisessentially essentiallyaareverse reversebiased biasedgated gatedp-i-n p-i-ndiode. diode.As Asfor forESD ESDprotection, protection,TFET, TFET,the thegate gate TFET terminalisisconnected connectedtotothe thesource sourceby bydefault. default.Under Underthe thenegative negativeESD ESDstress, stress,namely, namely,ESD ESDcurrent current terminal injectedinto intothe the source terminal of TFET with drain terminal grounded. will operate isisinjected source terminal of TFET thethe with drain terminal grounded. TFETTFET will operate in a in a positive conduction mode and has acurrent high current discharge capability as illustrated positive diode diode conduction mode and has a high discharge capability as illustrated in Figurein Figure 1a. Whereas under positive ESD the stress, thecurrent ESD current is injected into the drain terminal 1a. Whereas under positive ESD stress, ESD is injected into the drain terminal with with the the source terminal grounded. TFET operate in avalanche breakdown mode dischargethe theESD ESD source terminal grounded. TFET willwill operate in avalanche breakdown mode toto discharge currentasasillustrated illustratedininFigure Figure1b. 1b.Since Sinceavalanche avalanchebreakdown breakdownrequires requiresa arelatively relativelyhigh highelectric electricfield, field, current theconduction conductionvoltage voltageofofTFET TFETunder underpositive positiveESD ESDstress stressisishigh, high,making makingititunacceptable unacceptableininadvanced advanced the nanoscaletechnologies. technologies.Thus, Thus,the theresearch researchon onTFET TFETunder underESD ESDstress stressmainly mainlyfocuses focuseson onthe thepositive positive nanoscale dischargemode. mode. discharge
Figure1.1.Schematics Schematicsofoftunnel tunnelfield-effect field-effecttransistor transistor(TFET) (TFET)under under(a) (a)negative negativeand and(b) (b)positive positive Figure electrostatic discharge (ESD) stresses. electrostatic discharge (ESD) stresses.
shouldbebementioned mentionedthat, that, since TFET has a relatively positive mode ESD robustness, ItItshould since TFET has a relatively lowlow positive mode ESD robustness, it it cannot be used as a single protection device in an IC, but can be used to implement a protection cannot be used as a single protection device in an IC, but can be used to implement a protection networkasasshown shownininFigure Figure2,2,ininwhich whichTFET TFETisisused usedtotoreplace replacethe thetraditional traditionaldiode diodetotoenhance enhancethe the network whole chip ESD robustness. As for the pin-to-pin ESD event, their discharge paths exist in the TFET whole chip ESD robustness. As for the pin-to-pin ESD event, their discharge paths exist in the TFET basedprotection protectionnetwork networkasasshown shownininFigure Figure2,2,whereas whereasininthe thetraditional traditionaldiode-based diode-basedprotection protection based networkonly onlyPath2 Path2exists. exists.InInPath1 Path1and andPath3, Path3,TFET1 TFET1and andTFET4 TFET4operate operateininavalanche avalanchebreakdown breakdown network mode with low ESD robustness. Thus, it is necessary to improve the robustness of TFET under mode with low ESD robustness. Thus, it is necessary to improve the robustness of TFET positive under ESD stress. positive ESD stress.
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Figure 2. Schematic of the ESD protection network with TFETs. Figure Figure 2. 2. Schematic Schematic of of the the ESD ESD protection protection network with TFETs.
3. Device Structure and Simulation Setup 3. Device Structure Structure and Simulation Simulation Setup 3. Device As illustrated and in Figure 3, theSetup device structure proposed in this work is identical to the As illustrated in Figure 3, the device structure proposed in this work is identical to identical the conventional conventional silicon point-tunneling TFET except that the source and the drain are made of As illustrated in Figure 3, the device structure proposed in this work regions is to the silicon point-tunneling TFET except that the source and the drain regions are made of SiGe. The device SiGe. The device sizepoint-tunneling is not set to a very value [11,23].are Themade default conventional silicon TFETsmall except thatfor thebetter sourceheat anddissipation the drain regions of size isThe not set to asize very value better heat dissipation The default[11,23]. parameters device parameters are:issmall Thickness the gate oxide (HfO ) Tox[11,23]. = heat 4 nm, thickness ofdevice the silicon TSi = 1 SiGe. device not set to of afor very small value for 2better dissipation The default are: of the gate (HfO =oxide 4 nm, thickness of4the Tof =of1 gate µm,silicon width the oxof 2) T Si the μm, Thickness width of the device Woxide Si = 1 μm, the junction nm, length LG = 100 device parameters are: Thickness of depth the gate (HfO 2) X Tj ox= =10 nm,silicon thickness the TofSinm, =1 device W = 1 µm, depth of the junction X = 10 nm, length of the gate L = 100 nm, and source and the and width source and drainW side silicide blocking lengths SOPXj==DOP = 100 Silicide blocking is used Si of j of the G nm. of μm, thethe device Si = 1 μm, depth junction 10 nm, length the gate LG = 100 nm, drain side silicide lengths SOP =current DOPlengths = crowding 100 nm. blocking isSilicide used inblocking ESD protection in ESD protection devices to reduce the The doping concentrations and source and theblocking drain side silicide blocking SOPSilicide =effect DOP[12,16]. = 100 nm. is used 20 cm −3, doping 19 cm−3, andof 16drain, devices to reduce the current crowding effect [12,16]. The concentrations the source, of the source, drain, and substrate are N S = 1 × 10 N D = 5 × 10 N Sub = 1 × 10 cm−3, in ESD protection devices to reduce the current crowding effect [12,16]. The doping concentrations 20 cm−3 , N = 5 × 1019 cm−3 , and N 16 cm−3 , respectively. and substrate are N = 1 × 10 = 1 × 10 19 cm −3, andpossible respectively. doping profileare is used to avoid Sub of the source,Abrupt drain,Sand substrate NSD= 1in×the 1020simulation. cm−3, ND = In 5 ×order 10 NSub= 1 ×high 1016defect cm−3, Abrupt doping profile is used in the simulation. In order to avoid possible high defect density at the density at the SiGe/Si interface, the default Ge mole fraction is set at 0.4 [22]. respectively. Abrupt doping profile is used in the simulation. In order to avoid possible high defect SiGe/Si interface, the default Ge mole fraction is set at 0.4 [22]. density at the SiGe/Si interface, the default Ge mole fraction is set at 0.4 [22].
Figure TFET. Figure3.3.Schematic Schematicof ofthe theproposed proposedSiGe SiGesource/drain source/drain (S/D) (S/D) TFET.
Figure 3. Schematic of the proposed SiGe source/drain (S/D) TFET.
The the source region is The SiGe SiGe S/D S/D TFET TFET can can be be fabricated fabricatedusing usingthe thefollowing followingprocess processflow. flow.First, First, the source region recessed into the p-Si substrate by an etching process. Then the p+ SiGe source region is grown by is recessed intoS/D theTFET p-Si substrate by an etching Then the p+ SiGe source is grown by The SiGe can be fabricated usingprocess. the following process flow. First,region the source region epitaxy. Similarly, the drain region is recessed into the p-Si substrate by the etching process and the n+ epitaxy. Similarly, the drain region is recessed into the p-Si substrate by the etching process and the is recessed into the p-Si substrate by an etching process. Then the p+ SiGe source region is grown by SiGe drain region isthe grown by epitaxy. Afterward, dielectric and the gate are deposited n+ SiGe drain region is grown byisepitaxy. Afterward, the gate dielectric and stack theprocess gate stack are epitaxy. Similarly, drain region recessed intothe thegate p-Si substrate by the etching and the and patterned. Finally, the spacers are formed. deposited and patterned. Finally, the spacers are formed. n+ SiGe drain region is grown by epitaxy. Afterward, the gate dielectric and the gate stack are Simulations are out Sentaurus simulator. Simulations are carried carried out in in the Sentaurus simulator. The The dynamic dynamic nonlocal nonlocal BTBT BTBT model model is is deposited and patterned. Finally, thethe spacers are formed. used instead of the local BTBT model. This is because the dynamic model takes into account usedSimulations instead of the BTBT This is because the dynamic model takes into account the are local carried out model. in the Sentaurus simulator. The dynamic nonlocal BTBT modelthe is spatial variation of energy andThis therefore can model model the BTBT BTBT probability moreaccount accurately. spatial variation of the the energy bands and therefore can the probability more accurately. used instead of the local BTBTbands model. is because the dynamic model takes into the The fitted coefficients of the SiGe BTBT probability are calculated by linear interpolation between the The fitted coefficients the SiGe BTBT probability are calculated linear interpolation the spatial variation of theof energy bands and therefore can model the by BTBT probability morebetween accurately. parameters of pure Si and pure Ge [23]. The lattice temperature is calculated using the thermodynamic parameters of pure ofSithe and [23]. The temperature is calculatedbetween using the the The fitted coefficients SiGepure BTBTGe probability arelattice calculated by linear interpolation model. Van of Overstraeten-de Man generation model, high field Philips thermodynamic model.SiVan avalanche generation model, high fieldand saturation, parameters pure andOverstraeten-de pureavalanche Ge [23].Man The lattice temperature is saturation, calculated using the
thermodynamic model. Van Overstraeten-de Man avalanche generation model, high field saturation,
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unified mobility models, band-gap model and model dopingand dependent Shockley-Read-Hall and Philips unified mobility models,narrowing band-gap narrowing doping dependent Shockleyrecombination model are also used. Read-Hall recombination model are also used. Transmission line pulsing (TLP) pulses, which mimic the stressing of the human body model (HBM), are used to simulate the quasi-static current-voltage (I-V) behavior of the devices during the ESD conditions. The drain terminal of the TFET was stressed with TLP pulses while keeping the gate The rise rise time time and and the the pulsewidth pulsewidth are are set set at at 10 10 ns ns and and 100 100 ns, ns, and the source terminals grounded. The respectively. The voltage samples are obtained by averaging the transient data in the range of 60 ns to respectively. The voltage samples are obtained by averaging the transient data in the range of 60 ns 90 90 ns ns [16]. to [16]. 4. Simulation Simulation Results Results and and Discussion Discussion 4. The TLP curves of of both and Si Si TFETs TFETs are The TLP I-V I-V curves both the the SiGe SiGe S/D S/D and are shown shown in in Figure Figure 4. 4. The The triggering triggering voltage and failure current of the SiGe S/D TFET are 4.1 V and 0.7 mA/µm, respectively, which are 35% voltage and failure current of the SiGe S/D TFET are 4.1 V and 0.7 mA/μm, respectively, which are lower and 17% higher than those of the Si counterpart. These improved key parameters will make the 35% lower and 17% higher than those of the Si counterpart. These improved key parameters will new TFET easier to fit into the modern ESD design window and offer higher ESD protection capability. make the new TFET easier to fit into the modern ESD design window and offer higher ESD protection It should beItnoted that SiGe source has nearly influence oninfluence the ESD characteristics [15], and the capability. should bethe noted that the SiGe sourceno has nearly no on the ESD characteristics improvement is achieved by introducing the SiGe drain in the TFET. [15], and the improvement is achieved by introducing the SiGe drain in the TFET. The reduction reduction of the triggering triggering voltage voltage of of the the TFET TFET is is achieved achieved by by introducing introducing the the SiGe SiGe material material The of the in the drain region. The Ge material has the following three advantages in triggering the TFET in the drain region. The Ge material has the following three advantages in triggering the TFET atat a a lower voltage. First, Ge has a higher BTBT probability than Si due to its narrower bandgap and lower voltage. First, Ge has a higher BTBT probability than Si due to its narrower bandgap and lower lower carrier effective The TFET a BTBT-assisted avalanche generationmechanism, mechanism,hence hence aa carrier effective mass.mass. The TFET has has a BTBT-assisted avalanche generation higher BTBT probability gives rise to a more significant avalanche breakdown [16,17]. Second, Ge has has higher BTBT probability gives rise to a more significant avalanche breakdown [16,17]. Second, Ge a higher impact ionization coefficient than Si under the same electric field [24]. This means that a higher impact ionization coefficient than Si under the same electric field [24]. This means that the the critical electric field required for avalanche breakdown in the SiGe S/DTFET is lower than that in the Si critical electric field required for avalanche breakdown in the SiGe S/DTFET is lower than that in the TFET. Third, the drain/substrate heterojunction offers an enhanced electric field, which helps to reduce Si TFET. Third, the drain/substrate heterojunction offers an enhanced electric field, which helps to the triggering voltage [25]. SiGe andSiGe Si have the bandgap reduce the triggering voltage [25]. andsimilar Si haveelectron similaraffinities, electron thus affinities, thus thedifference bandgap approximately equals the valence band offset. Figure 5a shows the energy bands of the SiGe S/D TFET difference approximately equals the valence band offset. Figure 5a shows the energy bands of the stressed under a TLP current density of 0.5 mA/µm. It can be seen that there is a valence band offset SiGe S/D TFET stressed under a TLP current density of 0.5 mA/μm. It can be seen that there is a at the drain/substrate This obstructs the holes moving the source, causingto some valence band offset at interface. the drain/substrate interface. Thisfrom obstructs thetoholes from moving the holes to accumulate on the drain side, as evidenced by the hole concentration plot shown in Figure 5b, source, causing some holes to accumulate on the drain side, as evidenced by the hole concentration with a significant hole density peak at a distance of 5 nm below the Si/SiO2 interface on the drain side. plot shown in Figure 5b, with a significant hole density peak at a distance of 5 nm below the Si/SiO2 This leadson to the an enhancement in the electric at the drain/substrate consequently a interface drain side. This leads to anfield enhancement in the electricinterface field at and the drain/substrate reduction in the trigger voltage. interface and consequently a reduction in the trigger voltage.
TLP Current (mA/μm)
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SiGe S/D TFET Pure Si TFET
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Figure TFET and and Si Si TFET. TFET. Figure 4. 4. Transmission Transmission line line pulsing pulsing (TLP) (TLP) I-V I-V curves of the SiGe S/D S/D TFET
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Figure5. 5.(a) (a)Energy Energy bandsand and(b) (b)hole holeconcentration concentrationsimulated simulatedat at90 90ns nsunder underaaaTLP TLPcurrent currentdensity density Figure Figure 5. (a) Energy bands bands and (b) hole concentration simulated at 90 ns under TLP current density 2 interface. of 0.5 0.5mA/μm, mA/μm,at at distance of nm below the Si/SiO 2 interface. of of 0.5 mA/µm, ataaadistance distanceof of555nm nmbelow belowthe theSi/SiO Si/SiO interface. 2
Asshown shownin inFigure Figure2, 2,the thefailure failure currentof ofthe thenew newTFET TFET is also improved. Under an ESD event, As shown in Figure 2, the failure current current of the new TFET is isalso alsoimproved. improved. Under Underan anESD ESDevent, event, As the Joule heat is the main heat component in the device, and it can be expressed as in reference [26], the Joule Joule heat heat is is the the main heat component in the device, and it can be expressed as in reference [26], the 2 2 || J JJpp | |22 + || JJ| nJn ||2|2 H = H + H = p n Joule = H p + H n = Joule = HHJoule H pp + Hnn = pq pqμμ p ++nq nqμμ n pqµpp nqµn n
(1) (1) (1)
where H is is the heat, heat, J is the the currentdensity, density, μ is the the mobility, and and subscripts nn and and p denote electrons electrons where where H H is the the heat, JJ is is thecurrent current density, μµ is is the mobility, mobility, and subscripts subscripts n and pp denote denote electrons and holes, respectively. The hole Joule heat is higher than the electron Joule heat because the impact and and holes, holes, respectively. respectively. The The hole hole Joule Joule heat heat is is higher higher than than the the electron electron Joule Joule heat heat because because the the impact impact generated holes move move fromthe the drain interface interface to the the source through through the channel channel region, whereas whereas the generated generated holes holes move from from the drain drain interface to to the source source through the the channel region, region, whereas the the electrons are collected by the drain terminal without traveling. Furthermore, the high electric field electrons are collected by the drain terminal without traveling. Furthermore, the high electric field electrons are collected by the drain terminal without traveling. Furthermore, the high electric field and and carrier carrier scattering scattering significantly significantly degrade degrade the the mobility, mobility, especially especially near the the drain and and the source source and carrier scattering significantly degrade the mobility, especially near thenear drain anddrain the sourcethe interfaces. interfaces. These, These, in in turn, cause cause aa large large amount amount of of hole hole Joule Joule heat heat generated generated at at the the interface interface regions regions interfaces. These, in turn, causeturn, a large amount of hole Joule heat generated at the interface regions as shown in as shown in Figure 6. The hole mobility in the SiGe S/D TFET is higher than that in the conventional as shown in Figure 6. The hole mobility in the SiGe S/D TFET is higher than that in the conventional Figure 6. The hole mobility in the SiGe S/D TFET is higher than that in the conventional Si TFET as SiTFET TFETas asshown shownin inFigure Figure7. 7.Thus, Thus,the the SiGeS/D S/D TFEThas hasan anelevated elevatedrobustness robustnessdue dueto tothe the factthat that Si shown in Figure 7. Thus, the SiGe S/D SiGe TFET hasTFET an elevated robustness due to the fact that fact the hole the hole Joule heat is the dominate heat source and hole mobility in SiGe is higher than that in Si. the hole Joule heat is the dominate heatand source hole mobility SiGe isthan higher Joule heat is the dominate heat source holeand mobility in SiGe isinhigher thatthan in Si.that in Si. The thermal thermal conductivity conductivity is is another another important important factor factor influencing influencing the the ESD ESD thermal thermal breakdown. breakdown. The The thermal conductivity is another important factor influencing the ESD thermal breakdown. SiGe has aa lower lower thermal conductivity conductivity compared with with Si, which which hinders the the heat dissipation dissipation [27,28]. SiGe SiGe has has a lower thermal thermal conductivitycompared compared withSi, Si, whichhinders hinders theheat heat dissipation[27,28]. [27,28]. However, the volume of the SiGe regions are relatively small and the reduction in the the triggering triggering However, the volume of the SiGe regions are relatively small and the reduction in However, the volume of the SiGe regions are relatively small and the reduction in the triggering voltage implies that that less Joule Joule heat is is generated. voltage voltage implies implies that less less Joule heat heat is generated. generated.
Figure6. Contourplot at90 90ns nsunder underaaaTLP TLPcurrent currentdensity densityof of0.5 0.5mA/µm. mA/μm. Figure 6. Contour plotof of hole hole Joule Joule heat heat simulated simulated at at 90 ns under TLP current Figure density of 0.5 mA/μm.
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Figure Hole mobilities adistance distance 5nm nm below the Si/SiO 2interface. interface. Figure 7. mobilities at aa distance of 55 nm below the Si/SiO Figure 7.7.Hole Hole mobilities atat ofof below the Si/SiO 22 interface.
InInthe the TFET, the increase in the Ge mole fraction (x) can cause reduction ininthe theSiGe SiGeS/D S/DTFET, TFET,the theincrease increasein inthe theGe Gemole molefraction fraction(x) (x)can cancause causeaaareduction reductionin the In SiGe S/D the triggering voltage, and a slight increase in the failure current as shown in Figure 8. This trend can be triggeringvoltage, voltage,and andaaslight slightincrease increaseininthe thefailure failurecurrent currentasasshown shownininFigure Figure8.8.This Thistrend trendcan canbe be triggering easily understood from the preceding discussions. However, when the Ge mole fraction is higher than easily understood from the preceding discussions. However, when the Ge mole fraction is higher easily understood from the preceding discussions. However, when the Ge mole fraction is higher 0.4, the defect density at theatSiGe/Si interface may may degrade the device performance. than 0.4, thedefect defect density atthe theSiGe/Si SiGe/Si interface maydegrade degrade thedevice device performance. than 0.4, the density interface the performance.
TLP Current (mA/μm) TLP Current (mA/μm)
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Figure8. TLPI-V I-Vcurves curvesofofSiGe SiGeS/D S/DTFET TFETwith withdifferent differentGe Gemole molefractions. fractions. Figure TFET with different Ge mole fractions. Figure 8.8.TLP S/D
Dimensions have significantinfluences influences characteristics of protection ESD protection devices. Dimensionshave havesignificant significant influences onon thethe characteristics ESD protection devices. From Dimensions on the characteristics ofofESD devices. From From Figure 9, be itbecan be seen that with aDOP large DOP and SOP value (see 1), the although the Figure can seen that with largeDOP and SOP value (see Figure 1),Figure although thetriggering triggering Figure 9,9,ititcan seen that with aalarge and SOP value (see Figure 1), although triggering voltage is slightly increased, the failure current is significantly increased. This can voltage is slightly increased, the failure current is significantly increased. This can be attributed voltage is slightly increased, the failure current is significantly increased. This can be attributed be toto attributed to two reasons. The increase in device volume offers a better heat dissipation and thus a tworeasons. reasons.The Theincrease increaseinindevice devicevolume volumeoffers offersaabetter betterheat heatdissipation dissipationand andthus thusaareduced reduced two reduced temperature in theIn device. In addition, when DOP and SOP are increased, theresistance series resistance temperature thedevice. device. Inaddition, addition, whenDOP DOP and SOP are increased, theseries series resistance the temperature ininthe when and SOP are increased, the ininthe in the discharge path is increased, hence the ballasting effect suppresses the current crowding along discharge path is increased, hence the ballasting effect suppresses the current crowding along the discharge path is increased, hence the ballasting effect suppresses the current crowding along the the lateral direction [16]. The contour plots of lattice temperature with two DOP and SOP values are lateraldirection direction[16]. [16].The Thecontour contourplots plotsofoflattice latticetemperature temperaturewith withtwo DOP and andSOP SOPvalues valuesare are lateral shown in Figure 10. shown in Figure 10. shown in Figure 10. The gate length can also affect the ESD performance. As listed ininTable Table 1,1,the scaling ininthe the gate Thegate gatelength lengthcan canalso alsoaffect affectthe theESD ESDperformance. performance.As Aslisted listedin Table1, thescaling scalingin thegate gate The the length reduces the triggering voltage and the failure current ofofthe the TFET. The former can be attributed lengthreduces reducesthe thetriggering triggeringvoltage voltageand andthe thefailure failurecurrent currentof theTFET. TFET.The Theformer formercan canbe beattributed attributed length to the increase in the lateral electric field, which enhances the reverse biased p-n junction tunneling to the increase in the lateral electric field, which enhances the reverse biased p-n junction tunneling to the increase in the lateral electric field, which enhances the reverse biased p-n junction tunneling and impact ionization [29]. In addition, the increase in spreading resistance may also play a role and impact ionization [29]. In addition, the increase in spreading resistance may also play role and impact ionization [29]. In addition, the increase in spreading resistance may also play[30,31]. aarole However, since thesince gate the isthe grounded, the electric field nearfield the drain/substrate junction junction isjunction strongly [30,31].However, However, since gateisisgrounded, grounded, the electric field nearthe thedrain/substrate drain/substrate [30,31]. gate the electric near isis affected by the gate, and the impact of gate length on the triggering voltage is not very significant [18]. strongly affected by the gate, and the impact of gate length on the triggering voltage is not very strongly affected by the gate, and the impact of gate length on the triggering voltage is not very The failure[18]. current increases with increasing gate length owning tolength the larger size improved significant [18].The The failurecurrent current increaseswith withincreasing increasing gatelength owning thelarger largersize size significant failure increases gate owning totoand the conduction uniformity. and improved conduction uniformity. and improved conduction uniformity.
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Figure TLPI-V I-Vcurves curvesofofSiGe SiGeS/D S/DTFET TFETwith withdifferent differentSOP SOPand andDOP DOPvalues. values. Figure 9. TFET with different SOP and DOP values. Figure 9.9.TLP S/D
Figure10. 10.Contour Contourplots plotsof latticetemperatures temperaturesin TFETsunder underTLP TLP current density 0.5 mA/μm Figure current density of 0.5 mA/µm Figure 10. Contour plots ofoflattice lattice temperatures ininTFETs TFETs under TLP current density ofof 0.5 mA/μm withdifferent differentDOP/SOP DOP/SOPvalues: values:(a) (a)DOP DOP===SOP SOP===100 100nm nmand and(b) (b)DOP DOP===SOP SOP===300 with values: (a) DOP SOP 100 nm and (b) DOP SOP 300nm. nm. with different DOP/SOP Table 1.Triggering Triggering voltagesand andfailure failurecurrents currentswith withdifferent differentgate gatelengths. lengths. Table Table 1. 1. Triggering voltages voltages and failure currents with different gate lengths. GateLength Length nm 100nm nm 150nm nm 200nm nm Gate 5050nm 100 150 200 Gate Triggering Length 50 nm 4.06 V 1004.1 nmV 150 nm 200 nm Voltage 4.18 V 4.28 Triggering Voltage 4.06 V 4.1 V 4.18 V 4.28 VV Failure Current 4.06 0.65 mA/μm 0.7 0.7 mA/μm 0.725mA/μm mA/μm 0.75mA/μm mA/μm Triggering Voltage VmA/μm 4.1 V 4.18 V 4.28 V Failure Current 0.65 mA/μm 0.725 0.75 Failure Current 0.65 mA/µm 0.7 mA/µm 0.725 mA/µm 0.75 mA/µm
Theimpact impactofofdrain draindoping dopinglevel levelon onSiGe SiGeS/D S/DTFET’s TFET’sESD ESDI-V I-Vcharacteristic characteristicisisshown shownininFigure Figure The 11. It can be observed that with the increase in drain doping level, the triggering voltage is reduced. of drain doping levelincrease on SiGeinS/D TFET’s ESDlevel, I-V characteristic is voltage shown in 11. 11. ItThe can impact be observed that with the drain doping the triggering is Figure reduced. can beattributed attributed theenhanced enhanced BTBT, andreduction reduction the critical electric fieldrequired required for ItThis cancan be be observed thattoto with the increase in drain doping level, the triggering voltage is reduced. This the BTBT, and ininthe critical electric field for avalanche breakdown. The failure current slightly increased with theincrease increase drain dopinglevel, level, This can bebreakdown. attributed to the enhanced BTBT, and reduction in thethe critical electric fielddoping required for avalanche The failure current isisslightly increased with inindrain and this is because the reduction in drain voltage results in less Joule heat. It should be mentioned avalanche failure in current slightlyresults increased with the increase in drainbedoping level, and this isbreakdown. because theThe reduction drainisvoltage in less Joule heat. It should mentioned that, since theBTBT BTBT and avalanche generations mainly occur on thedrain drainside, thesource source doping and this is the because the reduction in drain voltagemainly resultsoccur in less Joule heat. Itside, should be mentioned that, since and avalanche generations on the the doping levelsince nearly does not influence thegenerations TFET’sESD ESD characteristics [16]. that, the BTBT and avalanche mainly occur on[16]. the drain side, the source doping level level nearly does not influence the TFET’s characteristics nearly does not influence the TFET’s ESD characteristics [16].
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Drain Doping Level 19 -3 2×10 cm 19 -3 5×10 cm 20 -3 10 cm
TLP Current (mA/μm)
1.5
1.0
0.5
0.0
0
1
2 3 4 Drain Voltage (V)
5
Figure 11. TLP I-V curves of SiGe S/D S/DTFET TFETwith withdifferent differentGe Gemole molefractions. fractions.
5. Conclusions 5. Conclusions In this paper, a new grounded-gate TFET with SiGe source and drain regions was proposed and In this paper, a new grounded-gate TFET with SiGe source and drain regions was proposed and its ESD characteristics were investigated using TCAD simulations. Compared to the conventional Si its ESD characteristics were investigated using TCAD simulations. Compared to the conventional Si TFET, the triggering voltage of the SiGe S/D TFET is reduced because the SiGe regions offer a high TFET, the triggering voltage of the SiGe S/D TFET is reduced because the SiGe regions offer a high BTBT probability, a higher impact ionization coefficient, and a higher electric field due to the SiGe/Si BTBT probability, a higher impact ionization coefficient, and a higher electric field due to the SiGe/Si heterostructure. The failure current of the SiGe S/D TFET is also increased due to the combination heterostructure. The failure current of the SiGe S/D TFET is also increased due to the combination of of a lower triggering voltage and a smaller Joule heat resulting from a higher hole mobility in SiGe. a lower triggering voltage and a smaller Joule heat resulting from a higher hole mobility in SiGe. This This enhanced ESD performance will be beneficial for constructing robust TFET-based ESD protection enhanced ESD performance will be beneficial for constructing robust TFET-based ESD protection networks in the future. networks in the future. Author contributions: Contributions:Z.Y. Z.Y.provided providedthe theconcept, concept,designed designedthe thestructures, structures,performed performed the the simulations, simulations, and and wrote wrote the manuscript. All authors discussed the results, read, and approved the final manuscript. the manuscript. All authors discussed the results, read, and approved the final manuscript. Funding: This work was funded by the project of National Natural Science Foundation of China (grant number 61804123),This and work in partwas by funded the projects of the China Postdoctoral Science Foundation (grantofnumber 2017M623211), Funding: by the project of National Natural Science Foundation China (grant number Postdoctoral Science Foundation of Shaanxi Province, China (grant number 2017BSHEDZZ31), and Key Project 61804123), and in part by the projects of the China Postdoctoral Science Foundation (grant number 2017M623211), Foundation of the Education Department of Shaanxi Province, China (grant number 18JS082). Postdoctoral Science Foundation of Shaanxi Province, China (grant number 2017BSHEDZZ31), and Key Project Conflicts of of Interest: The authors declare of noShaanxi conflictsProvince, of interest. Foundation the Education Department China (grant number 18JS082).
Conflicts of Interest: The authors declare no conflicts of interest.
References
References 1. Cristoloveanu, S.; Wan, J.; Zaslavsky, A. A review of sharp switching devices for ultra-low power applications. 1. 2. 2. 3. 3. 4. 4. 5. 5. 6. 6. 7.
7.
8. 9.
IEEE J. Electron Devices Soc. 2016, 4, 215–226. [CrossRef] Cristoloveanu, S.; Wan, J.; Zaslavsky, A. A review of sharp switching devices for ultra-low power Hueting, R.J.E. The Balancing Act in Ferroelectric Transistors: How Hard Can It Be? Micromachines 2018, applications. IEEE J. Electron Devices Soc. 2016, 4, 215–226. 9, 582. [CrossRef] Hueting, R.J.E. The Balancing Act in Ferroelectric Transistors: How Hard Can It Be? Micromachines 2018, 9, Seabaugh, A.; Zhang, Q. Low-voltage tunnel transistors for beyond CMOS logic. Proc. IEEE 2010, 98, 582. 2095–2110. [CrossRef] Seabaugh, A.; Zhang, Q. Low-voltage tunnel transistors for beyond CMOS logic. Proc. IEEE 2010, 98, 2095– Ionescu, A.M.; Riel, H. Tunnel field-effect transistors as energy efficient electronic switches. Nature 2011, 479, 2110. 329–337. [CrossRef] Ionescu, A.M.; Riel, H. Tunnel field-effect transistors as energy efficient electronic switches. Nature 2011, Chen, S.; Wang, S.; Liu, H.; Li, W.; Wang, Q.; Wang, X. Symmetric U-Shaped Gate Tunnel Field-Effect 479, 329–337. Transistor. IEEE Trans. Electron Devices 2017, 64, 1343–1349. [CrossRef] Chen, S.; Wang, S.; Liu, H.; Li, W.; Wang, Q.; Wang, X. Symmetric U-Shaped Gate Tunnel Field-Effect Chen, Y.-N.; Fan, M.-L.; Hu, P.-H.; Su, P.; Chuang, C.-T. Evaluation of stability, performance of ultra-low Transistor. IEEE Trans. Electron Devices 2017, 64, 1343–1349. voltage MOSFET, TFET, and mixed TFET-MOSFET SRAM cell with write-assist circuits. IEEE J. Emerg. Sel. Chen, Y.-N.; Fan, M.-L.; Hu, P.-H.; Su, P.; Chuang, C.-T. Evaluation of stability, performance of ultra-low Topic Circuits Syst. 2014, 4, 389–399. [CrossRef] voltage MOSFET, TFET, and mixed TFET-MOSFET SRAM cell with write-assist circuits. IEEE J. Emerg. Sel. Strangio, S.; Palestri, P.; Esseni, D.; Selmi, L.; Crupi, F.; Richter, S.; Zhao, Q.T.; Mantl, S. Impact of TFET Topic Circuits Syst. 2014, 4, 389–399. unidirectionality and ambipolarity on the performance of 6T SRAM cells. IEEE J. Electron Devices Soc. 2015, Strangio, S.; Palestri, P.; Esseni, D.; Selmi, L.; Crupi, F.; Richter, S.; Zhao, Q.T.; Mantl, S. Impact of TFET 3, 223–232. [CrossRef] unidirectionality and ambipolarity on the performance of 6T SRAM cells. IEEE J. Electron Devices Soc. 2015, 3, 223–232. Lanuzza, M.; Strangio, S.; Crupi, F.; Palestri, P.; Esseni, D. Mixed tunnel-FET/MOSFET level shifters: A new proposal to extend the tunnel-FET application domain. IEEE Trans. Electron Devices 2015, 62, 3973–3979. Sithanandam, R.; Kumar, M.J. A new on-chip ESD strategy using TFETs-TCAD based device and network
Micromachines 2018, 9, 657
8.
9. 10. 11.
12.
13.
14. 15.
16. 17. 18.
19.
20. 21.
22. 23. 24. 25. 26. 27.
28.
9 of 10
Lanuzza, M.; Strangio, S.; Crupi, F.; Palestri, P.; Esseni, D. Mixed tunnel-FET/MOSFET level shifters: A new proposal to extend the tunnel-FET application domain. IEEE Trans. Electron Devices 2015, 62, 3973–3979. [CrossRef] Sithanandam, R.; Kumar, M.J. A new on-chip ESD strategy using TFETs-TCAD based device and network simulations. IEEE J. Electron Devices Soc. 2018, 6, 298–308. [CrossRef] Liou, J.J. Challenges of designing electrostatic discharge (ESD) protection in modern and emerging CMOS technologies. Proc. ISNE 2014, 4, 1–3. Galy, P. ElectroStatic Discharge (ESD) one real life event: Physical impact and protection challenges in advanced CMOS technologies. In Proceedings of the 2014 International Semiconductor Conference (CAS), Sinaia, Romania, 13–15 October 2014; pp. 31–34. Boschke, R.; Linten, D.; Hellings, G.; Chen, S.-H.; Scholz, M.; Mitard, J.; Witters, L.; Collaert, N.; Thean, A.; Groeseneken, G. ESD characterization of diodes and ggMOS in Germanium FinFET technologies. In Proceedings of the 2015 37th Electrical Overstress/Electrostatic Discharge Symposium (EOS/ESD), Reno, NV, USA, 27 September–2 October 2015; pp. 1–9. Boschke, R.; Chen, S.-H.; Scholz, M.; Hellings, G.; Linten, D.; Witters, L.; Collaert, N.; Groeseneken, G. ESD Ballasting of SiGe FinFET ggNMOS devices. In Proceedings of the 2017 IEEE International Reliability Physics Symposium (IRPS), Monterey, CA, USA, 2–6 April 2017. Lin, C.-Y.; Wu, Y.-H.; Ker, M.-D. Low-leakage and low-trigger-voltage SCR device for ESD protection in 28-nm high-k metal gate CMOS process. IEEE Electron Device Lett. 2016, 37, 1387–1389. [CrossRef] Galy, P.; Athanasiou, S. Preliminary results on TFET-gated diode in thin silicon film for IO design & ESD protection in 28 nm UTBB FD-SOI CMOS technology. In Proceedings of the 2016 International Conference on IC Design and Technology (ICICDT), Ho Chi Minh City, Vietnam, 27–29 June 2016; pp. 1–4. Kranthi, N.K.; Shrivastava, M. ESD behavior of tunnel FET devices. IEEE Trans. Electron Devices 2017, 64, 28–36. [CrossRef] Yang, Z.; Zhang, Y.; Yang, Y.; Yu, N. Investigation of the double current path phenomenon in gate-grounded tunnel FET. IEEE Electron Device Lett. 2018, 39, 103–106. [CrossRef] Yang, Z.; Yu, N.; Liou, J.J. Impact of the gate structure on ESD characteristic of tunnel field-effect transistors. In Proceedings of the 2018 7th International Symposium on Next Generation Electronics (ISNE), Taipei, Taiwan, 7–9 May 2018; pp. 1–4. Mayer, F.; Le Royer, C.; Damlencourt, J.-F.; Romanjek, K.; Andrieu, F.; Tabone, C.; Previtali, B.; Deleonibus, S. Impact of SOI, Si1−x Gex OI and GeOI substrates on CMOS compatible tunnel FET performance. In Proceedings of the 2008 IEEE International Electron Devices Meeting, San Francisco, CA, USA, 15–17 December 2008; pp. 1–5. Kim, S.H.; Agarwal, S.; Jacobson, Z.A.; Matheu, P.; Hu, C.; Liu, T.-J.K. Tunnel field effect transistor with raised germanium source. IEEE Electron Device Lett. 2010, 31, 1107–1109. [CrossRef] Schmidt, M.; Schäfer, A.; Minamisawa, R.A.; Buca, D.; Trellenkamp, S.; Hartmann, J.-M.; Zhao, Q.-T.; Mantl, S. Line and point tunneling in scaled Si/SiGe heterostructure TFETs. IEEE Electron Device Lett. 2014, 35, 699–701. [CrossRef] Wang, W.; Wang, P.F.; Zhang, C.M.; Lin, X.; Liu, X.Y.; Sun, Q.Q.; Zhou, P.; Zhang, D.W. Design of U-shape channel tunnel FETs with SiGe source regions. IEEE Trans. Electron Devices 2014, 61, 193–197. [CrossRef] Sithanandam, R.; Kumar, M.J. A novel cascade-free 5-V ESD clamp using I-MOS: Proposal and analysis. IEEE Trans. Device Mater. Reliab. 2016, 16, 200–207. [CrossRef] Sze, S.M. Physics of Semiconductor Devices, 3rd ed.; Wiley: New York, NY, USA, 2006; pp. 39–41. Sarkar, D.; Singh, N.; Banerjee, K. A novel enhanced electric-field impact-ionization MOS transistor. IEEE Electron Device Lett. 2010, 31, 1175–1177. [CrossRef] Synopsys. User Manual, Ver. I-2013.03, Synopsys TCAD Sentaurus; Synopsys: San Jose, CA, USA, 2013. Shrivastava, M.; Agrawal, M.; Mahajan, S.; Gossner, H.; Schulz, T.; Kumar Sharma, D.; Rao, V.P. Physical insight toward heat transport and an improved electrothermal modeling framework for FinFET architectures. IEEE Trans. Electron Devices 2012, 59, 1353–1363. [CrossRef] Aksamija, Z.; Knezevic, I. Reduced thermal conductivity in SiGe alloy-based superlattices for thermoelectric applications. In Proceedings of the International Silicon-Germanium Technology and Device Meeting, Berkeley, CA, USA, 4–6 June 2012; pp. 1–2.
Micromachines 2018, 9, 657
29.
30.
31.
10 of 10
Thijs, S.; Griffoni, A.; Linten, D.; Chen, S.-H.; Hoffmann, T.; Groeseneken, G. On gated diodes for ESD protection in bulk FinFET CMOS technology. In Proceedings of the EOS/ESD Symposium Proceedings, Anaheim, CA, USA, 11–16 September 2011; pp. 1–8. Zhang, X.Y.; Banerjee, K.; Amerasekera, A.; Gupta, V.; Yu, Z.; Dutton, R.W. Process and layout dependent substrate resistance modeling for deep sub-micron ESD protection devices. In Proceedings of the 2000 IEEE International Reliability Physics Symposium Proceedings, San Jose, CA, USA, 10–13 April 2000; pp. 295–303. Griffoni, A.; Thijs, S.; Russ, C.; Trémouilles, D.; Linten, D.; Scholz, M.; Collaert, N.; Witters, L.; Meneghesso, G.; Groeseneken, G. Next generation bulk FinFET devices and their benefits for ESD robustness. In Proceedings of the 2009 31st EOS/ESD Symposium, Anaheim, CA, USA, 30 August–4 September 2009; pp. 1–10. © 2018 by the authors. Licensee MDPI, Basel, Switzerland. This article is an open access article distributed under the terms and conditions of the Creative Commons Attribution (CC BY) license (http://creativecommons.org/licenses/by/4.0/).
