INSTRUMENTATION DESIGN FOR CROSS-CORRELATION ...

July 15, 2010 11:40 WSPC/S0219-4775 167-FNL S021947751000023X

Fluctuation and Noise Letters Vol. 9, No. 3 (2010) 313–322 c World Scientific Publishing Company
DOI: 10.1142/S021947751000023X

INSTRUMENTATION DESIGN FOR CROSS-CORRELATION MEASUREMENTS BETWEEN GATE AND DRAIN LOW FREQUENCY NOISE IN MOSFETS

G. GIUSI and F. CRUPI DEIS, University of Calabria, Via Pietro Bucci 42C 87030 Arcavacata di Rende (CS), Italy C. CIOFI DFMTFA and INFM, University of Messina, Salita Sperone 31 98166 Messina, Italy C. PACE and P. MAGNONE DEIS, University of Calabria, Via Pietro Bucci 42C 87030 Arcavacata di Rende (CS), Italy Received 13 October 2009 Accepted 12 May 2010 Communicated by Peter McClintock A two-channel measurement system suited for the on-wafer characterization of the gate and drain low frequency noise in MOSFETs is presented. Guidelines for designing the preamplifier and the bias stage at the drain and gate terminals are discussed. Results show that, the natural choice of employing transimpedance amplifiers as first preamplifier stage is useful only at the gate side, while it is preferable the use of voltage preamplifiers at the drain side to avoid voltage saturation. A simple prototype which implements the proposed design approach is reported. The system capability is tested through the measurement of the gate noise, the drain noise and the cross-correlation between the two channels in nMOSFETs with ultrathin oxide thickness. Keywords: Low frequency noise; noise measurement; gate noise; drain noise; low noise instrumentation.

1. Introduction Low frequency noise measurements represent one of the most powerful tool to investigate the defect density and the conduction mechanisms in CMOS devices [1–4]. As the size of new generation devices shrinks toward the nanometric scale, the noise level can impact the correct operation even in the case of digital circuits. It is for this reason that there is a strong need for noise characterization systems allowing a fast and reliable evaluation of the noise characteristics of MOSFETs at 313

July 15, 2010 11:40 WSPC/S0219-4775 167-FNL S021947751000023X

314

G. Giusi et al.

the wafer level as part of the normal characterization steps to be performed when developing new devices and technologies. Several measurement systems have been already extensively reported in literature in the past [5–7]. Most of these systems make use of very high cost instrumentation like spectrum analyzers, PLLs, and so on. In this paper we present a measurement system, that it is suitable for the complete low frequency noise characterization of MOSFET devices at wafer level, with the advantage of the very low cost of the used hardware. Because of the relatively high levels of noise to be measured (usually one is interested in the flicker noise component), the reaching of the lowest possible background noise was not the primary goal. Our group already proposed a lot of circuital topologies for the measurement of very low noise levels [8–9]. Therefore, here we moved our efforts toward the attainment of such characteristics as simplicity, high flexibility, low cost, and ease of implementation. Preliminary results demonstrating the effectiveness of the approach we propose are also reported. The remainder of the work is divided as stated in the following. In Sec. 2 (general part) the problem of the bias stage is addressed. In Sec. 2.1 guidelines for the design of the gate preamplifier are discussed. In Sec. 2.2 guidelines for the drain preamplifier are discussed together with the design of a suitable bias stage. In Sec. 3 details about the implementation and experimental results are shown. Finally, in Sec. 4 the conclusions.

2. System Design In the case of the low frequency noise characterization of CMOS devices one is generally interested in the measurement of the noise generated at the gate and at the drain terminals when the device is biased in the linear region of operation [2]. As bias in such conditions is normally obtained by means of two adjustable voltage sources VGS and VDS (see Fig. 1), the most convenient way in order to detect noise would seem to employ a couple of transresistance amplifiers whose input ports are put in series with the input and output loops. This, as we shall demonstrate in the following, is not the best choice in the case of the measurement of the noise generated at the drain terminal. Moreover, the biasing itself is an issue to be carefully addressed in the case of low frequency noise measurement systems. In fact, one would be willing to have adjustable voltage sources for testing the device in different operating conditions. Unfortunately,

VGS

VDS

Fig. 1. Typical bias network for a MOSFET.

July 15, 2010 11:40 WSPC/S0219-4775 167-FNL S021947751000023X

Instrumentation Design for Gate and Drain LFNM

315

IBIAS

VBIAS

TLC071

RL

TLC071

VBIAS

10 µF

10 µF

DUT

(a)

(b)

Fig. 2. Schematics of a low noise voltage source (a) and a low noise current source (b).

standard solid state DA converters as could be used for implementing VDS and VGS are far too noisy to be employed for these applications and the realization of very low noise programmable voltage sources is not an easy task [10]. However, √ if a voltage noise level in the order of few tens of nV / Hz can be tolerated in the frequency range above a few Hz, a quite simple implementation of a low noise programmable voltage can be obtained as in Fig. 2(a). In such a circuit, a noisy programmable voltage source can be used in order to set the desired voltage at the output before to start the measurement. When the switch that connects the biasing voltage to the capacitor is opened, the output voltage is maintained by the input capacitor. It must be noted that the same circuit can be easily transformed in a current source in those cases in which the voltage drop across the DUT is very low with respect to the system supply voltage by using a series resistor RL (Fig. 2(b)). If the voltage drop across the load is small and the equivalent DUT impedance is small compared to the biasing resistance RL , then the current supplied to the DUT is about VBIAS /RL , that is almost independent of the voltage drop across the load, and the additional noise introduced by the biasing resistor is shunted by the DUT impedance itself thus resulting negligible in several cases of interest, as we shall see in the following. 2.1. Design for gate noise measurements Once a programmable voltage source for bias is available, it can be used, in conjunction with a transresistance amplifier, to configure a self-biasing current-to-voltage converter for the gate terminal (see Fig. 3(a)). Note that, because of the virtual ground between the input pins of the operational amplifiers, the gate voltage almost coincides with the voltage at the non-inverting input of the operational amplifier. As discussed in [11], in the virtual short circuit approximation, discarding the noise coming from the bias stage, the equivalent current noise at the input of the transresistance amplifier is given by: Sineq = SiDUT + Sin +

Svn 4kT + , 2 |ZDUT // RR | RR

(1)

July 15, 2010 11:40 WSPC/S0219-4775 167-FNL S021947751000023X

316

G. Giusi et al.

V BIAS RL RR

E DUT E no I DUT

E no

Z DUT R F2

Z DUT V BIAS

(a)

R F1

(b)

Fig. 3. Schematics of a transresistance amplifier with its biasing stage (a) and of a voltage amplifier with its biasing stage (b). IDUT and EDUT represent the equivalent current noise and the equivalent voltage noise genera-tors of the DUT, while ZDUT is its equivalent impedance.

where SiDUT is the current noise generated by the DUT (at the gate of the mosfet in our special case), Sin and Svn represent the PSD of the equivalent input current and voltage noise of the operational amplifier, ZDUT is the equivalent impedance of the DUT (the impedance seen toward the gate in our case), RR is the feedback resistance, k is the Boltzmann constant, and T the absolute temperature. It is apparent that, as the quantity we want to measure is SiDUT , all the other contributions have to be negligible. Sin can be made negligible by selecting an MOSFET input operational amplifier as the TLC070. At the same time, the contribution due to Svn can be made negligible if the impedance of the DUT as well as the feedback resistor is made sufficiently large. In fact, in several cases of interest, the main unwanted noise contribution reduces to the last term in Eq. (1). As the transresistance gain does coincide with RR , the choice to be made is that of selecting the largest possible RR complying with the following limitations: (a) RR must be such that the output of the operational amplifier does not saturate. As both the biasing voltage and the DC current flowing through the DUT do contribute to the output voltage, both contributions must be carefully estimated for a correct selection of RR ; and (b) RR sets the frequency range into which the virtual short circuit approximation holds [11]; moreover for large values of RR , its unavoidable parasitic capacitance usually sets the bandwidth of the system. 2.2. Design for drain noise measurements In principle one could use the very same approach used in the case of the gate source loop for measuring the current noise at the drain. However, in such a case, the equivalent impedance seen toward the drain is in the order, at most, of a few kΩ. Moreover, the current flowing through the drain is in the order of a few mA. Both these conditions make the realization of transresistance amplifier with an acceptably low noise level and sufficient gain quite difficult, due to the problem of

July 15, 2010 11:40 WSPC/S0219-4775 167-FNL S021947751000023X

Instrumentation Design for Gate and Drain LFNM

317

the operational amplifier saturation. In such a case, therefore, it is better to follow a different approach, which consists of employing a voltage amplifier (see Fig. 3(b)). The equivalent input voltage noise is:

2




ZDUT
2 RL



+ Svn + SRF 1 RF 2 , (2) + 4kT RL
Seneq = SeDUT
ZDUT + RL
ZDUT + RL
where SeDUT is the voltage noise generated by the DUT, the second term in Eq. (2) is the noise produced by RL , Svn is the equivalent input voltage noise of the op-amp, and SRF 1RF 2 is the equivalent input noise generated by the feedback resistances and by the equivalent input current noise of the op-amp. This last term can be made negligible by choosing a MOSFET input op-amp (like the TLC070) and by choosing low values for the feedback resistances. Let us note that the choice of RL  |ZDUT |2 has two advantages (a) the DUT is biased by a constant current VBIAS /RL regardless of ZDUT , and (b) the equivalent input voltage noise is only due to the DUT noise and to Svn , that is Seneq ≈ SeDUT + Svn . It is worth noticing that when a transresistance amplifier is used for drain noise measurements, the dominant term in the background noise in Eq. (1) is that due to the preamplifier voltage noise because of the low ZDUT , meaning that the background noise of the voltage amplifier and that of the transresistance amplifier are the same. There are two advantages in using a voltage amplifier instead of a transresistance amplifier in this case. First, the gain and therefore the output voltage of the amplifier are independent on the DUT impedance, which can change significantly with the bias point and with the MOSFET geometry. In fact to have a gain which is independent of the DUT impedance, the open loop gain should be as high as possible. In the case of a transresistance amplifier, the open loop gain is: βA =

ZDUT // ZIN AV , ZDUT // ZIN + ZF

(3)

where ZIN and AV are the input impedance and the voltage gain of the operational amplifier, respectively. In order to have the highest open loop gain, it is required to have |ZDUT //ZIN |  |ZF |. In the case of drain noise measurements we have |ZDUT //ZIN | ≈ |ZDUT |, hence, in order to obtain a high open loop gain, we need |ZDUT |  |ZF |, that is a feedback impedance even lower than the DUT impedance degrading the signal-to-noise ratio (SNR). In the case of gate current noise measurements this problem is not present because the DUT impedance is very high and the feedback impedance cannot be chosen so low to degrade the SNR. Second, it is possible to insert a simple RC high pass filter before the voltage amplifier in order to avoid the saturation of the operational amplifier. In fact in the case of drain noise measurements with a transresistance amplifier, the output DC voltage is VBIAS (1 + RR /RDUT ). Because RR should be chosen as high as possible to increase the SNR, and because RDUT is relatively low (drain impedance), the

July 15, 2010 11:40 WSPC/S0219-4775 167-FNL S021947751000023X

318

G. Giusi et al.

total DC voltage at the output can easily excess the allowed voltage swing of the output stage of the operation amplifier. It is worth noting that this solution is particularly interesting in the case of MOSFET biased in the saturation region, due to the higher drain voltage.

3. System Implementation and Testing Figure 4 depicts the block diagram of the on-wafer measurement system, which consists of a Cascade prober equipped with a Temptronic thermal controller (−65◦ C to 200◦ C) [12], a low noise amplification and biasing stage and a PC-based spectrum analyzer which is a common PC equipped with a high resolution digital acquisition board (National DSA PCI-4451). Particular care should be addressed to the shielding system since the low noise section and the on-wafer station are not in the same box. To avoid coupling with external electromagnetic fields, very short triaxial cables are used to connect components and also the PC-based spectrum analyzer is battery powered to avoid coupling with the power line. The core of the system is the low noise section, which has been enclosed in a metal box placed close to the contacting probes and is battery powered. The schematics of the low noise section is shown in Fig. 5. According to the discussion reported in Sec. 2, it consists of a voltage amplifier with its biasing stage for the drain current noise measurements and a self-biasing transresistance amplifier for the gate current noise measurements. Each low noise programmable voltage source has been implemented by means of a 10-µF capacitor and a TLC2201 MOSFET input operational amplifier. The TLC2201 is characterized by a typical input bias current of 1 pA, and therefore a voltage drift at the output below 0.4 mV/hour is obtained, which is acceptable for noise measurements lasting a few hours. A low pass filter with a cutoff frequency of 100 mHz has been included in the gate bias stage in order to avoid

Low Noise Section

Drain channel ouput

2 channels PC Based Spectrum Analyzer

Gate channel ouput

Shieleded On Wafer Station

Voltage Amplifier & Bias

D TransImpedance Amplifier & Bias

G

DUT

S B

Fig. 4. Block diagram of the presented on-wafer low noise measurement system.

July 15, 2010 11:40 WSPC/S0219-4775 167-FNL S021947751000023X

Instrumentation Design for Gate and Drain LFNM

319

TLC2201

VBIAS

10 µF

RL

Gain Stage High Pass Filter

Gain Stage

TLC2201 TLC2202

Drain Bias Stage 4.7 µF

Drain channel output

300 K :

1K: SW-D

10 K :

100 : 100 :

Transimpedance Preamplifier Stage

D.U.T.

RR

High Pass Filter

Gain Stage

SW-G

TLC070 TLC2202

4.7 µF

Gate channel output

300 K :

10 K : 100 : 330 K : TLC2201

VBIAS

1 µF

330 K :

1 µF

10 µF

Low Pass Filter Gate Bias Stage

Fig. 5. Schematics of the low noise section.

that external interferences, by coupling with the gate bias circuit, might induce additional drain noise. The system allows the synchronous acquisition of the two channels, thus allowing the evaluation not only of the spectrum of the gate current noise and of the drain current noise, but also the evaluation of their crossspectrum. A set of measurements has been performed for testing the prototype of the low frequency noise measurement system we have designed and built. The devices used in this study are nMOSFETs with poly-Si gate, with gate length L of 1 µm and with gate width W of 10 µm. The gate dielectrics consists of a 1.5-nm layer of SiON. The gate and the drain current power spectral density at different gate bias are reported in Figs. 6 and 7, respectively. We have evaluated the drain current fluctuations by dividing the drain voltage fluctuations by the channel resistance, since the MOSFETs have been biased into the linear region. A typical 1/f γ behavior with γ close to 1 is observed in both cases. For the gate noise measurements we used different values of RR (1 MΩ, 10 MΩ, 100 MΩ) because of the

July 15, 2010 11:40 WSPC/S0219-4775 167-FNL S021947751000023X

320

G. Giusi et al. -17

-21

10

10

VGS from 1.2V to 1.6V -22

10-18

Sid (A2/Hz)

Sig (A2/Hz)

10

10-23 10-24

1/f

100

VDS=40mV 10-19 -20

10

-25

10

101

10-21 0 10

102

VGS-VT from 0.45V to 1.05V

1/f

101

102

Frequency (Hz)

Frequency (Hz) Fig. 6. Power spectral density of the gate current noise in nMOSFET with SiON gate dielectrics at different gate bias.

Fig. 7. Power spectral density of the drain current noise in nMOSFET with SiON gate dielectrics at different gate bias.

different values of the DC gate current. In all cases, for frequencies higher than 1 Hz, the instrumentation noise was dominated by the thermal noise of the feedback resistor that gives rise to an equivalent current background noise at room temperature of 1.66 × 10−26 A2 /Hz (RR = 1 MΩ), 1.66 × 10−27 A2 /Hz (RR = 10 MΩ), and 1.66 × 10−28 A2 /Hz (RR = 100 MΩ). For the drain noise measurements two different values of RL have been utilized, 20 kΩ or 50 kΩ. In both cases we ensured that the biasing resistance was much greater than the MOSFET channel one, so that the DC drain current was fixed by the ratio VBIAS /RL . The instrumentation noise was dominated by the equivalent input voltage noise of TLC2201 that was 3.24 × 10−16 V2 /Hz at f = 10 Hz and 6.4 × 10−17 V2 /Hz at f = 1 kHz. The equivalent current background noise can be obtained by dividing the equivalent voltage background noise by the squared channel resistance. In our experiments, in the worst case, the equivalent current background noise was about 9 × 10−22 A2 /Hz at 10 Hz. In Figs. 8 and 9 the results of the cross-correlation measurements are shown. In Fig. 8 the gate and the drain current noise spectra and their cross-spectrum for VGS = 0.8 V and VDS = 40 mV are plotted. In Fig. 8 there is an RTS noise on the gate current spectrum with a corner frequency of ∼ 40 Hz and a flicker noise on the drain current. Figure 9 shows the absolute value of the cross-correlation coefficient defined as: |Sidig | , C= Sid Sig

(4)

with Sidig the cross-noise spectrum between drain and gate [13]. The crosscorrelation coefficient gives us a measure of the correlation between the fluctuations produced on the two currents by the activity of the charge traps, situated in the gate dielectrics and/or at the oxide/semiconductor interface. A clear notch at the corner frequency of the gate Lorentzian component is observed.

July 15, 2010 11:40 WSPC/S0219-4775 167-FNL S021947751000023X

PSD (A2/Hz)

10-19

Cross-correlation coefficient

Instrumentation Design for Gate and Drain LFNM

Drain Spectrum

10-21 10-23 10-25 10-27 0 10

Cross-Spectrum Gate Spectrum 101

102

103

Frequency (Hz) Fig. 8. Power spectral density of the gate and the drain noise and their cross-spectrum in nMOSFET at VGS = 0.8 V and VDS = 40 mV.

321

100

-1

10

10-2

10-3 0 10

1

10

2

10

3

10

Frequency (Hz) Fig. 9. Cross-correlation coefficient as a function of the frequency corresponding to the spectra of Fig. 8.

4. Conclusions In this work we have presented a two-channel on-wafer noise measurement system suited for the low frequency characterization of the gate and the drain noise in MOSFETs. We have provided the guidelines for designing the preamplifier and the bias stage at the drain and gate terminals. Discussion concluded that at the gate side it is preferable to use a transimpedance preamplifier due to the relatively high gate impedance. At the drain side it is preferable to use a voltage preamplifier in order to maintain an acceptable noise level and to avoid voltage saturation. The system performances have been tested through measurements of the gate and drain current noise spectra and their cross-spectrum in nMOSFETs with ultrathin oxide. Acknowledgments The authors wish to thank Prof. Guido Groeseneken and Dr. Stefan De Gendt from IMEC for providing test devices. References [1] A. Van der Ziel, Noise: Sources, Characterization, Measurement (Englewood Cliffs, NJ, Prentice-Hall, 1970), p. 54. [2] E. Simoen and C. Claeys, On the flicker noise in submicron silicon MOSFETs, SolidState Electron. 43 (1999) 865–882. [3] G. Giusi, N. Donato, C. Ciofi and F. Crupi, A new technique for extracting the mosfet threshold voltage using noise measurements, Fluct. Noise Lett. 4 (2004) 643–649. [4] G. Giusi, F. Crupi, C. Pace, C. Ciofi and G. Groeseneken, A comparative study of drain and gate low frequency noise in nMOSFETs with hafnium based gate dielectrics, IEEE Trans. Electron Devices 53(4) (2006) 823–828. [5] G. Festa and B. Neri, Thermally regulated low-noise, wideband, I/V converter, using Peltier heat pumps, IEEE Trans. Instrum. Meas. 43(6) (1994) 900–905. [6] Chun-Yu Chen and Chieh-Hsiung Kuan, Design and calibration of a noise measurement system, IEEE Trans. Instrum. Meas. 49(1) (2000) 77–82.

July 15, 2010 11:40 WSPC/S0219-4775 167-FNL S021947751000023X

322

G. Giusi et al.

[7] A. Blaum, O. Pilloud, G. Scalea, J. Victory and F. Sischka, A new robust on-wafer 1/f noise measurement and characterization system, in Proc. 2001 Int. Conf. Microelectronic Test Struct. ICMTS (Kobe, Japan, 2001), pp. 125–130. [8] C. Ciofi, G. Scandurra, R. Merlino, G. Cannat` a and G. Giusi, A new correlation method for high sensitivity current noise measurements, Rev. Sci. Instrum. 78 (2007) 114702. [9] G. Giusi, F. Crupi and C. Pace, Ultra sensitive low noise voltage amplifier for spectral analysis, Rev. Sci. Instrum. 79 (2008) 084701. [10] C. Pace, C. Ciofi and F. Crupi, Very low-noise, high-accuracy programmable voltage reference, IEEE Trans. Instrum. Meas. 52(4) (2003) 1251–1254. [11] C. Ciofi, F. Crupi, C. Pace and G. Scandurra, Improved trade-off between noise and bandwidth in op-amp based transimpedance amplifier, IMTC Conf. Proc. 3 (2004) 1990–1993. [12] A. Lord, Cascade microtech, On-wafer 1/f Noise Measurements, Agilent RF Modeling and Simulation Workshop (Lausanne, Switzerland, 2000). [13] J. Lee and G. Bosman, Comprehensive noise performance of ultrathin oxide MOSFETs at low frequencies, Solid-State Electron. 48 (2004) 61–71.