USG/FSG stack at final ILD layers in order to prevent moisture penetration to underlying SiLK TM and improve mechanical properties (1). In this paper, the ...
Interconnect Mechanical Reliability with Low κDielectric as Final ILD Cindy Goldberg, Lei Mercado*, Stanley Filipiak, Stephen Crown Motorola Advanced Products Research and Development Laboratories, Austin, TX 78703 * Motorola Final Manufacturing Technology Center, Tempe, AZ 85284 Abstract The use of low κ materials as the final intralayer dielectric (ILD) layer can impact the integrity of edge seals, blown fuses, and even the interface integrity at lower levels. Furthermore, the influence of the final ILD on lower levels depends on the total number of metal levels in the product. This paper addresses the role of final ILD in both environmental and package reliability, and the use of predictive modeling of mechanical reliability. Introduction The transition to continually lower dielectric constant materials has been accompanied by decreasing elastic moduli, hardness, and interfacial adhesion. Although CMP compatibility may be the first manifestation of mechanical property scaling, the ability to withstand packaging stresses and lifetime testing is critical to successful integration of low k materials. Both wirebond and C4 packaging methods involve thermal and mechanical stresses on the die. Additionally, packaging and assembly result in interfaces exposed to moisture. Even interfaces strong enough to withstand CMP, may delaminate upon exposure to the stresses of packaging. The selection of dielectric material for final ILD can impact both package reliability and lifetime reliability of a semiconductor device. For SiLK integration, Goldblatt, et al., used a USG/FSG stack at final ILD layers in order to prevent moisture penetration to underlying SiLK TM and improve mechanical properties ( 1). In this paper, the results of low k integration at final ILD is presented. Predictive modeling based on fracture mechanics is used to predict the impact of modulating dielectric and interface properties on mechanical reliability. It is shown that the choice of dielectric materials used at final ILD can influence mechanical reliability at all metal levels. Environmental Stress Testing FSG materials have shown interface instability upon exposure to moisture, with free fluorine migrating to interfaces upon atmospheric exposure and subsequent thermal cycling ( 2,3,4).
The use of FSG was compared to undoped SiO 2 and a bilayer FSG/SiO 2 stack at final ILD (with FSG used at lower levels for both splits), with both sets of die packaged, and exposed to lifetime testing. Failures were observed for the FSG split following 96 hours of autoclave testing. The failure mode was found to be associated to delamination along the FSG/SiN interface at final passivation adjacent to the crack stop. Subsequent copper diffusion along that interface resulted in shorting of adjacent lines in the circuit. Figures 1a, b, and c show the delamination from moisture exposure at the crack stop, fuse blow, and scribed edge, respectively. The use of the FSG/SiO 2 stack prevents autoclave induced delamination at the crack stop, but not at blown fuses, because the fuse blow must penetrate into the via dielectric, whereas the crack stop penetrates only the surface of the final ILD.
(a)
FSG/PEN interface
(b)
(c)
Figure 1 FSG delamination following autoclave (a) along FSG/PEN interface at crack stop, (b) FSG/PEN interface at blown fuse, and (c) along various interfaces emanating at the diced edge. It should be noted that for the FSG used, post-autoclave delamination is observed only when the FSG/PEN interface is directly exposed (e.g. along an etched or scribed edge). This observation is applicable to other low k materials which exhibit a degradation in interface adhesion strength upon moisture exposure. Various classes of low-k materials exhibit moisture-sensitive interface adhesion strength. Package Stress Testing Wirebonding of die with FSG at final ILD produces comparable results to environmental testing. The splits containing FSG or FSG/SiO 2 stacks are susceptible to delamination at the interface between the interlayer FSG and overlying metal barrier in the bond pad, depending on wirebonding conditions. Wirebonding with other low κ materials at final ILD have also shown interface reliability issues depending on die attach and wirebond conditions.
driving force exceeds the interface adhesion strength. The test structure is embedded in a flipchip test vehicle with 360 I/O’s at 225-µm pitch. The substrate size is 25 x 25 mm. The die attach temperature was 220 o C. The multilevel, multi-scale submodeling technique was used, as shown in Fig. 3. 5 Four levels of global models and submodels had to be used to capture the global impact on the low-k structures. After the die-attach process, the under-bump structure at the outermost bump was found to have the highest stresses. Under the outer edge of the bump, the low-k stack was subjected to combined tensile and shear load, which acted as a driving force for the low-k stack delamination. 25mm
4 1
package
2 3
bump
Figure 3 Multi-Level, Multi-Scale Submodeling Technique For the case of a four metal level SiCOH/PEN integration, the crack driving force at the SiCOH/PEN interface is shown at each metal level, as a function of whether SiO 2 or SiCOH is used as the final ILD, in Figure 4. The crack driving force at the lower levels increases by 46115% when SiCOH is used at final ILD instead of SiO2 . 1.2
Normalized G
1 0.8 TEOS in LM
0.6
SiCOH in LM
0.4 0.2 0
Figure 2 Delamination along FSG/barrier interface upon wirebonding, when FSG is used as final ILD. Finite Element Simulation An interface fracture mechanics-based approach was used to predict interface delamination associated with flip-chip packaging steps of dieattach. (5). Delamination will occur when the crack
LM
M3
M2
M1
Figure 4 Simulated crack driving force at the SiCOH/SiN interfaces as a function of final ILD. This influence of the final ILD on lower levels was further modeled as a function of the total number of metal levels. In upper layers, the delamination force is 20-40% higher in an 8-layer
stack as compared to a 4-layer stack. The crack driving force from package stress decreases from the upper levels to the lower levels. At lower metal levels, an 8-layer stack has a slightly lower crack driving force compared to a 4-level stack due to the higher number of softer layers on top acting as a stress buffer. The optimal integration in terms of mechanical reliability is to use SiO 2 as both the final intra- and inter-layer dielectric. However, the use of an ILD with κ~4 rather than κ~2-3 can significantly impact RC delay. Capacitancesensitive interconnect speed paths can be designed to accommodate the higher capacitance at last metal. Fuse Integrity As previously mentioned, blown fuses can provide a pathway for moisture penetration into the die. The processes for forming and blowing fuses are also significantly impacted by the choice of dielectric material at final ILD. Figure 5 shows significant damage emanating from blown fuses embedded in low k dielectric when laser conditions are not optimized. When this damage extends to adjacent fuses or circuitry, device failure can result.
Figure 5 Top-down image of blown fuses embedded in low κ dielectric with unoptimized laser conditions. Laser conditions must be optimized for compatibility with low k dielectrics. The challenge is to provide adequate energy to ensure that the fuse is completely blown without damaging the adjacent dielectric. As described earlier for environmental and package reliability, the use of SiO 2 at final intra- and inter-layer dielectric is also optimal for fuse blow reliability.
Conclusions The choice of dielectric material at final ILD has a significant impact on both lifetime and package reliability of low k devices. Interface reliability at lower levels is influenced by the final ILD properties, and the total number of metal levels. The optimal integration is to use an undoped oxide as both the final intra- and inter-layer dielectric. Predictive modeling can be used to predict the effect of modulating interface and bulk dielectric properties for various interconnect designs and package integrations. Acknowledgements The authors would like to acknowledge the tremendous support from the Physical Analysis Laboratory of the Dan Noble Center. References (1) Goldblatt, R.D., et al. (2000). A High Performance 0.13µm Copper BEOL Technology with Low-k Dielectric. IITC 2000, pp.261-263. (2) Tsui, T., Goldberg, C., Braeckelmann, G., Filipiak, S., Ekstrom, B., Lee, J.J., Jackson, E., Herrick, M., Iacoponi, J., Martin, J., Sieloff, D. (2001). The Use of Four-Point Bending Technique for Determining the Strength of Low k Dielectric/Barrier Interface. “Technology and Reliability for Advanced Interconnects and Low-k Dielectrics” Mater. Res. Soc. Proc., Vol. 612, pp.D1.2.1-D1.2.5. (3) Bencher, C., Filipiak, S. (2001). A Comparison of TEOS and Silane Precursors for the Deposition of PE-CVD Fluorine Doped Glass (FSG) for Copper Damascene. Advanced Metallization Conference 2000, 625-628. (4) Wistrom, R., Bomberger, G., Cohen, S., Hazel, S., Lavoie, M., Gambino, J., Poley, D., Dokumaci, O. (2001). Film properties and integration of a variety of FSG films. IITC 2001, 168-170. (5) Mercado, L., Goldberg, C., Kuo, S.-M., “A Simulation Method for Predicting Packaging Mechanical Reliability with Low κ Dielectrics” in press.
