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While the term software radio has meant many things, the ulti- .... test the software development environment via implementation of the ...... a freelance journalist.
TOPICS IN SOFTWARE AND DSP IN RADIO

A PC-Based Software Receiver Using a Novel Front-End Technology Massimiliano Laddomada, Politecnico di Torino Fred Daneshgaran, California State University, Los Angeles Marina Mondin, Politecnico di Torino Ronald M. Hickling, TechnoConcepts, Inc.

This work has been developed in collaboration with EuroConcepts s.r.l (http://www.euroconcepts.it)

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ABSTRACT

INTRODUCTION

Since the software radio concept was introduced, much progress has been made in the past few years in making it a reality. Many softwareradio-based systems have been designed through the development efforts of both commercial and noncommercial organizations. While the term software radio has meant many things, the ultimate goal in software radio has been the realization of an agile radio that can transmit and receive signals at any carrier frequency using any protocol, all of which can be reprogrammed virtually instantaneously. Such a system places great demands on the limits of data converter and processor technologies since it requires real-time disposition of gigasamples of data produced by direct conversion of wireless signals into digital data. From a processing standpoint, the challenge in software radio is to exploit the three basic processor types — fixed architecture processors, FPGAs, and programmable DSPs/ RISCs/CISCs — in such a way as to optimize the three-way trade-offs between speed, power dissipation, and programmability. With respect to the latter characteristic, the issues of highlevel language interfaces, portability, and reprogramming speed must be considered. This article describes the architecture and operation of a PC-based software radio receiver. The development environment is a real-time PCbased platform that allows testing to be done in a simple manner using the main software functionality of a PC. The front-end of the receiver implemented in hardware represents a novel wideband design (bandwidth of up to 100 MHz centered at a carrier frequency of up to 2 GHz) that functionally converts wireless signals directly into a gigasample digital data stream in the receiver (and vice versa in the transmitter). This direct conversion approach shows the greatest promise in realizing the main goal of software radio.

A variety of architectures for designing a software radio (SR) platform have been presented in recent literature [1–4]. The objective of SR is to realize a multimode, multistandard platform for new-generation communications systems that can be reconfigured on the fly. The basic ingredients in the design of SR are hardware such as mixers and analog-to-digital converters (A/Ds), reconfigurable hardware such as field programmable gate arrays (FPGAs) and programmable logic devices (PLDs), digital signal processing (DSP) boards, and general-purpose computers [5, 6]. The embedded software can obviously reside in all the programmable entities used in the design. There are several issues that must be addressed in the design of any SR unit: • Transceiver partition between hardware and programmable hardware entities • Deciding which type of programmable hardware should be used • Interfacing the various entities used in the design of the SR unit for real-time operation of the platform • Ability of the designed architecture to adapt with the evolving communication protocols Any SR architecture attempts to respond to the above issues with the goal of achieving some degree of optimization based on the design objectives of the SR platform. Our vision of the impact of the above issues on performance metrics are: • The first issue impacts how much radio frequency (RF) bandwidth the SR platform can process. • The second issue impacts the degree of programming flexibility in the design, and how much time it would take to reprogram the hardware. • The third issue could impact the choice of hardware architecture given that ultimately

0163-6804/01/$10.00 © 2001 IEEE

IEEE Communications Magazine • August 2001

different components of the design must be able to communicate in real time. • The fourth issue is at the core of the design of any SR system. In the final analysis, if an SR cannot keep up with the evolving communication protocols, what is the point of having one? From a flexibility point of view, it is desirable to push the analog-to-digital boundary as close to the antenna as possible [5]. In our design, we have been able to achieve this via a proprietary highspeed high-resolution A/D and D/A which simultaneously perform precision downconversion of the signal around the carrier all the way down to baseband, and upconversion of the signal from baseband to the carrier frequency, respectively. Such a design is also known as direct conversion or zero-IF design [5, 6]. Furthermore, preferably after the direct conversion front-end one would use a general-purpose workstation platform since it is by far the most flexible programmable hardware that could be used. Indeed, in the prototype design presented in this article we have used precisely such an architecture. The key advantages of such a design are: • Flexibility in implementation of communication protocols using a high-level object-oriented programming paradigm. • Short development time since the objectoriented code fragments can be merged in a variety of ways in order to implement a variety of communication links. • Direct reception and transmission of data in digital form all the way to the antenna. The chipset developed at TechnoConcepts, (i.e., high-speed A/D and D/A chips) plus additional off-the-shelf chips such as frequency synthesizers and low noise amplifiers (LNAs) can be mounted on the antenna mast directly so that digital data at baseband is ported directly to and from the antenna. • Use of software to perform experimentation or virtual instrumentation functions. • Sharing of functional blocks among different air interface standards and ability to upgrade existing blocks or insert new ones on demand in order to improve performance (i.e., to adapt with signal processing advances). • Ability to perform remote system maintenance via software through the use of virtual instrumentation. We should point out that as far as the domain of application of SR platforms is concerned, the SR transceiver can be used in base stations and mobile devices that are not severely power limited, such as those mounted on automobiles (i.e., available power greater than 30 W). These platforms differ in the number of users served, the number of channels and services supported, and, from a more practical point of view, in their dimensions and power consumption. As a general rule, unless the entire processing core can be mapped into silicon directly and merged with the high-speed front-end, currently it is not feasible to implement the proposed SR scheme in handheld severely power-limited environments. Our approach to the design of the SR platform consists of realizing a real-time PC-based receiver using a workstation. This approach has also been adopted by many other researchers

IEEE Communications Magazine • August 2001

working on the problem [1, 2, 7]. The technological advances in high-speed circuits and computer architecture have made workstations very powerful and relatively inexpensive compared to other programmable hardware platforms. The goal of this first phase of the project has been to demonstrate the feasibility of a test platform, for either a mobile or a base station receiver, without power constraints. We should note that such a high-level language software-oriented approach has the advantage that more complex architectures may be adopted in the second phase of the project by simply translating the high-level language code into a low-level language code for programming FPGAs and/or application-specific integrated circuits (ASICs), depending on the platform architecture. The converse is generally not possible. In this sense, the software routines that implement a certain transmission standard are completely portable. The hardware platform architecture may very well utilize parallel and/or pipeline processing in general-purpose microprocessors using embedded systems. The exact mix of parallel and/or pipeline general-purpose processing hardware and reconfigurable hardware in the design is clearly dependent on the domain of application of the SR unit. The high-level language routine represents a floating object overlaying the hardware with portions of the code translated into low-level language code for the reconfigurable logic entities, and the rest of the code being mapped into the general-purpose parallel and/or pipeline processing modules. The rest of the article is organized as follows. We describe the general architecture of the prototype SR receiver platform. We describe the I/O interface, and present the programming environment developed for the SR platform. We present the conclusions, and the final section is devoted to acknowledgments.

Our approach to the design of the SR platform consists of realizing a real-time PC-based receiver using a workstation. This approach has also been adopted by many other researchers working on the problem.

ARCHITECTURE OVERVIEW The SR receiver is based on an 800 MHz Pentium III platform. The operating system adopted for the workstation is Linux because it guarantees maximum accessibility to all computer resources, such as device drivers for input/output (I/O) operations, and because it is shareware. For the design presented in this article, no kernel tuning was performed to prioritize processes, although the workstation was primarily used to run the software receiver code. The system has a 33 MHz peripheral component interconnect (PCI) bus which is 32 bits wide. The receiver functionalities were implemented in software using a high-level programming language. This design approach allows the air interface parameters to be reconfigured simply. The SR prototype is conceived to support realtime Advanced Mobile Phone System (AMPS) and Gaussian ninimum shift keying (GMSK) reception. Since there are many issues related to an SR transmitter whose description would require a separate article, the main part of this article is focused on receiver implementation. The high-level receiver architecture for both reception systems is shown in Fig. 1 and described in detail below. It is composed of two

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RF signal PCI bus, 32 bits wide

I BPF

LNA

Roofing filter

Programmable attenuator

I/O interface

A/D

Digital signal processing unit

Q 14–16 bits PC-based workstation

■ Figure 1. The receiver architecture.

main blocks, an analog radio subsystem and a signal processing subsystem (henceforth referred to as the DSP unit) which communicates with the front-end through an I/O interface. The receiver analog front-end is based on a pair of wideband delta-sigma (∆Σ) converters, one for the in-phase and the other for the quadrature signal components. The converters have an RF bandwidth up to 100 MHz centered around an RF frequency up to 2 GHz and convert the signal from the antenna in a sampled data stream down to baseband (i.e., direct conversion or zero IF design). The output of the A/Ds subsequently feeds the workstation via an I/O interface card. This latter functionality will be discussed later, but its main function is to absorb processing jitter due to operation in a general time-shared workstation. The high-speed A/D has a signal-toquantization-noise ratio (SNR) that varies depending on the oversampling factor, as explained below. The block diagram of the SR wideband frontend, which is the first few blocks of the scheme depicted in Fig. 1, highlighting the critical components, is shown in Fig. 2. This figure represents the global architecture of the front-end under development. Portions of this front-end have been built and tested, but at the time of this writing all the components of the front-end have not yet been integrated. The key objectives in the first phase of the development were to verify the functionality of the high-speed A/D and D/A with precision downconversion, resolve interfacing problems with a general-purpose computer platform for real-time operation, and test the software development environment via implementation of the key physical layer functions of AMPS and GSM standards. The basic prerequisite has been real-time transmission and reception of voice and data over the radio link using the physical layer functions of the noted standards implemented in software. For our prototype testing we have used a single-antenna configuration which is sufficient to pick up signals in the 0.8–2.1 GHz band where most cellular telephony applications lie. Generally speaking, antennas and tuned circuits at the front-end are efficient constant Q elements (Q is the quality factor of the tuned resonator). Using present technology, it is very difficult to construct a single antenna element and efficiently couple the received power to the LNAs and transmit power from the power amplifiers

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(PAs) to the antenna over a frequency band ranging several decades. Same argument holds for the design of LNAs and PAs. Hence, from a practical point of view it is essential to have multiple antennas and corresponding analog front-end elements to efficiently receive and transmit signals over a band of frequencies spanning several decades. In the block diagram of Fig. 2, we show highspeed transmit/receive (T/R) switches. This is not meant to be restrictive in any sense, and diplexers could easily be accommodated in the structure. As a matter of practice, efficient means of coupling signal power to the antenna and receiving power from the antenna is only possible if there is sufficient isolation between the transmit and receive ports. This is typically done by either switching between transmit and receive modes, or using simultaneous transmission and reception on two different frequency bands with sufficient separation, using a diplexer. Obviously, we may also employ a combination of the two techniques. In the receive path of Fig. 2 , we show a band selector which essentially switches among the multiple frequency bands allocated by the Federal Communications Commission (FCC) for different applications. The analog–digital conversion beyond this point is performed using the proprietary high-speed A/D which performs precision downconversion of the signal. The signal processing after band selection may be described as follows: •In-phase and quadrature (I and Q) paths are distinct, and are clocked by very precise I and Q clock signals. The clock signals themselves are generated from a frequency synthesizer that generates a signal at twice the center frequency of the band being digitized. A precise phase splitter generating the desired I and Q clock signals follows the frequency synthesizer. The functions of downconversion and phase splitting are embedded in the single-chip A/D. No mixers are needed in the design. The A/D takes as input the output of the LNA and a clocking signal from an external frequency synthesizer, and generates at the output the data stream, which is further filtered in a separate FPGA to generate the digital samples of the downconverted baseband signal. •The bandwidth of the A/D is very large, and usually several frequency channels associated with a given standard are digitized in one shot. In order to separate distinct frequency channels,

IEEE Communications Magazine • August 2001

I-channel ∆Σ ADC and precision downconversion Band selector Multiphase clock

Frequency synthesizer

R T

R

Q-channel ∆Σ ADC and precision downconversion

T

R

Channelizer

Wideband LNAs and RF BPFs

I-channel decimation filter

Q-channel decimation filter

T

Wideband PAs Multiphase clock

Frequency synthesizer

Synthesis filter bank

I-channel ∆Σ DAC and precision upconversion

Q-channel ∆Σ DAC and precision upconversion

■ Figure 2. The global architecture of the front-end. a channelizer (which could be in the form of an analysis filter bank) is used to generate complex data streams corresponding to the samples of the complex envelopes of the signals in different frequency bands. Resampling, rescaling, and phase correction of the digitized waveforms can be performed on either the composite signal just prior to the channelizer, or individual channels after the channelizer. •The combined precision downconversion using a single master clock and subsequent channelization, resampling, rescaling, and phase correction operations essentially allow the front-end to pick up signals associated with different air interfaces. The oversampling factor of the signal is application-dependent, but at the very minimum 5 samples/symbol are generated and subsequently processed. •Channel selection operations and further signal processing are performed after the channelizer but are not shown in the figure for simplicity. The transmit side of Fig. 2 essentially performs the inverse operation to the receive side. Inclusion of the frequency synthesizer and multiphase clock generator in the transmit block diagram allows possible simultaneous operation of the unit in both transmit and receive modes, possibly over two distinct frequency bands and possibly using different antennas.

THE FRONT-END The receiver front-end is powered by ∆Σ data converter technology capable of operating at speeds in excess of 2 GHz. The process of frequency translation is built into the architecture

IEEE Communications Magazine • August 2001

of the A/D. Initial prototype chips have been fabricated using 0.6 µm gallium arsenide (GaAs) metal semiconductor field-effect transistor (MESFET) technology from Vitesse Semiconductor, Inc. Additional chips have been developed using silicon germanium (SiGe) technology, which has the advantage of being able to be fabricated on the same silicon substrate as conventional complementary metal oxide semiconductor (CMOS) FET very large scale integrated (VLSI) circuits (the product is in the beta testing phase and not yet ready for public release). A continuing emphasis in the development of data converters has been achieving high dynamic range. TechnoConcepts has achieved dynamic ranges in excess of 100 dB at low speeds (< 1 MHz) with continuous-time implementations of ∆Σ converters using conventional silicon CMOS technology, and has achieved dynamic ranges of approximately 60 dB at high clock rates (> 500 MHz). The present work is aimed at extending the dynamic range to larger than 80 dB in the near term, ultimately achieving dynamic ranges on the order of 100 dB. Raw dynamic range, achieved without the use of automatic gain control (AGC), is an important factor in the effectiveness of the receiver circuits, since AGC circuits are incapable of alleviating the in-band interference problem. Particularly with wideband receivers, AGC circuits can be triggered by strong in-band signals (in adjacent channels), potentially shutting out a weak signal by suppressing its level to below the noise floor. Thus, in practice, the raw dynamic range amounts to the true operating dynamic range of the receiver.

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The present work DAC

is aimed at extending the dynamic range to larger than 80 dB in the near term, ultimately achieving dynamic ranges on the order of

+AVin

Loop amplifier

Loop filter

Vin

To decimation filter

+

Complementary amplifier

Threshold comparator

Clock signal

-AVin

100 dB. ■ Figure 3. A block diagram of the ∆Σ analog-to-digital converter.

The wideband A/Ds need to cope with a large number of signals coming from different sources and having experienced different transmission effects such as fading and shadowing. Hence, the received carriers are often characterized as having dramatically different RF power. It is this difference that affects the performance requirements of the wideband A/Ds. As an example, consider the practical case in which two carriers are received by a wideband A/D; let us suppose one carrier as blocking (by virtue of its enormously larger power level) and the other as wanted. Moreover, let us assume that P B is the power of the blocking signal and P W the power of the desired signal such that P B » P W. For instance, in order to comply with GSM specifications, the receiver should be able to distinguish a blocking signal with power up to about 85 dB over the useful signal power (i.e., P B ≤ P W + 85 dB , where the two signals are 0.8–1.6 MHz apart). The spurious free dynamic range (SFDR) is an important performance measure used in wideband receivers. It indicates the capacity of the A/D to accurately detect a low-level signal in an environment with strong interference. In particular, it is the ratio between the desired sinusoidal signal power to the peak power of the largest spurious signal in the output spectrum of the A/D. Note that SFDR is different from the SNR because it takes into account the nonlinearity effects and is an additive term that adds to the minimum SNR required for the wanted signal, which is dictated by other system requirements such as the minimum acceptable bit error rate (BER). The required minimum value of SFDR needed could be expressed as P  SFDRmin = 10 log B  + SNRmin .  PX  For the GSM example noted above, the power ratio between blocking and wanted signals results in an increment in A/D resolution with a number of bits equal to about 14. This increment in A/D resolution represents the protection the A/D needs to provide against blocking signals.

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The high-speed A/D has an SNR that varies depending on the oversampling factor, as explained in the next subsection. The precision downconversion is embedded in the chip. Hence, all that is needed to operate the single-chip A/D is an oscillator and power supply. The input to the A/D is the LNA output, and its output is a data stream at oversampling frequency. This stream is subsequently fed to an FPGA that performs decimation filtering with adjustable parameters. The output of this FPGA are the digital samples of the analog signal. The A/D chip has been designed to have a resolution of 14–16 bits (i.e., SNR of 84–96 dB) at the highest sampling rate (up to 2 GHz) for an RF bandwidth of up to 100 MHz. At the time of this writing, we have not completed testing the chip at its performance limits. The SFDR, which is a measure of linearity, is better than 90 dB. For testing of the prototype SR platform we have had great flexibility in trading RF bandwidth for resolution and choice of the center frequency of the carrier. In our testbed, interference could be generated in any number of ways, including: • Distorting the received samples using a channel model implemented in software just before the receiver signal processing chain • Using cordless telephones and cell phones to generate interference

∆Σ CONVERTER ARCHITECTURE

The high-speed ∆Σ modulator A/D with embedded precision downconversion is a classic design with several modifications and integration of critical functions on a single substrate to achieve significant performance improvements over traditional designs. A block diagram of the ∆Σ modulator is shown in Fig. 3. The main features of the design are: •The complementary amplifier provides negatively and positively amplified versions of the input signal to the switching port. Precision downconversion is essentially achieved by commutation and subsequent filtering in the rest of the modulator. Mathematically, this is equivalent to multiplying the incoming signal by a square wave with amplitude ±A at the carrier frequency

IEEE Communications Magazine • August 2001

fc, instead of a sinusoid at the same frequency. A simple expansion of the square wave in its Fourier series would reveal that the operation in the frequency domain is equivalent to scaling and shifting the Fourier transform of the signal around the carrier frequency up and down the frequency axis. The desired shift is the one around DC which can be low-pass filtered. Actually, this filtering and decimation is an inherent part of the ∆Σ architecture which converts the binary stream out of the comparator into digital samples of the downconverted baseband signal. •The A/D resolution is determined by the oversampling factor and loop filter order. More precisely, 1.5, 2.5, 3.5, and 4.5 bits of resolution per octave oversampling ratio are achievable for loop filters from first to fourth order. The commutation frequency is the same as the center frequency of the band to be downconverted to near DC and digitized. As an example, for a second order loop, at a center frequency of 1 GHz, and for an RF bandwidth of 10 MHz around the center frequency, the oversampling ratio is 100 or 6.6 octaves. The resulting resolution is greater than 16 bits, resulting in about 99 dB of raw dynamic range. Downconversion via commutation greatly enhances the dynamic range and allows for precise control over the clocking phase of the I and Q components. The proprietary A/D can achieve a resolution of up to 18 bits for GSM 900 (RF bandwidth of 25 MHz), 16 bits for DCS 1800 (RF bandwidth of 75 MHz), and 17 bits for Universal Mobile Telecommunications System frequency division duplex (UMTS-FDD) (RF bandwidth of 60 MHz) operating at 1900 MHz. •Downconversion of the signal to a frequency near DC but not DC allows for utilization of digital filters to eliminate DC offset effects of the analog components in downstream signal processing stages. •The loop filter is based on simple analog designs greatly enhancing the A/D bandwidth and completely eliminating the need for switched capacitor filters (SCFs). The problem with SCFs is that they cause aliasing and hence interference. Eliminating the SCF, the A/D can use a continuous time filter with lower order, which allows operation of the loop at much higher frequencies. •The A/D uses commutation for downconversion of the RF signal as opposed to subsampling, which requires tremendous precision and femtosecond pulses to achieve high resolution. •All the components of the A/D are integrated on a single substrate using novel circuit solutions, completely avoiding the need to exit the integrated circuit (IC), reducing costs and size, and eliminating the problem of circuit nonidealities. •A novel superlinear commutating amplifier is used at the input stage as the core of the design. •The overall design uses a current steering technique based on GaAs MESFETs and SiGe devices, resulting in constant power dissipation regardless of the center frequency of the signal to be downconverted and digitized.

THE CHANNELIZER The channelizer can be implemented on an FPGA using a standard weighted overlap-add technique [8]. A 32-channel scheme based on a

IEEE Communications Magazine • August 2001

300-tap finite impulse response (FIR) filter has been designed. A decimation factor of 32 has been considered, so the system receives as input the baseband complex envelope of a frequency multiplexed signal containing 32 subchannels, and generates at the output samples of the complex envelopes of the 32 separate channels. For verification of the prototype testbed functionality, a single baseband channel has been processed. In the testing phase, the frequencydivision multiplexed (FDM) channels may contain either AMPS-like or GSM-like signals. Different FIR filters have been designed for the AMPS and GSM cases, in order to meet their air interface specifications, and different A/D sampling rates and baseband processing rates must be used for these two schemes (in particular, baseband processing rates of 1200 ksamples/s and 1015 ksamples/s, respectively, have been obtained, as described below).

Different FIR filters have been designed for the AMPS and GSM cases, in order to meet their air interface specifications, and different A/D sampling rates and baseband

THE AMPS RECEIVER

processing rates

The system allows continuous reception of a frequency modulated (FM) signal containing both an analog component (the voice signal) and a digital component (a data signal containing all the signaling information). The modulated signal has RF bandwidth of 30 kHz. Referring to Fig. 1, the wideband A/D front-end outputs two sample streams at a constant rate, one for the I component and the other for the Q component of the signal around the carrier (i.e., samples of the complex envelope of the information bearing baseband signal). The I and Q samples each have a resolution of 14 bits. This is a sufficient resolution in order to comply with the D-AMPS requirements [9]. The need for high resolution is mainly due to cochannel and adjacent channel interference problems. A common problem in this regard is the existence of a strong interference signal in the vicinity of a weak desired signal on the frequency axis (in-band interference). If the A/D resolution is not sufficiently high, the weak signal gets buried in the quantization noise of the A/D, making its detection practically impossible. The A/D converter has an embedded downconversion system which outputs the samples of the input signal directly in baseband. This approach has the advantage of avoiding the need for rate conversion filters in the succeeding signal processing units. Subsequently, the I/O interface captures the I and Q samples, collecting them in a block of 32bit words. The actual 14+14 useful bits are those with index 3–16 and 19–32, and are later isolated with logical mask operations. The functionality necessary for performing data transfers is embedded in the I/O board. The collected data is subsequently divided into their I and Q components via software, through logic operations such as logical AND and shift acting on bits. The data, grouped in blocks of 32-bit samples by the I/O interface, are transferred to the processor through the 32-bit PCI bus using the direct memory access (DMA) transfer mode. In this way, while the DSP routines are processing the AMPS data stream of the previous data block, a new block of data is transferred to the user space. Note that the signal processing operations are strictly related to I/O, so the former always has a

must be used for these two schemes.

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The choice of processing blocks of data at the time, instead of sample by sample processing, has a basic advantage

block of sampled data to process. This approach guarantees use of the whole PCI bus. The choice of processing blocks of data at a time, instead of sample-by-sample processing, has a basic advantage in that the call of the processing routines is performed only once for each block of data as opposed to once per sample. This way, the overhead time due to function calling is greatly reduced. The same concept also applies to the time required for the I/O interface to transfer data coming from the analog frontend to the user space.

in that the call of

THE GMSK RECEIVER

the processing

The system allows continuous reception of a binary GMSK modulated signal. For this feasibility study, only one channel is processed at baseband by the prototype test platform. The useful signal has a bandwidth of 200 kHz and is centered around a carrier frequency up to 2 GHz. In an actual base station receiver a simple expansion method for processing multiple GSM channels is that of inserting multiple DSP units, each processing one of the channels selected by the channelizer, in order to fully exploit the functional advantages of SR technology. Serial or parallel processing of the data fragments by multiple DSP units can also be foreseen. The I and Q data are 16 bits wide in order to satisfy the dynamic range requirements of the GSM air interface [9]. All I/O data transfers are performed in a manner similar to that of the AMPS demonstrator, with the difference that in this case all 32 bits transferred by the I/O system are useful data bits, and therefore no masking operations are required (further details about data and sample rates are provided later). The GMSK signal samples are then incoherently demodulated and Viterbi decoded via software by the DSP unit. Details on the structure and simulated performance of the baseband processing stage are presented below.

routines are performed only once for each block of data as opposed to once per sample.

THE I/O INTERFACE The main problem that arises using a workstation as the SR platform concerns the rate at which receiver operations are to be performed. For real-time operation, the data flux from the A/D with embedded precision downconversion is constant. However, as noted earlier, since the receiver operation is run in software and is under the control of the Linux kernel, the rate at which data is processed by the workstation is not constant. In order to avoid any kind of jitter due to rate fluctuations for task scheduling and memory management operations, an I/O interface board has been used. This board is a PCI high-speed digital I/O card and consists of 32-bit digital input and output channels. It performs data transfer using bus mastering DMA via a 32bit PCI bus architecture up to a maximum data transfer rate of 80 MHz, obtained with a new release of the board. Use of DMA transfer mode allows the main processor load to be reduced, since the data transfer takes place in the background, while the main processor performs DSP on the previous input data stream. The use of an I/O board eliminates the need for any kind of timing synchronization between the analog front-

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end and the main processor. The I/O board decouples the instantaneous rate at which the analog front-end produces data from the rate at which the previous block of data are processed by the CPU. Continuous data transfer in real-time mode is guaranteed by the double-buffered asynchronous continuous digital input programming scheme. The principle behind this operation mode is to use a circular buffer logically divided into two equal halves. The sampled data are stored starting from the first half of the buffer. Subsequently, when the device starts writing data into the second half, the data in the first half of the buffer is simultaneously transferred into the random access memory (RAM) using DMA. After the board has filled the second half of the circular buffer, the input data are transferred to the first half of the buffer, overwriting the data collected in the previous phase. The buffer length is set before each input transfer starts in order to guarantee real-time operation. The operation rate is chosen so that the DSP execution time in the workstation matches the time in which the I/O device board fills half of the circular buffer (it is also possible to transfer data at a rate less than the capacity of the DSP stage). This condition is a systemlevel constraint and ensures that the signal processing routines always have correct samples to process and that the system does not drop the data incoming from the front-end or change the rate at which the processed samples are transferred to the audio board. With the aim of evaluating the buffer size that meets the real-time constraint, average timing analysis as a function of the buffer size has been conducted on the time required to process the data with the AMPS and GMSK receivers, the time required to transfer data to the speaker, and the average time to transfer data from the receiver front-end to the user space. While the signal processing times for the AMPS and GMSK air interfaces may be deduced from the values shown in Table 2, the time spent transferring the data processed by the software routines to the audio board falls in the range of [0.1175 µs/sample; 0.175 µs/sample] for buffer size in the range of [2000; 20,000] samples, regardless of the adopted air interface. Finally, the average transfer time is a decreasing function of buffer sizes in the range [2000; 20,000 samples], and falls in the range [5.225 µs/sample ;0.625 µs/sample]. The buffer size that matches the real-time constraint is equal to 18,000 samples for the AMPS receiver. All time evaluations were made using C-shell time [10], which guarantees that the whole CPU is used for the application under examination.

THE PROGRAMMING ENVIRONMENT In order to specify the physical layer of the receiver structure, a programming environment has been developed. The environment allows real-time processing of the samples of the signal in a time-driven sample-by-sample or block-byblock fashion. The environment consists of a simple programming language with semantics allowing

IEEE Communications Magazine • August 2001

The simulated

Recovered voice

Low-pass filter

AMPS transmitter allows continuous

Bandpass filter

Hard limiter

FM demodulator

Manchester matched filter

Sampler decision

Recovered data

Xck(t) High-pass filter

Xa(t)

Envelope detector

Tuned resonator

an FM modulated signal containing both an analog

Clock synchronizer

component (the voice signal)

Clock synchronization block Xa(t)

transmission of

Timing generator

Xck(t)

and a digital component (a data signal

■ Figure 4. A block diagram of the AMPS software receiver.

containing all the signaling

direct definition of the system structure, a library of processing blocks, and a general management program. The management program controls the signal flow, while the actual processing is performed by a sequence of processing blocks belonging to the environment library. In the management program, system parameters such as the sampling rate, bit rate, and number of samples per symbol (in case of digital transmission) are defined, and the control variables of various blocks are updated. Even though sample-by-sample processing is possible, it is generally advisable to perform block-by-block operations, with block size equal to half the size of the I/O circular buffer, as described in the previous subsection. The processing blocks may operate with samples of the complex envelope of the narrowband signals, or with real samples of baseband or quasi-baseband signals. For the demonstrator described in this article, two different reception schemes have been considered, demonstrating the possibility of processing both AMPS and GSM-like signals. The specific processing architectures of these two systems are described in the following.

THE SIMULATED AMPS SYSTEM The simulated AMPS transmitter allows continuous transmission of an FM signal containing both an analog component (the voice signal) and a digital component (a data signal containing all signaling information). The voice signal, either acquired through an external acquisition system or synthetically generated, is added to the Manchester modulated data signal with a bit rate of 9 kb/s. The resulting signal is then frequency modulated and transmitted. The modulated signal has RF bandwidth equal to 30 kHz. The receiver architecture is depicted in Fig. 4, and consists of the software processing section. The software processing includes a bandpass filter, hard limiter, and frequency demodulator. The bandpass filter is an 8-pole Butterworth filter with 3 dB bandwidth equal to 30 kHz (in reality, the I and Q signal components are separately low-pass filtered). The hard

IEEE Communications Magazine • August 2001

limiter and frequency demodulator are jointly implemented with a block that directly evaluates the signal’s instantaneous frequency. The voice signal is then recovered by lowpass filtering of the demodulated signal, while the data signal is recovered after matched filtering and sampling. The sampling signal is generated by an intermediate frequency (IF) rectifier clock recovery subsystem composed of an envelope detector, a tuned resonator, and a timing generator. Simulated performance of the AMPS receiver using the developed software blocks in a two-ray mobile environment [11] are reported in Fig. 6. In this case a baseband sampling rate of 1200 ksamples/s has been used, and a single AMPS carrier has been considered. Maximum, minimum, and average processing speed in samples per second of the AMPS receiver are reported in Table 2. A summary of system parameters is presented in Table 1.

information).

THE SIMULATED GSM-LIKE SYSTEM In the GSM-like system, attention was focused on the reception of a binary GMSK modulated signal. The digital data, running at 203 kb/s (corresponding to six out of the eight slots of a GSM frame with overall bit rate of 270 kb/s), are transmitted using GMSK modulation at a center frequency of 875 MHz (nominal). The receiver architecture is depicted in Fig. 5, and consists of the high-speed ∆Σ A/D with embedded precision downconversion and a software processing section. The software processing includes an 8-pole Butterworth bandpass filter with 3 dB bandwidth of 210 kHz, a hard limiter plus frequency demodulator implemented by direct evaluation of the instantaneous frequency, a low-pass filter the output of which is fed to a Viterbi processor whose function is to remove the residual intersymbol interference, and a maximum likelihood (ML) timing estimator providing accurate timing information to the Viterbi processor. The receiver uses 5 samples/symbol and therefore runs at a speed greater than or equal to 203 × 5 = 1015 ksamples/s. Maximum, minimum, and average processing speed in samples per second of the GSM-like receiver are

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Bandpass filter

FM demodulator

Low-pass filter

tiple layers of the protocol stack of modern wireless communication protocols.

Viterbi processor

ACKNOWLEDGMENTS The authors would like to express their gratitude to the reviewers for their valuable comments that improved the quality of the article. The authors wish to thank Paolo Bande, Ilaria Casuccio, Sandro Manni, and Massimiliano Sanna of EuroConcepts, s.r.l. for their support during the development of this work.

ML timing estimator

■ Figure 5. A block diagram of the GSM-like software receiver.

reported in Table 2. Simulated performance of the GMSK receiver in a two-ray mobile environment [11] using the developed software blocks is reported in Fig. 6. The summary of the system parameters are presented in Table 3.

CONCLUSION This article is focused on the design of a very flexible software radio receiver composed essentially of a high-speed, high-precision A/D converter with embedded precision downconversion and a general-purpose computer platform. The aim is to demonstrate the capability of the frontend and the software programming environment, and as a proof of concept demonstration vehicle. The software environment was developed with multi-processing in mind, and the code can be easily fragmented and operated in a sequential pipeline mode. This ability of the software development tool is fundamental in order to achieve the processing speedups needed to support mul-

REFERENCES [1] IEICE Trans. Commun., Special Issue on Software Defined Radio and its Technologies, June 2000. [2] IEEE JSAC, Special Issue on Software Radio, vol. 17, no. 4, Apr. 1999, pp. 591–602. [3] Proc. IST Mobile Commun. Summit 2000, Galway, Ireland, Oct. 2000. [4] Proc. CNIT 12th Tyrrhenian Int’l. Wksp. Digital Commun., Italy, Sept. 2000. [5] J. Mitola, “The Software Radio Architecture,” IEEE Commun. Mag., vol. 33, no. 5, Feb. 1995, pp. 26–38. [6] IEEE Pers. Commun., Special Issue on Software Radio, Aug. 1999. [7] Bonnet et al., “A Software Radio Platform for New Generations of Wireless Communications Systems,” CNIT 12th Tyrrhenian Int’l. Wksp. Digital Commun., Italy, Sept. 2000. [8] R. E. Crochiere and L. R. Rabiner, Multirate Digital Signal Processing, Prentice Hall, 1983. [9] K. C. Zangi and R. D. Koilpillai, “Software Radio Issues in Cellular Base Stations,” IEEE JSAC, vol. 17, no. 4, Apr. 1999, pp. 603–12. [10] T. Turletti, H. J. Bentzen, and D. Tennenhouse, “Toward the Software Realization of a GSM Base Station,” IEEE JSAC, vol. 17, no. 4, Apr. 1999, pp. 603–12. [11] T. S. Rappaport, Wireless Communications, Principles and Practice, Prentice Hall PTR, 1996

BER for the GMSK system

SNRout for the AMPS system

15

100 v= 20 km/h, C/D = –3 dB v= 100km/h, C/D = –10 dB v= 100km/h, C/D = –3 dB

SNR to the output of the receiver (dB)

10

BER

10–1

10–2

5

0

–5

–10 v = 20 km/h, C/D = –10 dB v = 20 km/h, C/D = –3 dB v = 100 km/h, C/D = –10 dB v = 100 km/h, C/D = –3 dB 0

-15 0

10

20 Eb/N0 (dB)

30

0

5

10

15

20

SNR to the input of the receiver (dB)

■ Figure 6. Simulated performance of the AMPS and GMSK software receivers in a two-ray mobile environment. υ is the mobile speed and C/D the power ratio between reflected and direct rays.

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ADDITIONAL READING [1] IEEE Commun. Mag., Special Issue on Software Radio, vol. 37, no. 2, , Feb. 1999. pp. 82–112. [2] E. Buracchini, “The Software Radio Concept,“ IEEE Commun. Mag., no. 9, Sept. 2000, pp. 138–43.

BIOGRAPHIES M A S S I M I L I A N O L A D D O M A D A [M] ([email protected]) received his Master’s degree in electronics engineering from Politecnico di Torino in 1999. Since November 1999 he is attending the Ph.D. program in electrical engineering at the Department of Electronics there. His main interest fields include architecture design and efficient digital signal processing techniques for software radio. Currently he is involved in studying blind equalization techniques for radio mobile channels. He writes for some Italian newspapers as a freelance journalist. FRED DANESHGARAN ([email protected]) received his B.S. degree in electrical and mechanical engineering from California State University, Los Angeles (CSLA) in 1984, an M.S. degree in electrical engineering from CSLA in 1985, and a Ph.D. in electrical engineering from the University of California, Los Angeles (UCLA), in 1992. From 1985 to 1987 he was an instructor in the Department of Electrical and Computer Engineering (ECE) at CSLA. From 1987 to 1993 he was assistant professor, from 1993 to 1996 associate professor, and since 1997 full professor in the ECE Department at CSLA. Since 1989 he has been chair of the communications group of the ECE department at CSLA. Since 1994 he has secured more than $1.3 million in financing for research and development at CLSA in collaboration with others. He has developed fiber optics and nonlinear optics research laboratories with funding from NSF, ONR, and other sources. From 1999 to 2000 he acted as chief scientist for TechnoConcepts, Inc., where he directed the development of a prototype software-defined radio system, managed the hardware and software teams, and orchestrated the entire development process. In 2000 he co-founded EuroConcepts s.r.l., an R&D company specializing in the design of advanced communication links and software radio. Currently, he is acting as chief executive officer and chief technology officer of EuroConcepts s.r.l. In 2000 he founded Quantum Bit Communications, LLC., a consulting firm specializing in wireless communications. In 1996 he acted as an independent lead research consultant operating through Quantum Bit Communications where he worked on the development of algorithms for target detection from compressed data and managed a group of research scientists working on the topic. Since 1992 he has been a research consultant to the TLC group of the EE Department, Politecnico di Torino, Italy, where he has consulted on a variety of projects for both national and European funded contracts, and conducted joint research on wavelets, coded modulation, channel coding, and other topics with members of the Signal Analysis and Simulation (SAS) group. MARINA MONDIN [M] ([email protected]) received a Laurea in ingegneria elettronica (summa cum laude) in 1986, and her Ph.D. in electrical engineering in 1990, both from Politecnico di Torino, Italy. In 1987 she was a recipient of the De Castro scholarship, and she spent the year 1987–1988 as visiting scholar in the Department of Electrical Engineering at UCLA. Since 1990 she has been with the Dipartimento di Elettronica, Politecnico di Torino, where she is currently associate professor. She is a member of the IEEE Communications and Information Theory Societies. Her current interests are in the areas of turbo coding, trellis-coded modulation, simulation of communication systems, application of wavelets to digital communications, and software radio. From 1999 to 2000 she was a senior scientist for TechnoConcepts, Inc., where she directed the software development efforts. In 2000 she co-founded EuroConcepts s.r.l., an R&D company specializing in the design of advanced communication links and software radio. Currently, she is acting as chief operations officer of the company. R ONALD M. H ICKLING received his M.S. degree in electrical engineering from UCLA in 1987. He has more than 20 years experience in design and implementation of integrated circuits related to communications for U.S. defense and

IEEE Communications Magazine • August 2001

Voice bandwidth

4 kHz

Signaling data rate

9 kb/s

RF bandwidth per channel

30 kHz

Cumulative RF bandwidth

> 10 MHz

Number of AMPS carriers tested

One at a time

Interference

Simulated, from cell phone

Carrier frequency

875 MHz (nominal), variable

Receiver clock

2 × 875 MHz (nominal), variable

A/D data rate

1200 ksamples/s

A/D resolution

14 b/sample

LPF type and bandwidth

8-pole Butterworth, 30 kHz (3 dB)

■ Table 1. A summary of system parameters for the AMPS software radio.

Speed (ksamples/s)

Average

Maximum

Minimum

GSM-like receiver

1200

1300

1050

AMPS receiver

1700

1800

1200

■ Table 2. Processing speeds in kilosamples per second for the simulated AMPS and GSM-like systems.

Raw data rate

203 kb/s

RF bandwidth per channel

200 kHz

Cumulative RF bandwidth

> 10 MHz

Number of GSM carriers tested

One at a time

Interference

Simulated, from cell phone

Carrier frequency

875 MHz (nominal), variable

Receiver clock

2 × 875 MHz (nominal), variable

ADC data rate

1050 ksamples/s

ADC resolution

16 b/sample

BPF type and bandwidth

8-pole Butterworth, 210 kHz (3 dB)

Intersymbol interference removal

Viterbi postprocessing

Timing recovery

ML type

■ Table 3. A summary of system parameters for the GSM software radio. commercial contractors. In 1980 he started his career at Hughes Space and Communications Group developing circuits for satellite communications. In 1984 he joined the startup Gigabit Logic as the 36th employee and headed development teams on mixed-signal communication products. As a project manager, he frequently interfaced with customers in defining the requirements for Gigabit’s standard products. He co-founded TechnoConcepts in 1991 and is serving as president and chairman of the board. He has been responsible for securing more than $1.1 million in federal SBIR funds to develop key technology elements of its high-speed integrated circuit products for the communications industry. He has numerous awarded and pending patents, and has published in numerous leading industry journals.

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