Analogic algorithms for optical detection of breaks and short circuits on the layouts of printed circuit boards using CNN Péter Szolgay , Katalin Tömördi + Analogic and Neural Computing Systems Laboratory Computer and Automation Institute, Hungarian Academy of Sciences, P.O.B.63, H-1502 Budapest, Hungary, e-mail:
[email protected] + Image Processing and Neurocomputing Department, Faculty of Engineering, University of Veszprém, Egyetem u. 10, H-8201 Veszprém, Hungary, e-mail:
[email protected]
ABSTRACT: Printed circuit board layout inspection methods are mostly based on local geometric information, therefor they are well suited to the CNN paradigm. Here the detection of two layout errors is considered namely, the breaks in the wires and some kind of short circuits. The designed analogic algorithms to solve the problems above were tested on real life examples using an experimental system based on our CNNHAB digital multiprocessor add-in-board with 1 million cell space and at a speed of 2.0µs/cell/iteration. The break detection algorithm was tested on a 20*22 CNN Universal Machine (CNNUM) chip and the results were compared to other automatic optical inspection systems as well.
1. Introduction There is an increasing demand to reach 100% quality assurance at the PCB production. The faulty samples should be selected and repaired or removed before each critical technological step of production. An Automatic Optical Inspection (AOI) is necessary to avoid the human faults and to meet the requirements of high production rate and of tight tolerances. In addition to these a high speed, high detection accuracy and a low false-alarm rate are required. The main types of AOI techniques are as follows [6], [7]: (i) reference based methods [9], where the PCB samples are compared to a stored correct one , (ii) non-referential methods [10], where the technological rules are checked on the PCB samples, (iii) hybrid methods [7] are combination of the two previous methods. To avoid the alignment and lighting problems a non-referential method was used where the technological rules have to be checked. The layout rule checking of a printed circuit board documentation or a manufactured board is time consuming. The design and manufacturing rule checking of a layout needs mostly local geometric information, it is well suited to the CNN paradigm [1], [2]. The typical layout errors on a PCB artwork film or on a manufactured PCB are as follows: (i) the wire width is smaller than a given value, a wire may even be broken, (ii) the isolation on the layout is smaller than a given value, a short circuit may even be generated, (iii) the break of a pad, (iv) fleck or pinhole on a wire, and (v) the misalignment of the pads to the holes. The detection of the minimal line width violations is a key problem. It can be shown that a lot of layout error detection rules can be transformed to this problem [4]. In the paper two new types of layout errors are considered: breaks and short circuits. For detecting breaks, the basic idea of the algorithm is that a wire has to be terminated in a pad, in a via hole or in another wire [12]. The short circuit detection in a layout is based on global properties. To solve this problem the whole interconnection of a circuit has to be known. CNN is especially efficient in detecting local properties. An analogic algorithm is given to detect some types of short circuits [12]. The places of the ”H shape-type” interconnections will be detected on the layout. Hence, the most frequently occurring short circuits can be detected. Our experimental system consists of our CNN-HAB [3] digital multiprocessor add-in-board with its 1 million cell space and at about a speed of 2.0 µs/cell/iteration, and the input images of a printed circuit board or an artwork film are scanned in by using an HP ScanJet Plus scanner [11]. The point here is to have a scanned grey scale image where the layout figures can be easily identified on the background isolation area. The brake detection algorithm was tested on a 20*22 CNNUM chip [14] by using Prototyping System (CCPS) [13], the results were compared to professional AOI systems [7].
the CNN Chip
In paragraph 2 the details of the break detection analogic algorithm, in paragraph 3 the details of the short circuit detection analogic algorithm are given. In paragraph 4 some experimental results are given with complex real life examples running on the CNN-HAB and some simple test examples running on a CNNUM chip.
2. An analogic algorithm to detect breaks of wires on the layout of printed circuit boards 2.1 Problem formulation and pre-processing The first question is how to define a "break" on a wire. Places, where a wire is not terminated in a pad, in a via hole or in another wire segment (see Figure 1) have to be found. The flowchart of the analogic algorithm is given in Figure 3. to detect the breaks of wires.
Figure 1. Breaks of wires on a layout
The first step is to convert the grey-scale picture into a black and white one. To solve this problem the average, the threshold, or some non-linear filtering templates [5] can be used. This step is common in every CNN based layout error detection algorithm [4]. The next step is to skeletonize the layout image to make the detection phase wire size independent. For our purpose the black-and-white skeletonization [5] is not good enough, firstly because this method peels also the endings of the wire, and we do not find the exact positions of errors , secondly because the endings of the wires after the skeletonization have many different strange shapes. So we tried to find similar templates which, we call "horizontal skeleton" ("horskel") templates, which peel the black pixels only from right or form left of a wire, and so the algorithm finds the horizontal "skeleton" of the objects. This can be seen in Figure 2. for 3-pixel-wide vertical wires.
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Figure 2. a, b Skeletonized elements (b) of typical wire segments (a).
input image (grey scale)
averaging (5 iterations)
Horizontal skeletonization (4*w iterations)
Vertical skeletonization (4*w iterations)
one pixel object removal (8 iterations)
one pixel object removal (8 iterations)
improper ending detection (3 iterations)
improper ending detection (3 iterations)
OR to unify the errors
Image with detected error points
Figure 3. The analogic algorithm of the break detection on a layout with w wire width
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There are two horskel templates. They should be applied sequentially, always feeding the output back to the input before using the next template. The skeletonizing templates are:
⎡0.125 0 0.5⎤ A1 = [3] B1 = ⎢ - 0.5 0.5 0.5⎥ z1 = -1 ⎥ ⎢ ⎢⎣0.125 0 0.5⎥⎦ ⎡0.5 0 0.125⎤ A2 = [ 3] B2 = ⎢0.5 0.5 - 0.5 ⎥ z2 = -1 ⎢ ⎥ ⎢⎣0.5 0 0.125⎥⎦ The different enlarged wire endings of Figure 2. (a) after the skeletonization can be seen in Figure 4.
Figure 4. The different wire endings
For horizontal wires we use the vertical skeleton, "verskel" templates, which are the same as the horskel ones, rotating the templates with 90°. The possible endings are the same as in the vertical case after rotating with 90°.
2.2 How to find the endings on the horizontal and vertical skeletonized layout The next template finds the wire endings on the horizontal skeletonized layout, shown in Figure 4, and the single black pixel objects too. These small objects are to be removed by the "small object removal" template [5] .
⎡- 0.25 - 0.25 - 0.25⎤ A = [ 3] B = ⎢ - 0.5 0.5 - 0.5 ⎥ z = -5.8 ⎥ ⎢ ⎢⎣- 0.25 - 0.25 - 0.25⎥⎦ To find the endings of horizontal wires after vertical skeletonization, this template must be rotated with 90°.
2.3 The results and the limitations of the break detection algorithm To get the final result an OR function was used to collect the errors found on horizontal and vertical skeletonized layout. The pad size should be larger than the maximal line width (this condition is met in practical cases), which means that the pads are larger than one pixel after the skeletonization step. In our wire break detection algorithm the skeletonization step is making the rest of the algorithms independent from the current
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wire size. The actual wire width is a known value, which is used as an input data in our analogic algorithm determining the number of skeletonizing steps.
All the A templates (the feed-back templates) used in the break detection analogic algorithm are centrally symmetric which is a sufficient condition of the stability of the corresponding operations. The template values were computed from the desired steady state of the CNN defined by local rules.
3. An analogic algorithm to detect short circuits of wires on the layout of printed circuit boards
The first question is how to define a "short circuit" between wires. Places where two wires are connected have to be found (originally they must not be connected). The „H” type short circuits of wires (see Figure 5.) can be detected by the following analogic algorithm. The flowchart of the algorithm can be seen in Figure 7.
Figure 5. ”H” type short circuits
3.1 Pre-processing
The first step is to convert the grey-scale picture into a black and white one [5]. The next step is to decide whether there are holes in the picture or not. In the affirmative, first of all we have to fill them in. We use a two-step algorithm, which is much faster than the Hole Filler template [5]. In the first step we fill in the local concavities with the Hollow template (see Figure 6b) [5]. (This template brings those white pixels into black, which are surrounded by black pixels from at least four directions.)This is a template of diffusion type, so the transient must be stopped after a while. The running time depends on the sizes of the holes. Downloading the original image on the input, and the processed one on the initial state, the following template erases the newly appeared black pixels, which have at least one white neighbour (namely none of them is in hole) see Figure 6c.
The template is the following:
⎡0 0 0⎤ ⎡1.1 1.1 1.1⎤ ⎥ ⎢ A = 1.1 1.1 1.1 B = ⎢0 8.8 0⎥ ⎥ ⎢ ⎥ ⎢ ⎢⎣0 0 0⎥⎦ ⎢⎣1.1 1.1 1.1⎥⎦
z=0 a,
b,
c,
Figure 6. The Hole Filling's steps: a, b, c,
5
input image (grey scale)
averaging (5 iterations)
no
Are there holes? yes
Hole filling algorithm (30 iterations)
Vertical peeling (2*4*3 iterations)
Horizontal peeling (2*4*3 iterations)
Smoothing (4*4*3 iterations)
Smoothing (4*4*3 iterations)
detection of possible error points (2 iterations)
detection of possible error points (2 iterations)
OR to get all the possible error points
OR to get all the possible error points
selection of real error points with distance classification (10 iterations)
selection of real error points with distance classification (10 iterations)
OR to unify the errors
Image with detected error points
Figure 7. The analogic algorithm of the short circuit detection
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The algorithm branches here into two parts, the part of the method for ”standing H” shapes between vertical lines is considered in details next and for ”lying H” shapes between horizontal lines all the templates must be rotated by 90°. At the end the two results must be logically OR-ed.
3.2 Peeling When we have the hole free (filled in) layout image, we can start a peeling algorithm. This consists of two types of peelings. First we peel some pixels from the top and from the bottom. The next template peels black pixels, having black pixels below, and white pixels above them, so it peels from the top till the wire is of one pixel wide:
⎡0 0 0⎤ A = ⎢0 2 0⎥ ⎥ ⎢ ⎢⎣0 0 0⎥⎦
⎡0 0.5 0⎤ B = ⎢0 2.5 0⎥ ⎥ ⎢ ⎢⎣0 - 0.5 0⎥⎦
z = -3
Rotating it by 180°, it peels the pixels from the bottom. We need this template to cut the wires where they change direction (elbow or junction), and peel the short circuit connections. See Figure 8.
elbows
junction
before peeling
after peeling
Figure 8. Cutting the wires where they change direction After some cycles of peeling, we use a one-pixel connecting template, because the vertical lines of the scanned images are not really vertical (see e.g. in Figure 9a), and so after these cycles the connection can be cut (Figure 9b). The connecting template is enough here, to eliminate this fault (Figure 9c):
⎡0 0 0⎤ A = ⎢0 2 0⎥ ⎥ ⎢ ⎢⎣0 0 0⎥⎦
⎡0 0 0⎤ B = ⎢1 1 1 ⎥ ⎥ ⎢ ⎢⎣0 0 0⎥⎦
z=1
a,)
b,)
c,)
Figure 9. Operation of the one-pixel connecting template But if the short circuit is on a big area, then we have to
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peel many times, and then if the short circuit is close to the wire endings or elbow, with this template we cut the short circuit wires too, and so we can not find the places of errors. Therefor, in the second peeling phase we use a different peeling template, which does not cut the connections anywhere, only peels the pixels from the top and from the bottom, till the horizontal lines are only one-pixel wide (or sometimes two pixel wide if the wire is not really horizontal, see Figure 10.).
Figure 10. Sometimes there are two-pixel wide wire places after the peeling
The next template peels from the top, and rotating it by 180°, it peels from the bottom:
⎡0 0 0 ⎤ A = ⎢0 2.5 0⎥ ⎥ ⎢ ⎢⎣0 0 0⎥⎦
1.5 0 ⎤ ⎡ 0 B = ⎢ 0.5 2.8 0.5 ⎥ ⎥ ⎢ ⎢⎣- 0.6 - 1.5 - 0.6⎥⎦
z = -1.2
Using these peeling templates, the question is how many times this template has to be used. It depends on the wire width (the first peeling cycles) and the admissible short circuit width (the second peeling cycles). The number of iterations in our examples can be seen in Figure 7.
3.3 Smoothing After the peeling phases, we have to smooth the image, since it consists of parts due to the second peeling, which are to be removed. If the wire endings with different shapes are removed in some cycles, (See Figure 11.) then only the shapes to be detected remain in the picture. The next four templates do this function. They must be used cyclically and the output must be fed back to the input after each iteration.
⎡0.5 1.1 1.1⎤ ⎡0 0 0⎤ ⎥ ⎢ A1 = 0 4 0 B1 = ⎢0.5 4 1.1⎥ z1 = -3.1 ⎥ ⎢ ⎥ ⎢ ⎢⎣0.5 1.1 1.1⎥⎦ ⎢⎣0 0 0⎥⎦
Figure 11. Wire endings with different shapes and the smoothed image
The other three templates can be generated by rotating this template by 90° , 180° and 270°.
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Another problem is that the horizontal lines after the peeling can have places where they are two-pixel wide (see Figure 12.) (when the wires or short circuit lines are wide, not really horizontal, and so only the second peeling algorithm peels at last ) and this disturbs the detection. The next templates make these line segments thinner:
A1 = [14]
0 0 0⎤ ⎡0 0 ⎢0 1.1 1.1 1.1 0⎥ ⎢ ⎥ B1 = ⎢0 1.1 -1.1 -1.1 0⎥ z1 = -1.9 ⎢ ⎥ ⎢0 -1.1 -1.1 1.1 0⎥ ⎢⎣0 1.1 1.1 1.1 0⎥⎦
A2 = [14]
0 0 ⎡0 0 ⎢0 1.1 1.1 1.1 ⎢ B2 = ⎢0 -1.1 -1.1 1.1 ⎢ ⎢0 1.1 -1.1 -1.1 ⎢⎣0 1.1 1.1 1.1
0⎤ 0⎥ ⎥ 0⎥ z2 = -1.9 ⎥ 0⎥ 0⎥⎦
Figure 12. Removing the twopixel wide wire segments
3.4 Detection of possible error points The next step is to detect the possible error points. The shapes in Figure 13. can be detected with the following templates: Template 1
⎡0 0 0⎤ A1 = ⎢0 2 0⎥ ⎢ ⎥ ⎢⎣0 0 0⎥⎦
⎡1.1 - 2.2 0⎤ B1 = ⎢2.2 0.2 0⎥ ⎢ ⎥ ⎢⎣1.1 - 2.2 0⎥⎦
z1 = -7.7
⎡0 - 2.2 1.1⎤ B2 = ⎢0 0.2 2.2⎥ ⎢ ⎥ ⎢⎣0 - 2.2 1.1⎥⎦
z2 = -7.7
Template 2
⎡0 0 0⎤ A2 = ⎢0 2 0⎥ ⎢ ⎥ ⎢⎣0 0 0⎥⎦
The detected points must be logically OR-ed to get all the error points. See Figures 13. and 14. Template 1
Template 2
Figure 13. The shapes of the wires for the error detection templates
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These templates find junctions and sometimes elbows of wide wires (see Figure 14.).
the
In Figure 14. it can be seen that the points signed with ‘a’, ‘b’ and ‘c’ are usually not real error points, only if they are close enough to each other.
c
a b Figure 14. The detected points
3.5 Selection of real error points with distance classification The short circuits detector algorithm may do false alarms due to the fact no node identifiers can be assigned to the different layout objects. It can be seen in Figure 14. that there are detected places which are not short circuits. These detected places are points. We have to classify them, and choose only the points which are real short circuits with high probability. For this purpose, we use distance classification, namely if there are two detected points within a certain distance, then they form short circuit with high probability. Otherwise, they have to be removed. The steps are as follows. First we increase the size of these points with the Increase template [5] till the desired patches reach each other, and then feeding the result to the input with the following diffusion type template which peels the patches from the left and the right.
⎡0 0 0⎤ A = ⎢1.5 1 1.5⎥ ⎢ ⎥ ⎢⎣ 0 0 0 ⎥⎦
⎡0 0 0⎤ B = ⎢0 2 0⎥ ⎢ ⎥ ⎢⎣0 0 0⎥⎦
z = -4.5
Then, after certain number of iterations, the patches which were generated by single points (they have no neighbour points in the given distance) will disappear. So now with the Recall template [5] we can ”recall” the real error points’ patches, and they can be logically AND-ed with the possible error points and in this way, we get the result, the real error points on the PCB. Snapshot of this method can be seen in Figure 15.
a.)
b.)
c.)
d.)
e.)
Figure 15. Distance classification a.) The possible error points b.) The patches generated around a point c.) The patches after peeling d.) After recalling e.) The result
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3.6 The results and the limitations of the short circuit detector analogic algorithm If we run this algorithm for the ”lying H”-s too by using the rotated templates, and using logical OR function we can get all the H type short circuits on a PCB. In our short circuit detection algorithm the peeling steps are making the rest of the algorithms independent from the current wire size. The actual wire width is a known value, which is used as an input data in our analogic algorithm determining the number of the peeling steps. Using the proposed short circuit detection algorithm, that short circuits can be detected only which are generated between the layout objects on the same layer. This means the following case cannot be detected by our short circuit detector algorithm if a via hole with node A runs into a wire with a node B. Our short circuits detector algorithm may do false alarms as well due to the fact that the suspicious points are selected by a distance classification. All the templates used in short circuit detection algorithm have centrally symmetric A templates providing a sufficient condition for the stability of the corresponding analogic operations. The template values were computed from the desired steady state of the CNN defined by local rules.
4. Current experiments on the experimental system
4.1 Black and white image generation After the scanning process, we get a grey scale picture of the printed circuit board. The layout error detection algorithms work on black and white images, so we have to generate black and white pictures where the interconnections are black and the isolation areas are white or opposite. We used the average and threshold templates shown in Table 1. To get the best results for different types of PCB-s we have to use different templates. The threshold level of the Threshold template can be set by the constant bias current z. The used time step was 1.
PCB types Code
Size in
number
pixels
The iteration numbers using the templates: Average
Threshold
z=...
P1
784*601
P2
320*397
3
0.5
P3
332*374
3
0.5
Remarks
4
The scanned image was not well processable
P4
784*255
3
0.5
Table 1. Black and white image generation
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4.2 Current experiments with analogic layout error detection algorithms by using the CNN-HAB accelerator board Having the black and white picture, we can start the error detection algorithms. The first experience was to find the breaks in the wire. (This algorithm finds the breaks in the horizontal and vertical wires.) The algorithm worked well, only the repeat parameters of skeleton algorithm had to be set. Table 2. contains these settings, and the processing times on an Intel Pentium PC with 75MHz by using the CNN-HAB accelerator board [3]. An artwork film input of F1 and the result of the error detection are in Figure 16. The second experience was to find the ”H” type short circuits on a printed circuit board. Here also the repeat parameters had to be set, and in the distance classification the possible maximum distance have to be defined between the two farthest points of the short circuit. The input of the P1 and the results of the error detection are in Figure 17. The critical parameters and the processing times are shown in Table 2. for some real-life examples. The primary aim of these experiments were to test our analogic algorithms in complex real-life examples.
PCB types Code number
Finding breaks skeleton repeat
processing
number
time
P1
2
P2
Finding short circuits peeling 1
peeling 2
distance
processing
repeat number
repeat number
settings
time
2.5 min
5
3
2*4
12 min
4
1.5 min
5
3
2*7
4.5 min
P3
2
2 min
3
2
2*4
3 min
P4
3
2 min
5
3
2*4
7.5 min
F1 (artwork)
2
1.5 min
5
3
2*4
6.5 min
Table 2 Current experiments with CNN-HAB
4.3 Current experiments by using a 20*22 CNN Universal Machine (CNNUM) chip A 20*22 CNNUM chip [14 ], designed 0.8 µ CMOS technology with on-chip optical input, was used. The input and the output are binary (±1). Four binary images and eight different templates can be stored on the chip. The time constant of the chip is 250ns. In order to achieve the available maximum speed of the chip, all the used templates and intermediate results were stored on the chip. Due to the on-chip memory limitations, the number of the templates and internally stored images should not exceed 8 or 4, respectively. The measured accuracy of the chip [14 ] was about 6-7 bits. The CNN Chip Prototyping System (CCPS) [13] provided an easy-to-use analogic algorithm development environment to the 20*22 CNNUM chip. The break detection algorithm was written in C++ using the ACL library and also on Analogic Machine Code (AMC). In our test example black and white input image was used. The algorithm was run 5000 times and the whole time was measured. The time requirement of the algorithm including the image and template downloading to the chip and saving the results in a file - supposing one skeletonization step, was 7.6 ms by using the AMC code. The processing speed value 57895 pixels/s on the 20*22 CNNUM chip and it is higher than the best published processing speed values of professional AOI systems [7].
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Figure 18. The input layout image and the detected wire breaks by using a 20*22 CNNUM chip The templates of the break detection analogic algorithm were robust enough to be implemented on the CNNUM chip with six bit accuracy. The CCPS system has an automatic template conversion procedure to compute the template values down loaded on the chip from the templates values stored in the CNN Software Library [5]. The CNNUM chip can use templates of the nearest neighbourhood. The allowed range of bias value and of other template values are ±6 and ±3, respectively. Due to these limitations, some templates of the short circuit detector algorithm have to be scaled to run it on this chip.
5. Conclusions Analogic CNN algorithms were given to detect layout errors on printed circuit boards. The algorithms were tested on real-life examples by using the CNN-HAB, a digitally emulated CNN and the results were promising. The time requirements of all the layout error detection algorithms using digital image processing methods are proportional to the area of the layout to be tested. The time dependence of the analog VLSI implementation of the analogic algorithms proposed here are independent of the area to be checked, providing a very high processing speed. To check this property the break detection algorithm was implemented on a 20*22 CNNUM chip. The processing speed value of break detection algorithm running on a relatively small CNNUM chip is higher than the best published processing speed values of professional AOI systems [7]. The processing speed is increasing linearly with the number of the pixels (CNN cells) on a CNNUM chip. A CNNUM based test system using larger and more powerful chips can be a low cost part of a computer-integrated manufacturing system of PCBs.
Acknowledgement This work has been supported by Research Grant No. T019063 National Research Fund of Hungary (OTKA)
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[6] R. T. Chin, C. A. Harlow, “ Automated Visual Inspection: A Survey”, IEEE Trans. on Pattern Analysis and Machine Intelligence, Vol. PAMI-4, No.6, pp. 557-573, (Nov. 1982) [7] M. Maganti, F.Ercal, C.H.Dagli and S. Tsunekawa, ”Automatic PCB Inspection Algorithms: a Survey”, Computer Vision and Image Understanding, Vol. 63, No 2. pp. 287-313 ( March 1996.) [8] G. A. W. West,” A System for the Automatic Visual Inspection of Bare-Printed Circuit Boards”, IEEE Trans. on Systems, Man and Cybernetics, Vol. SMC-114, No. 5, pp. 767-773, (Sept./Oct. 1984.) [9] Y. Hara, H. Doi, K. Karasaki, T. Iida, “ A System for PCB Automated Inspection Using Fluorescent Light”, IEEE Trans. on Pattern Analysis and Machine Intelligence, Vol. PAMI-10, No.1, pp. 69-78, (Jan. 1988.) [10] A. M. Darwish, A. K. Jain, “ A Rule Based Approach for Visual Pattern Inspection”, IEEE Trans. on Pattern Analysis and Machine Intelligence, Vol. PAMI-10, No.1, pp. 56-68, (Jan. 1988.) [11] HP ScanJet Plus User’s Manual. 1989. [12] P. Szolgay, K. Tömördi, "Optical detection of breaks and short circuits on the layouts of printed circuit boards using CNN" Proceedings of CNNA '96 Seville, pp. 87-91, 1996. [13] T. Roska, P. Szolgay, Á. Zarándy, P. Venetianer, A. Radványi, T. Szirányi, "On a CNN chip-prototyping system" Proceedings of CNNA '94, Rome, pp 375-380, 1994. [14] R.Dominguez-Castro, S.Espejo, A.Rodriguez-Vázques, R.Carmona,P.Földesy, Á. Zarándy, P. Szolgay, T. Szirányi and T. Roska “A 0.8 µm CMOS 2-D programmable mixed-signal focal-plane array-processor with on-chip binary imaging and instructions storage” Vision Chip with Local Logic and Image Memory, IEEE J. of Solid State Circuits Vol. 32, No. 7, pp. 1013-1026, (July,1997.)
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Figure 16. Detecting breaks in the wires (F1)
Figure 17. Detecting short circuits (P1)
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