(Lecture #15). The slides included herein were taken from the materials
accompanying. Fundamentals of Logic Design, 6th Edition, by Roth and Kinney,.
ECE 331 – Digital System Design
Constraints in Logic Circuit Design (Lecture #15)
The slides included herein were taken from the materials accompanying Fundamentals of Logic Design, 6th Edition, by Roth and Kinney, and were used with permission from Cengage Learning.
Power Consumption
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Power Consumption •
Each integrated circuit (IC) consumes power
•
Power consumption can be divided into two parts: – Static power consumption (PS) – Dynamic power consumption (PD)
•
Total power consumption (PT) can then be determined as – PT = PS + PD
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Static Power Consumption •
PS = VCC * ICC –
VCC = supply voltage
–
ICC = supply current
•
ICC and VCC are specified in the datasheet for the integrated circuit (IC).
•
For TTL devices, PS is significant.
•
For CMOS devices, PS is very small (~0 W).
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Example: 74LS08 VCC
ICCH, ICCL Spring 2011
ECE 331 - Digital System Design
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Example: 74LS32 VCC
ICCH, ICCL Spring 2011
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Example: 74HC32 VCC
Spring 2011 ICC
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Example: Static Power Consumption IC
VCC (max) ICCH (max) ICCL (max) PSH (max) PSL (max)
74LS08
5.25 V
74LS32
5.25 V
74HC32
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6.00 V
4.8 mA
25.2 mW 8.8 mA
6.2 mA
46.2 mW 32.55 mW
9.8 mA 20 µA
51.45 mW 120 µW
20 µA
ECE 331 - Digital System Design
120 µW
8
Example: Static Power Consumption ●
The static power consumption is a function of the duty cycle. –
●
●
PS = PS_high * thigh + PS_low * tlow –
where thigh = time in the high state
–
and tlow = time in the low state
Assume a 50% duty cycle –
●
duty cycle – percentage of time in the high state
PS = PS_high * 0.5 + PS_low * 0.5
Assume a 60% duty cycle –
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PS = PS_high * 0.6 + PS_low * 0.4 ECE 331 - Digital System Design
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Example: Static Power Consumption IC 74LS08 74LS32 74HC32
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PSH (max) PSL (max) 25.2 mW 46.2 mW 32.55 mW 51.45 mW 120 µW 120 µW
50%
60%
35.7 mW
33.6 mW
42.0 mW
40.11 mW
120 µW
120 µW
ECE 331 - Digital System Design
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Dynamic Power Consumption ●
For TTL devices, PD is negligible compared to PS. –
●
For CMOS devices, PD dominates PT. –
●
Assume PD = 0 PD >> PS
PD in CMOS circuits arises from the movement of charge into and out of the device capacitance.
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Dynamic Power Consumption ●
●
In CMOS devices, charge is stored in the –
CPD = power dissipation capacitance (internal)
–
CL = capacitance of the load and wires (external)
These capacitors are in parallel –
●
CT = CPD + CL
The stored charge (on these capacitors) is –
Fall 2010
QT = CT * VDD = (CPD + CL) * VDD ECE 331 - Digital System Design
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Dynamic Power Consumption ●
●
The charge moves into and out of the capacitors on every transition of the output. –
Low → High
–
High → Low
Current = movement of charge –
IAVG = (CPD + CL) * VDD * fT ●
●
Where fT = output frequency
PD = IAVG * VDD = (CPD + CL) * V2DD * fT
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Example: 74HC00 VCC
CPD
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Example: Dynamic Power Consumption ●
From the data sheet for the 74HC00 –
●
VDD = 6V, CPD = 20 pF, CL = 50 pF
PD = (20 pF + 50 pF) * (6V)2 * fT fT (Hz)
PD (W)
1K
2.5 µ 2.52 m 252 m
1M 100 M
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Example: 74HC00
ICC VCC Spring 2011
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Example: Total Power Consumption ●
●
For the 74HC00, PS is determined as follows –
VDD = 6V
–
IDD = 20 µA
–
PS = VDD * IDD = 6V * 10 µA = 60 µW (~ 0 W )
The PT is then determined from
Fall 2010
–
PT = PS + PD
–
where PD is a function of fT ECE 331 - Digital System Design
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Total Power Consumption ●
Compare PT for 74xx00 (Quad 2-input NAND):
LS (TTL) HC (CMOS)
Fall 2010
0 Hz 15.8 mW 60 µW
1 MHz 15.8 mW 2.58 mW
ECE 331 - Digital System Design
100 MHz 15.8 mW 250 mW
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Total Power Consumption ●
Compare TTL and CMOS:
Fall 2010
PS
TTL VCC * ICC
CMOS VDD * IDD
PD
~0W
(CPD + CL) * (VDD)2 * fT
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Time Delay
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Time Delay ●
A standard logic gate does not respond to a change in its input(s) instantaneously.
●
There is, instead, a finite delay between a change in the input and a change in the output.
●
The propagation delay of a standard logic gate is specified in its data sheet.
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–
tPLH = low-to-high propagation delay
–
tPHL = high-to-low propagation delay ECE 331 - Digital System Design
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Time Delay ●
The time delay of individual logic gates can be used to determine the overall propagation delay of a logic circuit.
●
The propagation delay of a logic circuit can be used to define
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–
When the output of the logic circuit is valid.
–
The maximum speed of the combinational logic circuit.
–
The maximum frequency of the sequential logic circuit.
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Timing Analysis ●
A simple timing analysis can be performed on a logic circuit assuming that –
●
only one input transitions at a time
The time delay between the transition on the input and the transition on the output can be determined as follows
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–
identify the path between the input and output
–
sum the gate delays of all gates in the path ECE 331 - Digital System Design
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Timing Analysis ●
However, –
Some logic circuits have more than one path between an input and the output.
–
In some logic circuits, multiple inputs transition at the same time.
●
The simple timing analysis will not work.
●
Instead, perform a more conservative timing analysis using the –
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Sum of Worst Cases (SWC) Analysis method ECE 331 - Digital System Design
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Timing Analysis: SWC ●
Identify all input-output paths (i.e. delay paths)
●
Using the datasheet, select the worst-case gate delay for each logic gate. –
●
Calculate the worst-case delay for each path –
●
Select maximum of tPLH and tPHL Sum the gate delays of the gates in the path
Select the worst case –
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The maximum propagation delay for the circuit ECE 331 - Digital System Design
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Timing Analysis: SWC
Example: Using the SWC analysis method, determine the maximum propagation delay for the Exclusive-OR (XOR) Logic Circuit.
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Example: SWC A 74LS08
B 74F04
74LS04
74F08
tPLH (ns)
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F
74F32
tPHL (ns)
74LS04
min 0
typ 9
max 15
min 0
typ 10
max 14
74F04 74LS08 74F08
2.4 0 2.4
3.7 8 3.7
6.0 18 6.2
1.5 0 2.0
3.2 10 3.2
5.4 20 5.3
74F32
2.4
3.7
6.1
1.8
3.2
5.5
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Example: SWC A 74LS08
B 74F04
74LS04
74F08
tPD = 26.1 ns
tPLH (ns)
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F
74F32
tPHL (ns)
74LS04
min 0
typ 9
max 15
min 0
typ 10
max 14
74F04 74LS08 74F08
2.4 0 2.4
3.7 8 3.7
6.0 18 6.2
1.5 0 2.0
3.2 10 3.2
5.4 20 5.3
74F32
2.4
3.7
6.1
1.8
3.2
5.5
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Example: SWC A 74LS08
B 74F04
74LS04
74F08
tPD = 27.3 ns
tPLH (ns)
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F
74F32
tPHL (ns)
74LS04
min 0
typ 9
max 15
min 0
typ 10
max 14
74F04 74LS08 74F08
2.4 0 2.4
3.7 8 3.7
6.0 18 6.2
1.5 0 2.0
3.2 10 3.2
5.4 20 5.3
74F32
2.4
3.7
6.1
1.8
3.2
5.5
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Example: SWC A 74LS08
B 74F04
74LS04
74F08
tPD = 32.1 ns
tPLH (ns)
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F
74F32
tPHL (ns)
74LS04
min 0
typ 9
max 15
min 0
typ 10
max 14
74F04 74LS08 74F08
2.4 0 2.4
3.7 8 3.7
6.0 18 6.2
1.5 0 2.0
3.2 10 3.2
5.4 20 5.3
74F32
2.4
3.7
6.1
1.8
3.2
5.5
ECE 331 - Digital System Design
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Example: SWC A 74LS08
B 74F04
74LS04
74F08
tPD = 12.3 ns
tPLH (ns)
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F
74F32
tPHL (ns)
74LS04
min 0
typ 9
max 15
min 0
typ 10
max 14
74F04 74LS08 74F08
2.4 0 2.4
3.7 8 3.7
6.0 18 6.2
1.5 0 2.0
3.2 10 3.2
5.4 20 5.3
74F32
2.4
3.7
6.1
1.8
3.2
5.5
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Example: SWC
Input A (1) A (2) B (1) B (2)
Output F F F F
Delay (ns) 26.1 27.3 32.1 12.3
Worst Case Propagation Delay = 32.1 ns
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Transient Behavior
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Hazards ●
When the input to a combinational logic circuit changes, unwanted switching transients may appear on the output.
●
These transients occur when different paths from input to output have different propagation delays.
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Hazards transient
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Static 1-Hazards ●
When analyzing combinational logic circuits for hazards we will consider the case where only one input changes at a time.
●
Under this condition, a static 1-hazard occurs when the input change causes one product term (in a SOP expression) to transition from 1 to 0 and another product term to transition from 0 to 1.
●
Both product terms can be transiently 0, resulting in the static 1-hazard.
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Detecting Static 1-Hazards We can detect hazards in a two-level AND-OR circuit using the following procedure: 1. Write down the sum-of-products expression for the circuit. 2. Plot each term on the K-map and circle it. 3. If any two adjacent 1′s are not covered by the same circle, a 1-hazard exists for the transition between the two 1′s. For an n-variable map, this transition occurs when one variable changes and the other n – 1 variables are held constant.
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Detecting Static 1-Hazards
A= 1 C=1 B = 1 → 0 at 20ns
gate delay = 10ns Static 1-Hazard
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Removing Static 1-Hazards redundant, but necessary to remove hazard
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Static 0-Hazards ●
Again, consider the case where only one input changes at a time.
●
Under this condition, a static 0-hazard occurs when the input change causes one sum term (in a POS expression) to transition from 0 to 1 and another sum term to transition from 1 to 0.
●
Both sum terms can be transiently 1, resulting in the static 0-hazard.
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Detecting Static 0-Hazards We can detect hazards in a two-level OR-AND circuit using the following procedure: 1. Write down the product-of-sums expression for the circuit. 2. Plot each sum term on the map and loop the zeros. 3. If any two adjacent 0′s are not covered by the same loop, a 0-hazard exists for the transition between the two 0′s. For an n-variable map, this transition occurs when one variable changes and the other n – 1 variables are held constant.
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Detecting Static 0-Hazards
A=0 B=1 D=0 C = 0 → 1 at 5ns
Static 0-Hazard
AND/OR delay = 5ns NOT delay = 3ns Spring 2011
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Removing Static 0-Hazards
How many redundant gates are necessary to remove the 0-hazards? Spring 2011
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Hazards
Exercise: Design a hazard-free combinational logic circuit to implement the following logic function F(A,B,C,D) = A'.C' + A.D + B.C.D'
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Hazards
Exercise: Design a hazard-free combinational logic circuit to implement the following logic function F(A,B,C,D) = (A'+C').(A+D).(B+C+D')
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Hazards ●
Two-level AND-OR circuits (SOP) cannot have Static 0-Hazards.
●
Two-level OR-AND circuits (POS) cannot have Static 1-Hazards. Why?
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Questions?
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