11: Adders. Slide 3. CMOS VLSI Design. Single-Bit Addition. Half Adder. Full
Adder. 1. 1. 0. 1. 1. 0. 0. 0. S. C out. B. A. 1. 1. 1. 0. 1. 1. 1. 0. 1. 0. 0. 1. 1. 1. 0. 0. 1.
0.
December 31, 2007 Dr. Lynn Fuller. Rochester Institute of Technology.
Microelectronic Engineering. CMOS VLSI DESIGN. Page 1. ROCHESTER
INSTITUTE OF ...
May 24, 2002 - LASI 6.2, members.aol.com/lasicad. SPICEOPUS 2.03, fides.fe.uni-lj.si/spice cir2sp3, custom parser for netlist interface. â· Target technology:.
for a mixed analog-digital simulation environment in VLSI microelectronics ... that
the students are asked to design the comparator as full custom (low level ...
Design. 2. Introduction. ○ Integrated Circuits: many transistors on one chip. ○
Very Large ... Logic Design. ○ Physical ... T-R-A-N-S-I-S-T-O-R = TRANsfer
resiSTOR. ○ 1947: ... 1963: Frank Wanlass at Fairchild describes the first CMOS
logic gate (
24 Mar 2010 ... P.E. Allen and D.R. Holberg, CMOS Analog Circuit Design – 2nd Ed., ... B. Razavi
, Design of Analog CMOS Integrated Circuits, McGraw-Hill, ...
Vtout Vout. 500. Rt2. Vin. Vout. 500. 8. CMOS Mixed-Signal Circuit Design ...... Part (b) shows the result of etching down into the silicon areas that are exposed,.
Figure 30.2 Signals resulting from A/D and D/A conversion in a mixed-signal system. Anti-aliasing ...... The PSD is the Fourier transform of this equation (see Eq. [30.2] in the last chapter), ...... Available at http://legwww.epfl.ch/ekv/index.html.
Aug 18, 2006 - 1.2 Checking the correctness of the design file using ASIMUT. ...... Description bit. The standard bit type: '0' or '1' bit vector. Array of bits mux bit.
Introduction to VLSI CMOS Circuits Design. 1. Carlos Silva Cardenas. Catholic
University of Perú. Takeo Yoshida. University of the Ryukyus. Alberto Palacios ...
1998, XXXV, 422 p. Printed book. Hardcover. ▷ 172,95 € | £137.00 | $229.00. ▷
*185,06 € (D) | 190,25 € (A) | CHF 248.00. eBook. Available from your library or.
Aug 9, 1988 ... design of the output cell of a bipolar VLSI gate array IC. .... Standard VBB-based
internal comparator: Inside a VLSI IC, ECL VOH and VOL ...
In the first section of the lab, you will design the ALU decoder control logic by ...
The function of the aludec logic is defined in Chapter 1 of CMOS VLSI Design.
are intended to be used in conjunction with CMOS VLSI Design, 4 th ... VLSI
designers have a wide variety of CAD tools to choose from, each with their own.
preparing this book, they make no representation or warranties with respect to the ..... 17.1.2 Using DSM for Sensing in Flash Memory ...... GDS file in LASI (or any other layout pro-gram) is often called streaming the layout .... Please read the fil
Design of High-Performance Microprocessor Circuits. Anantha ...... showing the input-referred PSD of the output noise is a fiat spectrurn from DC to infinity!
EE382M-14 CMOS Analog Integrated Circuit Design. Lecture 3, MOS
Capacitances Small Signal Models, and. Passive Components. MOS
Capacitances n+ n+.
any LASI program to run from any directory on the hard disk. Drawing ... Using the. List command button and clicking on the cell "rulel" puts us into the drawing display ...... percent of ~ , we can define the diode reverse recovery time, or. (2.10).
2, FEBRUARY 2005. Millimeter-Wave CMOS Circuit Design. Hisao Shigematsu, Member, IEEE, Tatsuya Hirose, Forrest Brewer, and Mark Rodwell, Fellow, IEEE.
Series in Electrical and Computer Engineering) ... and Computer Engineering) Online , Read Best Book CMOS Analog Circuit
California Institute of Technology. Pasadena, CA 91125, USA. {sean,cc,alain}@async.caltech.edu. â Department of Electrical Engineering. University of Southern ...
Introduction q What makes a circuit fast? – I = C dV/dt -> tpd ∝ (C/I) ∆V – low capacitance – high current 4 B – small swing 4 A q Logical effort is proportional to C/I 1 1 q pMOS are the enemy! – High capacitance for a given current q Can we take the pMOS capacitance off the input? q Various circuit families try to do this… 9: Circuit Families
CMOS VLSI Design
Y
Slide 3
Pseudo-nMOS q In the old days, nMOS processes had no pMOS – Instead, use pull-up transistor that is always ON q In CMOS, use a pMOS that is always ON – Ratio issue – Make pMOS about ¼ effective strength of pulldown network 1.8 1.5
load P/2
1.2 P = 24
Ids
Vout 0.9
Vout 16/2 Vin
0.6 P = 14 0.3
P=4
0 0
0.3
0.6
0.9
1.2
1.5
1.8
Vin
9: Circuit Families
CMOS VLSI Design
Slide 4
Pseudo-nMOS Gates q Design for unit current on output to compare with unit inverter. q pMOS fights nMOS
Y inputs f
Inverter
A
gu gd gavg Y pu pd pavg
NAND2 = = = = = =
9: Circuit Families
A B
gu g Y gd avg pu pd pavg
NOR2 = = = = = =
CMOS VLSI Design
A
B
gu gd gavg Y pu pd pavg
= = = = = = Slide 5
Pseudo-nMOS Gates q Design for unit current on output to compare with unit inverter. q pMOS fights nMOS
Y inputs f
Inverter
A
gu gd gavg 2/3 Y pu 4/3 pd pavg
NAND2 = = = = = =
9: Circuit Families
gu g Y gd avg 8/3 pu 8/3 pd pavg 2/3
A B
NOR2 = = = = = =
CMOS VLSI Design
2/3 A
4/3 B
gu gd gavg Y pu 4/3 pd pavg
= = = = = = Slide 6
Pseudo-nMOS Gates q Design for unit current on output to compare with unit inverter. q pMOS fights nMOS
Y inputs f
Inverter
A
gu gd gavg 2/3 Y pu 4/3 pd pavg
NAND2 = 4/3 = 4/9 = 8/9 = = =
9: Circuit Families
A B
gu 2/3 g Y gd avg 8/3 pu 8/3 pd pavg
NOR2 = 8/3 = 8/9 = 16/9 = = =
CMOS VLSI Design
2/3 A
4/3 B
gu gd gavg Y pu 4/3 pd pavg
= 4/3 = 4/9 = 8/9 = = = Slide 7
Pseudo-nMOS Gates q Design for unit current on output to compare with unit inverter. q pMOS fights nMOS
Y inputs f
Inverter
A
gu gd gavg 2/3 Y pu 4/3 pd pavg
NAND2 = 4/3 = 4/9 = 8/9 = 6/3 = 6/9 = 12/9
9: Circuit Families
gu g Y gd avg 8/3 pu 8/3 pd pavg 2/3
A B
NOR2 = 8/3 = 8/9 = 16/9 = 10/3 = 10/9 = 20/9
CMOS VLSI Design
2/3 A
4/3 B
gu gd gavg Y pu 4/3 pd pavg
= 4/3 = 4/9 = 8/9 = 10/3 = 10/9 = 20/9 Slide 8
Pseudo-nMOS Design q Ex: Design a k-input AND gate using pseudo-nMOS. Estimate the delay driving a fanout of H Pseudo-nMOS
q q q q q
G= F= P= N= D=
9: Circuit Families
In1
1
Ink
1
CMOS VLSI Design
Y H
Slide 9
Pseudo-nMOS Design q Ex: Design a k-input AND gate using pseudo-nMOS. Estimate the delay driving a fanout of H Pseudo-nMOS
q q q q q
G = 1 * 8/9 = 8/9 F = GBH = 8H/9 P = 1 + (4+8k)/9 = (8k+13)/9 N=2 4 2 H 8k + 13 1/N D = NF + P = 3 + 9
9: Circuit Families
In1
1
Ink
1
CMOS VLSI Design
Y H
Slide 10
Pseudo-nMOS Power q Pseudo-nMOS draws power whenever Y = 0 – Called static power P = I•VDD – A few mA / gate * 1M gates would be a problem – This is why nMOS went extinct! q Use pseudo-nMOS sparingly for wide NORs q Turn off pMOS when not in use en Y A
9: Circuit Families
B
C
CMOS VLSI Design
Slide 11
Dynamic Logic q Dynamic gates uses a clocked pMOS pullup q Two modes: precharge and evaluate 2 A
φ
2/3 Y
1
Y
1
A
Static
4/3
Pseudo-nMOS φ
Precharge
Y A
1
Dynamic Evaluate
Precharge
Y
9: Circuit Families
CMOS VLSI Design
Slide 12
The Foot q What if pulldown network is ON during precharge? q Use series evaluation transistor to prevent fight. precharge transistor
φ Y
φ
φ Y
inputs
A
Y inputs
f
f
foot footed
9: Circuit Families
CMOS VLSI Design
unfooted
Slide 13
Logical Effort Inverter
φ
unfooted
NAND2
1 gd pd
φ
footed
9: Circuit Families
A
2
φ
B
2
1
gd pd
φ
1
A
3
2
B
3
gd pd
= =
3
1 Y
= =
A
Y
1
2
1
= =
Y A
φ
Y
1 Y
A
NOR2
φ
B
1 gd pd
= =
1 Y
gd pd
= =
CMOS VLSI Design
A
2
B 2
2 gd pd
= =
Slide 14
Logical Effort Inverter
φ
unfooted
NAND2
1 gd pd
φ
footed
9: Circuit Families
A
2
φ
B
2
1
gd pd
φ
1
A
3
2
B
3
gd pd
= 2/3 = 3/3
3
1 Y
= 2/3 = 3/3
A
Y
1
2
1
= 1/3 = 2/3
Y A
φ
Y
1 Y
A
NOR2
φ
B
1 gd pd
= 1/3 = 3/3
1 Y
gd pd
= 3/3 = 4/3
CMOS VLSI Design
A
2
B 2
2 gd pd
= 2/3 = 5/3
Slide 15
Monotonicity q Dynamic gates require monotonically rising inputs during evaluation φ – 0 -> 0 A – 0 -> 1 – 1 -> 1 violates monotonicity – But not 1 -> 0 during evaluation A φ
Precharge
Evaluate
Precharge
Y Output should rise but does not
9: Circuit Families
CMOS VLSI Design
Slide 16
Monotonicity Woes q But dynamic gates produce monotonically falling outputs during evaluation q Illegal for one dynamic gate to drive another!
A=1 φ A
Y
φ
Precharge
Evaluate
Precharge
X X Y
9: Circuit Families
CMOS VLSI Design
Slide 17
Monotonicity Woes q But dynamic gates produce monotonically falling outputs during evaluation q Illegal for one dynamic gate to drive another!
A=1 φ A
Y
φ
Precharge
Evaluate
Precharge
X X X monotonically falls during evaluation Y Y should rise but cannot
9: Circuit Families
CMOS VLSI Design
Slide 18
Domino Gates q Follow dynamic stage with inverting static gate – Dynamic / static pair is called domino gate – Produces monotonic outputs φ
Precharge
Evaluate
Precharge
domino AND W
W
X
Y
Z
X
A B
C
φ
Y Z
dynamic static NAND inverter
φ A B
9: Circuit Families
φ
φ W
X
H C
CMOS VLSI Design
Y
H
Z
=
A B
φ X C
Slide 19
Z
Domino Optimizations q Each domino gate triggers next one, like a string of dominos toppling over q Gates evaluate sequentially but precharge in parallel q Thus evaluation is more critical than precharge q HI-skewed static stages can perform logic φ S0
S1
S2
S3
D0
D1
D2
D3 H
Y
φ
9: Circuit Families
S4
S5
S6
S7
D4
D5
D6
D7
CMOS VLSI Design
Slide 20
Dual-Rail Domino q Domino only performs noninverting functions: – AND, OR but not NAND, NOR, or XOR q Dual-rail domino solves this problem – Takes true and complementary inputs – Produces true and complementary outputs sig_h
sig_l
Meaning
0
0
Precharged
0
1
‘0’
1
0
‘1’
1
1
invalid
9: Circuit Families
φ
Y_l inputs
f
Y_h f
φ
CMOS VLSI Design
Slide 21
Example: AND/NAND q Given A_h, A_l, B_h, B_l q Compute Y_h = A * B, Y_l = ~(A * B)
9: Circuit Families
CMOS VLSI Design
Slide 22
Example: AND/NAND q Given A_h, A_l, B_h, B_l q Compute Y_h = A * B, Y_l = ~(A * B) q Pulldown networks are conduction complements
Y_l
φ A_h
= A*B A_l
B_l
Y_h = A*B
B_h φ
9: Circuit Families
CMOS VLSI Design
Slide 23
Example: XOR/XNOR q Sometimes possible to share transistors
φ
Y_l = A xnor B
A_h
Y_h
A_l
A_l
B_l
B_h
A_h
= A xor B
φ
9: Circuit Families
CMOS VLSI Design
Slide 24
Leakage q Dynamic node floats high during evaluation – Transistors are leaky (IOFF ≠ 0) – Dynamic value will leak away over time – Formerly miliseconds, now nanoseconds! q Use keeper to hold dynamic node – Must be weak enough not to fight evaluation weak keeper φ A
1 k
X
H
Y
2 2
9: Circuit Families
CMOS VLSI Design
Slide 25
Charge Sharing q Dynamic gates suffer from charge sharing φ
φ A
Y CY
x
A Y
B=0
Cx x
9: Circuit Families
CMOS VLSI Design
Slide 26
Charge Sharing q Dynamic gates suffer from charge sharing φ
φ A
Y CY
x
A Y
B=0
Cx
Charge sharing noise x
Vx = VY =
9: Circuit Families
CMOS VLSI Design
Slide 27
Charge Sharing q Dynamic gates suffer from charge sharing φ
φ A
Y CY
x
A Y
B=0
Cx
Charge sharing noise x
CY Vx = VY = VDD Cx + CY
9: Circuit Families
CMOS VLSI Design
Slide 28
Secondary Precharge q Solution: add secondary precharge transistors – Typically need to precharge every other node q Big load capacitance CY helps as well φ Y A
secondary precharge transistor
x
B
9: Circuit Families
CMOS VLSI Design
Slide 29
Noise Sensitivity q Dynamic gates are very sensitive to noise – Inputs: VIH ≈ Vtn – Outputs: floating output susceptible noise q Noise sources – Capacitive crosstalk – Charge sharing – Power supply noise – Feedthrough noise – And more!
9: Circuit Families
CMOS VLSI Design
Slide 30
Domino Summary q Domino logic is attractive for high-speed circuits – 1.5 – 2x faster than static CMOS – But many challenges: • Monotonicity • Leakage • Charge sharing • Noise q Widely used in high-performance microprocessors
9: Circuit Families
CMOS VLSI Design
Slide 31
Pass Transistor Circuits q Use pass transistors like switches to do logic q Inputs drive diffusion terminals as well as gates q CMOS + Transmission Gates: – 2-input multiplexer – Gates should be restoring S
S A
A S
S
Y
Y
B
B
S
S 9: Circuit Families
CMOS VLSI Design
Slide 32
LEAP q LEAn integration with Pass transistors q Get rid of pMOS transistors – Use weak pMOS feedback to pull fully high – Ratio constraint
S A S
L
Y
B
9: Circuit Families
CMOS VLSI Design
Slide 33
CPL q Complementary Pass-transistor Logic – Dual-rail form of pass transistor logic – Avoids need for ratioed feedback – Optional cross-coupling for rail-to-rail swing S A S
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