Lecture 9: Circuit Families - CMOS VLSI Design

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9: Circuit Families. Slide 2. CMOS VLSI Design. Outline. ❑ Pseudo-nMOS Logic. ❑ Dynamic Logic. ❑ Pass Transistor Logic ...
Introduction to CMOS VLSI Design

Lecture 9: Circuit Families David Harris

Harvey Mudd College Spring 2004

Outline q Pseudo-nMOS Logic q Dynamic Logic q Pass Transistor Logic

9: Circuit Families

CMOS VLSI Design

Slide 2

Introduction q What makes a circuit fast? – I = C dV/dt -> tpd ∝ (C/I) ∆V – low capacitance – high current 4 B – small swing 4 A q Logical effort is proportional to C/I 1 1 q pMOS are the enemy! – High capacitance for a given current q Can we take the pMOS capacitance off the input? q Various circuit families try to do this… 9: Circuit Families

CMOS VLSI Design

Y

Slide 3

Pseudo-nMOS q In the old days, nMOS processes had no pMOS – Instead, use pull-up transistor that is always ON q In CMOS, use a pMOS that is always ON – Ratio issue – Make pMOS about ¼ effective strength of pulldown network 1.8 1.5

load P/2

1.2 P = 24

Ids

Vout 0.9

Vout 16/2 Vin

0.6 P = 14 0.3

P=4

0 0

0.3

0.6

0.9

1.2

1.5

1.8

Vin

9: Circuit Families

CMOS VLSI Design

Slide 4

Pseudo-nMOS Gates q Design for unit current on output to compare with unit inverter. q pMOS fights nMOS

Y inputs f

Inverter

A

gu gd gavg Y pu pd pavg

NAND2 = = = = = =

9: Circuit Families

A B

gu g Y gd avg pu pd pavg

NOR2 = = = = = =

CMOS VLSI Design

A

B

gu gd gavg Y pu pd pavg

= = = = = = Slide 5

Pseudo-nMOS Gates q Design for unit current on output to compare with unit inverter. q pMOS fights nMOS

Y inputs f

Inverter

A

gu gd gavg 2/3 Y pu 4/3 pd pavg

NAND2 = = = = = =

9: Circuit Families

gu g Y gd avg 8/3 pu 8/3 pd pavg 2/3

A B

NOR2 = = = = = =

CMOS VLSI Design

2/3 A

4/3 B

gu gd gavg Y pu 4/3 pd pavg

= = = = = = Slide 6

Pseudo-nMOS Gates q Design for unit current on output to compare with unit inverter. q pMOS fights nMOS

Y inputs f

Inverter

A

gu gd gavg 2/3 Y pu 4/3 pd pavg

NAND2 = 4/3 = 4/9 = 8/9 = = =

9: Circuit Families

A B

gu 2/3 g Y gd avg 8/3 pu 8/3 pd pavg

NOR2 = 8/3 = 8/9 = 16/9 = = =

CMOS VLSI Design

2/3 A

4/3 B

gu gd gavg Y pu 4/3 pd pavg

= 4/3 = 4/9 = 8/9 = = = Slide 7

Pseudo-nMOS Gates q Design for unit current on output to compare with unit inverter. q pMOS fights nMOS

Y inputs f

Inverter

A

gu gd gavg 2/3 Y pu 4/3 pd pavg

NAND2 = 4/3 = 4/9 = 8/9 = 6/3 = 6/9 = 12/9

9: Circuit Families

gu g Y gd avg 8/3 pu 8/3 pd pavg 2/3

A B

NOR2 = 8/3 = 8/9 = 16/9 = 10/3 = 10/9 = 20/9

CMOS VLSI Design

2/3 A

4/3 B

gu gd gavg Y pu 4/3 pd pavg

= 4/3 = 4/9 = 8/9 = 10/3 = 10/9 = 20/9 Slide 8

Pseudo-nMOS Design q Ex: Design a k-input AND gate using pseudo-nMOS. Estimate the delay driving a fanout of H Pseudo-nMOS

q q q q q

G= F= P= N= D=

9: Circuit Families

In1

1

Ink

1

CMOS VLSI Design

Y H

Slide 9

Pseudo-nMOS Design q Ex: Design a k-input AND gate using pseudo-nMOS. Estimate the delay driving a fanout of H Pseudo-nMOS

q q q q q

G = 1 * 8/9 = 8/9 F = GBH = 8H/9 P = 1 + (4+8k)/9 = (8k+13)/9 N=2 4 2 H 8k + 13 1/N D = NF + P = 3 + 9

9: Circuit Families

In1

1

Ink

1

CMOS VLSI Design

Y H

Slide 10

Pseudo-nMOS Power q Pseudo-nMOS draws power whenever Y = 0 – Called static power P = I•VDD – A few mA / gate * 1M gates would be a problem – This is why nMOS went extinct! q Use pseudo-nMOS sparingly for wide NORs q Turn off pMOS when not in use en Y A

9: Circuit Families

B

C

CMOS VLSI Design

Slide 11

Dynamic Logic q Dynamic gates uses a clocked pMOS pullup q Two modes: precharge and evaluate 2 A

φ

2/3 Y

1

Y

1

A

Static

4/3

Pseudo-nMOS φ

Precharge

Y A

1

Dynamic Evaluate

Precharge

Y

9: Circuit Families

CMOS VLSI Design

Slide 12

The Foot q What if pulldown network is ON during precharge? q Use series evaluation transistor to prevent fight. precharge transistor

φ Y

φ

φ Y

inputs

A

Y inputs

f

f

foot footed

9: Circuit Families

CMOS VLSI Design

unfooted

Slide 13

Logical Effort Inverter

φ

unfooted

NAND2

1 gd pd

φ

footed

9: Circuit Families

A

2

φ

B

2

1

gd pd

φ

1

A

3

2

B

3

gd pd

= =

3

1 Y

= =

A

Y

1

2

1

= =

Y A

φ

Y

1 Y

A

NOR2

φ

B

1 gd pd

= =

1 Y

gd pd

= =

CMOS VLSI Design

A

2

B 2

2 gd pd

= =

Slide 14

Logical Effort Inverter

φ

unfooted

NAND2

1 gd pd

φ

footed

9: Circuit Families

A

2

φ

B

2

1

gd pd

φ

1

A

3

2

B

3

gd pd

= 2/3 = 3/3

3

1 Y

= 2/3 = 3/3

A

Y

1

2

1

= 1/3 = 2/3

Y A

φ

Y

1 Y

A

NOR2

φ

B

1 gd pd

= 1/3 = 3/3

1 Y

gd pd

= 3/3 = 4/3

CMOS VLSI Design

A

2

B 2

2 gd pd

= 2/3 = 5/3

Slide 15

Monotonicity q Dynamic gates require monotonically rising inputs during evaluation φ – 0 -> 0 A – 0 -> 1 – 1 -> 1 violates monotonicity – But not 1 -> 0 during evaluation A φ

Precharge

Evaluate

Precharge

Y Output should rise but does not

9: Circuit Families

CMOS VLSI Design

Slide 16

Monotonicity Woes q But dynamic gates produce monotonically falling outputs during evaluation q Illegal for one dynamic gate to drive another!

A=1 φ A

Y

φ

Precharge

Evaluate

Precharge

X X Y

9: Circuit Families

CMOS VLSI Design

Slide 17

Monotonicity Woes q But dynamic gates produce monotonically falling outputs during evaluation q Illegal for one dynamic gate to drive another!

A=1 φ A

Y

φ

Precharge

Evaluate

Precharge

X X X monotonically falls during evaluation Y Y should rise but cannot

9: Circuit Families

CMOS VLSI Design

Slide 18

Domino Gates q Follow dynamic stage with inverting static gate – Dynamic / static pair is called domino gate – Produces monotonic outputs φ

Precharge

Evaluate

Precharge

domino AND W

W

X

Y

Z

X

A B

C

φ

Y Z

dynamic static NAND inverter

φ A B

9: Circuit Families

φ

φ W

X

H C

CMOS VLSI Design

Y

H

Z

=

A B

φ X C

Slide 19

Z

Domino Optimizations q Each domino gate triggers next one, like a string of dominos toppling over q Gates evaluate sequentially but precharge in parallel q Thus evaluation is more critical than precharge q HI-skewed static stages can perform logic φ S0

S1

S2

S3

D0

D1

D2

D3 H

Y

φ

9: Circuit Families

S4

S5

S6

S7

D4

D5

D6

D7

CMOS VLSI Design

Slide 20

Dual-Rail Domino q Domino only performs noninverting functions: – AND, OR but not NAND, NOR, or XOR q Dual-rail domino solves this problem – Takes true and complementary inputs – Produces true and complementary outputs sig_h

sig_l

Meaning

0

0

Precharged

0

1

‘0’

1

0

‘1’

1

1

invalid

9: Circuit Families

φ

Y_l inputs

f

Y_h f

φ

CMOS VLSI Design

Slide 21

Example: AND/NAND q Given A_h, A_l, B_h, B_l q Compute Y_h = A * B, Y_l = ~(A * B)

9: Circuit Families

CMOS VLSI Design

Slide 22

Example: AND/NAND q Given A_h, A_l, B_h, B_l q Compute Y_h = A * B, Y_l = ~(A * B) q Pulldown networks are conduction complements

Y_l

φ A_h

= A*B A_l

B_l

Y_h = A*B

B_h φ

9: Circuit Families

CMOS VLSI Design

Slide 23

Example: XOR/XNOR q Sometimes possible to share transistors

φ

Y_l = A xnor B

A_h

Y_h

A_l

A_l

B_l

B_h

A_h

= A xor B

φ

9: Circuit Families

CMOS VLSI Design

Slide 24

Leakage q Dynamic node floats high during evaluation – Transistors are leaky (IOFF ≠ 0) – Dynamic value will leak away over time – Formerly miliseconds, now nanoseconds! q Use keeper to hold dynamic node – Must be weak enough not to fight evaluation weak keeper φ A

1 k

X

H

Y

2 2

9: Circuit Families

CMOS VLSI Design

Slide 25

Charge Sharing q Dynamic gates suffer from charge sharing φ

φ A

Y CY

x

A Y

B=0

Cx x

9: Circuit Families

CMOS VLSI Design

Slide 26

Charge Sharing q Dynamic gates suffer from charge sharing φ

φ A

Y CY

x

A Y

B=0

Cx

Charge sharing noise x

Vx = VY =

9: Circuit Families

CMOS VLSI Design

Slide 27

Charge Sharing q Dynamic gates suffer from charge sharing φ

φ A

Y CY

x

A Y

B=0

Cx

Charge sharing noise x

CY Vx = VY = VDD Cx + CY

9: Circuit Families

CMOS VLSI Design

Slide 28

Secondary Precharge q Solution: add secondary precharge transistors – Typically need to precharge every other node q Big load capacitance CY helps as well φ Y A

secondary precharge transistor

x

B

9: Circuit Families

CMOS VLSI Design

Slide 29

Noise Sensitivity q Dynamic gates are very sensitive to noise – Inputs: VIH ≈ Vtn – Outputs: floating output susceptible noise q Noise sources – Capacitive crosstalk – Charge sharing – Power supply noise – Feedthrough noise – And more!

9: Circuit Families

CMOS VLSI Design

Slide 30

Domino Summary q Domino logic is attractive for high-speed circuits – 1.5 – 2x faster than static CMOS – But many challenges: • Monotonicity • Leakage • Charge sharing • Noise q Widely used in high-performance microprocessors

9: Circuit Families

CMOS VLSI Design

Slide 31

Pass Transistor Circuits q Use pass transistors like switches to do logic q Inputs drive diffusion terminals as well as gates q CMOS + Transmission Gates: – 2-input multiplexer – Gates should be restoring S

S A

A S

S

Y

Y

B

B

S

S 9: Circuit Families

CMOS VLSI Design

Slide 32

LEAP q LEAn integration with Pass transistors q Get rid of pMOS transistors – Use weak pMOS feedback to pull fully high – Ratio constraint

S A S

L

Y

B

9: Circuit Families

CMOS VLSI Design

Slide 33

CPL q Complementary Pass-transistor Logic – Dual-rail form of pass transistor logic – Avoids need for ratioed feedback – Optional cross-coupling for rail-to-rail swing S A S

L

Y

L

Y

B S A S B

9: Circuit Families

CMOS VLSI Design

Slide 34