ECL VLSI ASIC 100K Circuit Design Optimization

1JTANDEMCOMPUTERS

ECL VLSI ASIC lOOK Circuit Design Optimization

Aurangzeb Khan DucLe Dong Nguyen Bipolar VLSI Design Group Tandem VLSI

Technical Report 88.7 August 1988 Part Number 16257

ECL

VLSI

ASIC

lOOK CIRCUIT DESIGN OPTIMIZATION

Aurangzeb Khan

Duc Le

Dong Nguyen

Bipolar VLSI Design Group, Tandem VLSI

Technical Report 88.7 August 1988 Part Number: 16257

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ECL VLSI ASIC lOOK' CIRCUIT DESIGN OPTIMIZATION Aurangzeb Khan

Due Le

Dong Nguyen

June 1988 This paper illustrates the complex, inter-related design optimization choices required to achieve efficient, high speed silicon bipolar ECL VLSI ASICs. We present three possible design choices for ECL internal circuit design, and briefly discuss the trade-offs involved in our final choice. We then show the impact of this optimization on output driver circuit design, and for example, the need for a new analytical framework to understand the lOOK performance of the chosen output circuit design. An analytical framework for the lOOK temperature compensation of an effective threelevel series-gated ECL output driver is then presented. This analysis was developed during the design of the output cell of a bipolar VLSI gate array IC. Results from this analysis have been shown to agree quite well with actual measurements and computer-aided simulations.

Table of Contents 3

Overview Internal Comparator Design Output Driver Design Circuit Design Choices - Overview

3 3 4

Input Receiver Circuit Design

4

Input Receiver Circuit

5 5

Internal Comparator Circuit Design Optimal ECL Internal Logic Swing Standard VBB-based Internal Comparator Common Mode VBB-based Internal Comparator Vrl-based Internal Comparator

5 6 7

8

lOOK Output Driver Design - Diode Stacking Considerations

9

Circuit Design Optimization - Conclusions

13

lOOK Output Temperature Compensation

13

ECL lOOK VOH and dVOH/dT Equations

14

ECL lOOK VOL and dVOL/dT Equations

15

RC/RCM Optimization

16

Conclusions

18

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OVERVIEW Silicon bipolar ECL circuits attain fast switching speeds partially due to their small, well-controlled logic voltage swing. Since the delay perfonnance of a digital circuit is proportional to its' logic swing, we note that excessive logic swing creates a delay penalty. However, if the logic voltage swing is too small compared to the total potential noise losses, we can attain marginal noise margins, and consequently suffer from poor signal integrity. Thus a well-balanced logic voltage swing is optimized to provide reliable high speed operation with assured signal integrity. Internal Comparator Design: System level electrical signals usually contain transient noise due to a variety of sources such as, impedance variation, reflection, crosstalk, etc. This design example illustrates how internal circuit design can have a major impact on output driver design. Let us define input receiver and internal comparator circuit functions. An IC input receiver circuit receives off-chip signal inputs and provides buffered output signals with well-defined voltage levels. It also provides good driving capability for driving other circuits within the IC. This circuit uses the standard ECL first level comparator reference voltage, called VBB, to arbitrate high and low level signals from inputs. Since the incoming system level signals are coded around this reference voltage, our design choices are restricted to utilizing to VBB reference only. On the other hand, internal comparator circuits are used to perfonn a variety of logic functions within the IC. Such circuits receive signals from, and source signals to, other logic circuits within the IC. Since we have control of both the source and destination circuits, we can design any appropriate logic swing, high and low levels, and comparator reference voltages. There are three options for internal comparator circuit design: 1. Use standard VBB as Vr1. (Fig 1) 2. Use standard VBB and a common mode resistor offset. (Fig 2) 3. Use non-standard Vrl optimized to provide comparable VN1vIH, VNML. (Fig 3) The first choice ensures signal compatibility with off-chip inputs. This enables a gate array architecture design which can accept off-chip inputs to any arbitrary location within the Ie, thus providing usage flexibility, and reduced output driver cells' utilization. However, this technique makes the total logic swing too large, thus incurring a delay penalty. The second choice also ensures signal compatibililty with off-chip inputs, thus providing usage flexibility, etc., as discussed above. Since the common mode offset resistor is used to tune the total logic swing to an optimal level, this technique does not incur a delay penalty. However, the need for an extra component raises the silicon real estate cost of this solution, and also adds to routing complexity. In the third design choice, we develop and use a non-standard ECL reference voltage, called Vrl, to optimize the total voltage swing without requiring a common mode offset resistor. This .:hoice has the added benefit of facilitating three-level lOOK series-gating, thus providing enhanced circuit functionality at no incremental power. However, this choice restricts the ability of the array architecture to allow off-chip signal inputs to any location inside the IC, unless suitable CAD programs are developed to provide appropriate reference voltages which depend upon the source of input signals. Further, this technique requires two separate voltage regulators, versus one in the ftrst two cases. However, this approach ensures an optimal logic swing, eliminates the need for repetitive common mode resistors, and provides an improved ECL three-level series-gating perfonnance. Our choice in this regard was further strengthened by our ability to get CAD software support which made appropriate reference selection an automated function. Consequently, we reduced the total logic Tandem Computers

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swing by 30%. This reduction is achieved without any loss in noise margin. It leads to a faster propagation time for no incremental power. Output Driver Design: Having selected the non-standard Vrl-based circuit as our internal ECL design, we find that this significantly channels our output driver design choices, especially for a series-gated lOOK ECL output driver. In the lOOK output driver (Fig 3), Vrl cannot be applied directly to the output current switch first level reference transistor, since this introduces a base/collector saturation hazard for the input transistor. Thus Vr2, which is the internal second level reference, is applied as the first level reference voltage. Vr2

= Vr1 - Vbe(Q9)

Therefore Vr3 becomes the second-level reference. However, note that Vr3 is offset from Vrl by 2 Vbe, and thus represents a true third-level series-gating reference. Vr3

= Vr2 - Vbe(Q13)

In a conventional ECL output driver design, Vr3 is not a viable voltage reference because three level deep series gating is not allowable. This follows from diode stacking considerations, as described later. We are able to overcome this constraint only because we developed a current mirror based comparator current mechanism. This allows an acceptable diode stacking, since a current mirror reduces ECL VEE min. requirements by -600 mV under nominal condition. Diode stacking refers to a minimum ECL VEE requirement which depends on the number of series gating stages utilized in comparator design. In ECL, all reference voltage - Vrl, Vr2, Vr3, etc. are developed with respect to ECL VCC. Further, all current source voltages are developed with respect to ECL VEE. The current source transistor is set-up so that its' base follows ECL VEE, while its' collector follows ECL VCe. If ECL VCC - ECL VEE falls below a critical minimum, defined as the diode stack, the current source can saturate. Such saturation causes unacceptable circuit behaviour. Fig. 4 represents the conventional lOOK current source based approach. In this case, ECL VEE min.

= -4.48 V - 0.12 V = -4.60 V

Where 4.48V is the ECL VEE applied to the IC and 0.l2V is the Ohmic voltage loss in the Ie package. Fig. 3 represents our lOOK current mirror based approach. In this case, ECL VEE min.

= -3.92 V - 0.12 V = -4.04 V

which is well below the ECL VEE min. requirement for commercial range lOOK ECL VLSI ICs, and therefore represents an acceptable design. Circuit Design Choices· Overview: In this section, the basic theme of this paper - design optimization inter-relationships - has been presented in overview form. The following sections discuss the design trade-offs in more detail.

INPUT RECEIVER CIRCUIT DESIGN ECL signals transmitted across digital systems' interconnect media follow well-defmed, standard ECL VOH and VOL levels. On the driving side, ECL output drivers deliver digital information encoded within specific high and low level voltage ranges. Usually however, such signals also pick up unwanted transient noise spikes due to PCB impedance variation, reflection, crosstalk, etc. Tandem Computers

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On the receiving side, ECL receiverlbuffer circuits decode incoming system voltages and provide buffered driving capability within an IC. The receiverlbuffer comparator circuits arbitrate high and low level inputs with respect to a reference voltage centred around the nominal ECL logic voltage swing. This voltage level, commonly called VBB, ensures adequate high and low level noise margins, when nominal VIR, Vn... levels are input to the IC. Input Receiver Circuit: A conventional ECL input receiver is presented in Fig. 1. This ECL switch performs a buffer/driver function. It receives off-chip signal inputs at A and provides a buffered output at YA, such that YA = A. Standard ECL levels are input to this circuit. For lOOK, these levels are:

-880 mV > VIH> -1025 mV -1625 mV > VIL > -1810 mV In order to ensure adequate noise margin levels when standard ECL I/O input levels are applied to this input buffer, the reference voltage, Vrl = VBB, is chosen. At room temperature, nominal VBB is set to --1305mV. In this case, minimum noise margins can be defined as:

VNMHmin. = VIHmin. - VBBnom. VNMLmin. = VBBnom. - VILmax.

= (-1025) - (-1305) = 280 mV = (-1305) - (-1625) = 320 mV

INTERNAL COMPARATOR CIRCUIT DESIGN Using VBB as the reference voltage for the internal comparator creates a sub-optimal design. Essentially, this follows because internal data transmission voltages can be better controlled than external, PCB level data transmission voltages. Thus, VOH, VOL levels within an IC can be designed to a smaller voltage swing. Optimal internal circuit design techniques also lead to internal VOH levels that differ from external VOH levels, making the use of the external VBB reference sub-optimal. In this section, we explore several design approaches to internal circuit optimization, and the impact these choices have on output driver design. Optimal ECL Internal Logic Swing: The logic swing chosen for IC-internal logic circuits must ensure signal intergrity with fast operation. We can view the logic swing, VI, as made up of two components,

VI = VNMLoss + Vlmin. In this equation, VNMLoss represents the potential worst-case noise margin losses and Vlmin represents the minimum voltage difference required to ensure proper comparator operation. Vlmin can be understood as follows. If we assume matched devices, then comparator behaviour depends on the voltage difference between the input applied to one comparator transistor's base, and the reference voltage applied to the other transistor's base. So,

Delta V = Yin - V,1 = VT*ln(IClIIC2) This equation illustrates a fundamental aspect of the comparator function. For example, as the input voltage rises 60 mV above the reference voltage, the current, ICS, is split in a 10: I ratio between ICI and IC2. The following table illustrates this aspect more comprehensively. The nominal forward conduction voltage of the ECL switch transistors, Vbe, varies inversely with temperature, which requires higher delta voltages at higher junction temperature.

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Delta V =f[Tj] (mV) -550C 270C 1250C

lcl:lc2

Ratio 10:1 100:1 1000:1

45

60

90 135

120

180

90 180 270

If we accpet Vlmin. as 180 mY, then we can expect a 1% error in internal VOL at a junction temperature of 125 degrees C. This is an acceptable design target. The other factor, VNMLoss,

is used to account for noise margin loss mechanisms present within a large ASIC device. Such mechanisms include Ohmic voltage losses on long routed signal nets, delta Vbe effects dut to ICS, IOEF programming, Wire-OR voltage losses, Vref variations, etc. Let us approximate the total impact of these factors to be 120 mV worst case, which is a reasonable target. Then we can derme the optimal logic swing for our VLSI ASIC design to be, VI

= Optimal Logic Swing = 600 mY.

Standard VBB-based internal comparator: Inside a VLSI IC, ECL VOH and VOL levels differ from external input levels. With reference to Fig. 1, note that when input A is at a high level with respect to Vrl, the OR output YA attains,

=ECL VCC - Vbe(Q4) VNMH =VOH - Vr1

VOH and,

Conversely, when input A is at a low level with respect to VBB, the OR output YA attains, VOL = ECL VCC - VI- Vbe(Q4) where, VI and,

=lCS*Rc

VNML

=Vr1 - VOL

Usually, VNML = 300 mV is considered adequate. If the same reference voltage, VBB, is used inside the IC, the internal high and low level noise margins can be defined as: VNMHnom. VNMLnom.

= VOHnom. - VBBnom. = -760 mV + 1305 mV = 545 mV = VBBnom. - VOLnom. =- 1305 mV + [845 mV + 760 mV] = 300 mV

While such a design methodology ensures adequate VNMH and VNML values, it creates an excessively large total logic voltage swing, VI. This follows because, VI

= VOH - VOL = VNMH + VNML = 845 mV

and VNMH is over-designed at 545 mY. Since the delay performance of this circuit is proportional to its logic swing, this excessive logic swing creates a delay penalty.

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ECL VCC

RC

YA

A

VBB

VCS

ECL VEE

Fig. 1: Conventional ECL Switch Common-mode VBB-based internal comparator: One design technique used to balance the VNMH and VNML values, and thus optimize the total logic swing, is to use a common mode offset resistor. Such an ECL current switch is shown in Fig. 2. In this case,

VI where, where,

= VOH - VOL

VOH = vee - Vem - Vbe(Q4) VOL = vee - (Vem + Vdm) - Vbe(Q4) Vem =Ies * Rem Vdm =Ies * Rdm

and, by design,

VI

= Vdm

This circuit reduces the excessive VNMH by developing a common mode offset voltage, Vern, across Rem. While this technique successfully addressses the excessive swing issue, it creates the need for an additional component in each ECL current switch. In a large VLSI IC, such additional components can consume considerable Silicon real estate.

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ECL VCC

RDM

YA A

VBB

VCS

ECL VEE

Fig. 2: EeL Switch with Voh Offset Resistance Vrl-based internal comparator: A third design technique used to balance the VNMH and VNML values, and thus optimize the total logic swing, is to use a non-standard ECL reference voltage. Such an ECL current switch is identical to the conventional circuit presented in Fig. 1, except that the reference voltage, Vrl, is chosen to balance both VNMH and VNML with an optimally minimized total logic swing. In this case, with reference to Fig. 1, when input A is at a high level with respect to Vrl, the OR output YA attains, VOH = ECL VCC - Vbe(Q4)

so, VNMH

= VOH - Vr]

Conversely, when input A is at a low level with respect to Vrl, the OR output YA attains, VOL

where, VI

and,

=ECL VCC - VI- Vbe(Q4)

=ICS*Rc

VNML

= Vr] - VOL

Usually, VNML = 300 mV is considered adequate at room temperature. The optimal reference voltage, Vr!, to be used inside the IC, can be developed as follows: Tandem Computers

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Vr1nom.

= VOHnom. - VNMHnom. = -760 mV - 300 mV

Then,

=-1060 mV

= VOHnom. - Vr1nom. = -760 mV + 1060 mV =300 mV VNMLnom. = Vr1nom. - VOLnom. =- 1060 mV + 600 mV + 760 mV =300 mV

VNMHnom. and, where,

VI = ICS*Rc

=600 mV

This design methodology ensures adequate VNMH and VNML values and creates an optimal total logic voltage swing, VI, without requiring a common mode resistor. It reduces the excessive VNMH of the conventional approach by developing a reference voltage optimized for internal voltage swing values. The benefits of this technique are a 30% reduction - from 845 mV to 600 mV - in the total logic swing, without any loss of high or low noise margin. Thus the delay performance of the circuit is improved significantly without requiring any increase in power dissipation.

lOOK OUTPUT DRIVER DESIGN - DIODE STACKING CONSIDERATIONS Our choice of the third design technique mentioned above places some new constraints on the design of a series-gated lOOK ECL output driver. Specifically, the internal reference voltage, Vrl, cannot be applied directly to the output current switch first level reference transistor, sincc~ this introduces a base/collector saturation hazard when the current ICM (Fig. 3) is switched to place the output at a low level. In order to eliminate this saturation hazard, Vr2 ( which is usually a second level reference) is applied as the first level reference voltage.

Vr2

=Vr1 - Vbe(Q9)

Consequently, the internal input voltage levels, which are normally centred around Vrl, are emitter follower shifted to switch properly against Vr2. The use of Vr2 as the primary reference requires the use of Vr3 as the second-level reference. In this case,

Vr3

= Vr2 - Vbe(Q13)

Note that Vr3 is offset from Vrl by 2 Vbe voltages, and thus represents a true third level seriesgating reference. This low voltage reference necessitates the use of a current mirror circuit in order to ensure an acceptable diode stacking for lOOK operation.

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ECL VCC

RC

!I2

ECL VCCA

U!

RC

llCH or ICL

A Q9

Q6

B

QIO

RT VR3

Qll

50 Ohms VTT (= .2V)

RIEFI

RIEF2

ICS

l

ECL VEE

Fig. 4:

Conventional Two Level lOOK ECL Output Driver

The diode stacking can be illustrated with reference to Fig. 4, which represents the conventional lOOK current source based approach as in [1], [2], and [3]. In this circuit, note that Vr2 and Vr3 follow ECL VCC, while VCS follows ECL VEE. So the lowest voltage on the collector of the current source transistor, Q8, with respect to ECL VCC, is:

Vc(Q8)

= ECL VCC -/VrJ/ - Vbe(Q12)

Now, the voltage at the base of this current source transistor, Q8, with respect to ECL VCC is:

Vb(Q8)

=ECL VCC -/ECL VEE/ + VCS

Therefore,

=

Vbc(Q8) [ECL VCC - IECL VEEI + VCS]- [ECL VCC - IVr3/- Vbe(Q12)] =ECL VCC -/ECL VEE/ + VCS - ECL VCC + /VrJ/ + Vbe(Q12) =-/ECL VEE/ + VCS + /Vr3/ + Vbe(Q12) Tandem Computers

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Let us nonnalize our reference voltages in tenns of the nominal bipolar transistor forward conduction voltage, Vbe. Further, let, Vbe = Vbe(Q12)

Then, VCS = -1.7 Vbe

and, IVr31 = - 3.4 Vbe Therefore,

=-JECL VEEj + VCS + jVr3j + Vbe(Q12) =- JECL VEEj + 1.7 Vbe + 3.4 Vbe + Vbe

Vbc(Q8)

=-JECL VEEj + 6.1 Vbe This means that,

ECL VEE = -6.1 Vbe + Vbc(Q8)

If we restrict the maximum forward bias voltage on the base collector junction of transistor Q8 to less than 0.5 Vbe, then, ECL VEE min.

= -6.1 Vbe + O. 5Vbe = -5.6 Vbe

The nominal forward conduction voltage of the ECL switch transistors, Vbe, varies inversely with temperature. In our design, transistors are designed to conduct nominal ICS with Vbe = 76Q mV at room temperature. Typically, this Vbe will vary with temperature at - -1.6mV10C. Temp. (oC)

-55

o

25 125

Vbe (mV) 890 800 760 600

Since our design is required to operate at 0 oC, we can defme the ECL VEE min. requirement. ECL VEE min. = -5.6 Vbe -5.6 * 800 mV

=

=-4.48 V

Typically, a VLSI IC device is housed in a package. In our case, a pin grid array (PGA) package is used. Studies indicate that we can expect an -20 mV IR voltage drop each on the ECL vec and ECL VEE pins. Also, the power distribution scheme on our IC creates a load-dependent IR gradient of -40 mVeach on the ECL VCC and ECL VEE busses. These IR drops must be properly accounted for in the ECL VEE min. requirement, ECL VEE min. = -4.48 V - 0.12 V = -4.60 V

The minimum ECL VEE in [3] is -4.7V. This ECL VEE min. requirement exceeds the lOOK ECL VEE min requirement of -4.2V at the package power inputs. Therefore, we cannot use the conventional circuit of Fig. 4 for our lOOK output driver.

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ECL VCC

RC

!I2

ECL VCCA

n!

RC

ICH

!

A

or

ICL

Q9 Q6

B

QlO Q2 VX

(VCS + CI» RCM Qll

VR3

RT 50 Ohms VTT (= -2V)

RIEFl

RIEF2

ICMI

.Q8

Q7

ECL VEE

Fig. 3:

Three Level Series Gated lOOK EeL Output Drivel'

We developed the schematic shown in Fig. 3 to improve the ECL VEE min. functionality of our VLSI IC design. The use of a current mirror effectively reduces the ECL VEE min. require:ments to acceptable levels. The diode stacking can be illustrated with reference to Fig. 3, which represents our lOOK approach. In this circuit, the lowest voltage on the collector of the (:urrent source transistor, Q8, with respect to ECL VCC, is: Vc(Q8)

=ECL VCC - /Vr3/ - Vbe(Q12)

Now, the voltage at the base of this current source transistor, Q8, with respect to ECL VCC is: Vb(Q8)

= ECL VCC - JECL VEEj + Vbe(Q8)

Therefore, Vbc(Q8) = [ECL VCC - /ECL VEE/ + Vbe(Q8)] - [ECL VCC - /Vr3/ - Vbe(Q12)] = ECL VCC - /ECL VEE/ + Vbe(Q8) - ECL VCC + /Vr3/ + Vbe(Q12) /ECL VEE/ + Vbe(Q8) + /Vr3/ + Vbe(Q12)

=-

Let us nonnalize our reference voltages in tenns of the nominal forward conduction voltage, Vbe. Further, let, Tandem Computers

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Vbe = Vbe(Q12) = Vbe(Q8) and,

/VrJ/

=- 3.4 Vbe

Therefore,

Vbc(Q8)

=-/ECL VEE/ + Vbe(Q8) + /VrJ/ + Vbe(Q12)

=-/ECL VEE/ + Vbe + 3.4 Vbe + Vbe =-/ECL VEE/ + 5.4 Vbe

This means that.

ECL VEE

= -5.4 Vbe + Vbc(Q8)

If we restrict the maximum forward bias voltage on the base collector junction of transistor Q8 to less than 0.5 Vbe. then.

ECL VEE min.

= -5.4 Vbe + O. 5Vbe = -4.9 Vbe

Our design is required to operate at 0 oC. we can define the ECL VEE min. requirement.

ECL VEE min.

= -4.9 Vbe

= -4.9 * 800 mV =-3.92 V

Accounting for IR voltage drops,

ECL VEE min.

= -3.92 V· 0.12 V = -4.04 V

This ECL VEE min. requirement is well within the lOOK ECL VEE min requirement of -4.2V at the package power inputs.

CIRCUIT DESIGN OPTIMIZATION· CONCLUSIONS We have shown the impact of internal ECL circuit optimization - with respect to logic swing and component count· on ECL output circuit design. The additional design constraints added by lOOK operation requirements are also addressed. We find that the resulting circuit requires a new framework for effective lOOK optimization of VOH, VOL temperature dependence. The following section develops this framework, and provides some guidelines for lOOK optimization.

lOOK OUTPUT TEMPERATURE COMPENSATION Thus far, we have presented design trade-offs based on functionality and diode stacking considerations, which have led to the use of an effectively three-level series-gated ECL output driver. In order to accommodate three-level deep series-gating, this circuit employed a current mirror technique to reduce maximum voltage diode stacking to within lOOK ECL VEE min. limits. lOOK output levels, as distinct from lOKH output levels. exhibit near-perfect independence from temperature and power supply voltage variations. In particular, as the IC junction temperature is varied from 0 degrees C to 125 degrees C, we find that the IC output lOOK levels remain within the temperature invariant bounds,

-880 mV