Low-Power Test in Compression-Based Reconfigurable Scan Architectures Sobeeh Almukhaizim∗
Mohammad Mohammad
Mohammad Khajah
Computer Engineering Dept Kuwait University
Computer Engineering Dept Kuwait University
Advanced Systems Dept KISR
[email protected] [email protected] [email protected] ABSTRACT
1.
Scan-based testing of integrated circuits produces significant switching activity during shift and capture operations, dissipating excessive power levels and, possibly, resulting in an unexpected behavior of the design. The problem is further accentuated in compression-based scan; as don’t care bits are exploited to compress test patterns, additional care bits are specified in the deliverable pattern, limiting the effectiveness of x-filling techniques. In this work, we propose a low-power test method for compression-based reconfigurable scan architectures. In addition to their key objective of minimizing Test Data Volume (TDV), we illustrate how the distribution of care bits in scan chains can be manipulated, using the different encoding configurations supported by the reconfigurable scan architecture, with the objective of reducing the number of transitions during test. Hence, peak and average power of shift and capture operations are effectively reduced. Experimental results, performed using one possible reconfigurable scan architecture as a case study, indicate that up to 50% power reduction is possible at the expense of an increase in TDV, while similar reduction levels are overhead-free in other reconfigurable scan architectures.
Scan designs have emerged as a viable solution to testing sequential circuits, as combinational ATPG tools are used in place of the complex sequential ones, cutting ATPG time and boosting fault coverage level. Thus, scan-based testing has become the standard test procedure for sequential circuits. Despite its wide adoption, however, a large number of scan cells coupled with a large set of test patterns reflect into inflated Test Data Volume (TDV) and prolonged Test Application Time (TAT), increasing test cost significantly. Therefore, scan-based testing is typically applied in a compression environment, where a few number of scan-in pins drive a larger number of internal scan chains. Due to onchip stimulus expansion on the input side, TDV is reduced. Furthermore, driving a larger number of internal scan chains reduces the depth of the scan chains, decreasing the number of shift (scan) operations per pattern and shortening TAT. Despite the advantages of compression-based scan, achieving maximum compression is limited by the following two problems. First, the distribution of care bits in test patterns determines their encodability, where unencodable patterns are delivered in serial scan mode (i.e., no compression). As the compression ratio increases, the probability of a conflict between care bits also increases, reducing the number of encodable patterns. To address this problem, several methods have been proposed to improve the encodability of patterns, and, among them, reconfigurable scan architectures are quite effective, yielding almost complete encodability [1, 2, 9, 10, 12, 13, 14]. Second, encodable patterns dissipate excessive power levels during shift, which is further accentuated in compression-based scan. The increase in peak and average number of transitions is proportional to the increase in the compression ratio. This is attributed to the exploitation of don’t care bits to reduce TDV, which produces additional care bits in the deliverable pattern, limiting the effectiveness of x-filling strategies. Excessive power levels during test may: (1) cause structural damage to the silicon or package, and (2) cause a large voltage drop that may lead to erroneous data transfer in test mode, thus invalidating test and leading to yield loss [11]. Therefore, peak and average power reduction methodologies targeting compression-based scan designs are of paramount importance, which has led to the development of numerous techniques in recent years [4, 5, 6, 7, 8, 15]. In this work, we present a low-power test method for compression-based reconfigurable scan architectures. The key idea exploited in this work is to select among the different encoding configurations (supported by the reconfig-
Categories and Subject Descriptors B.7.3 [Integrated Circuits]: Reliability and Testing
General Terms Design
Keywords Low-Power Test, Reconfigurable Scan Architectures, Scan, x-filling ∗ Part of this work has been conducted while the author was a Visiting Assistant Professor in the Electrical Engineering Department at Yale University.
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INTRODUCTION
urable scan architecture) such that the distribution of care bits in test patterns is manipulated to reduce the number of transitions in scan cells. Such manipulation of the distribution may aim at reducing shift power (i.e., by minimizing the number of transitions between test patterns/responses and their shifted versions), capture power (i.e., by minimizing the number of transitions between test patterns and their responses), or both simultaneously. As a case study, we examine the reconfigurable scan architecture proposed in [13] with the objective of reducing shift-in/shift-out power. Experimental results based on random and deterministic test sets indicate that peak and average power are reduced significantly at the cost of an increase in TDV. Similar power reduction levels are overhead-free in other reconfigurable scan architectures [10, 12]. The rest of the paper is organized as follows. We briefly review in section 2 reconfigurable scan architectures. Then, in section 3, we illustrate, using an example, how to employ the reconfigurable scan architecture to reduce test power. Next, we describe an encoding algorithm for reducing peak and average power in section 4. Finally, we evaluate in section 5 the proposed encoding method on the reconfigurable scan architecture in [13] as a case study, and conclude in section 6.
2. PREVIOUS WORK A plethora of research efforts have been expended in developing reconfigurable scan architectures that reduce TDV and/or TAT. In this section, we describe such designs that manipulate the distribution of care bits [1, 2, 9, 10, 12, 13, 14], implying their ability to reduce test power. The reconfigurable Illinois scan architecture in [9] utilizes two modes of operation. In the first mode, a scan-in pin is connected to k scan chains, where k is the compression ratio, and each chain consists of n scan cells, degenerating to the basic Illinois scan design. In the second mode, however, the length of k − 1 chains is increased to n + 1, while the length of the last chain reduces to n − k + 1. Thus, the two different scan modes change the dependency between the values of scan cells in slices. As a result, more patterns become encodable, reducing the number of patterns applied in serial scan mode and, hence, TDV and TAT. In [14], reconfiguration is achieved by varying the mapping of scan-in channels to scan chains (i.e., by supporting different encoding configurations). The decompressor is implemented using switches, and the problem of determining an effective switch configurations that achieve complete fault coverage is formulated as a graph coloring problem. Unlike the previous two approaches, the scan design in [1, 2] exploits the response of a pattern to partially generate the subsequent pattern. Scan cells are arranged in a grid, where a scan slice can be horizontal or vertical. The scan data is used to modify the contents of scan slices in one or all bit positions. Hence, the reduction in TDV and TAT is dependent on the number of bits that must be modified in the current response to generate the subsequent pattern. In [10], the mapping between scan-in pins and slices is performed based on an analysis of the compatibility relation of scan chains. Topological and compatibility analysis are used to maximize the number of encodable patterns, thereby reducing TDV and TAT. The scan architecture selects the minimum number of encoding configurations such that all faults can be detected in broadcast test mode, eliminating
the need for serial scan mode. Using this approach, any single scan configuration that encodes all slices in the pattern is selected. When the objective is to ensure 100% fault coverage using broadcast mode, however, the constraint of enforcing a single encoding configuration per pattern increases the ATPG overhead significantly. The method was later extended in [13], where an encoding configuration is selected on a per slice basis. As a result, the reductions in TDV and TAT improve significantly. Very recently, Align-Encode [12] was proposed to provide a deterministic per pattern control over the care bit distribution of test vectors, improving the effectiveness of any stimulus decompressor. Align-Encode is reconfigured on a per pattern basis to delay the shift-in operations in selected scan chains, where the number of delay cycles can be between zero and the maximum allowable value. The alignment control data is shifted in, using dedicated control channels, during shift cycles to align the scan cells for the subsequent test pattern. Hence, the scan slices are aligned in such a way that originally undeliverable test vectors become encodable. When a test pattern can be encoded by multiple alignment configurations, any valid encoding is selected. Experimental results illustrate the effectiveness of Align-Encode in obtaining almost complete encoding efficiency in industrial designs. All of the previous methods modify the distribution of care bits to reduce TDV and/or TAT. In the sequel, we demonstrate how the distribution of care bits can be manipulated with the objective of reducing test power as well.
3.
MOTIVATION
We first describe in section 3.1 the computation of TAT and TDV. Then, in section 3.2, we illustrate, using an example, how the selection of encoding configurations supported by a reconfigurable scan architecture can be exploited to reduce test power.
3.1
TAT and TDV Computation
The TAT required for shifting patterns in a given test set is computed according to the following equation: T AT = (N E + N U × C) × Sdepth
(1)
where N E (N U ) represents the number of encodable (unencodable) patterns, C is the compression ratio, and Sdepth is the length of the longest scan chain in the encoding configuration. The TDV is given by: T DV = T DVreconf igurable + T DVserial
(2)
which corresponds to the TDV required for applying the complete test set, wherein encodable patterns are applied in reconfigurable mode (test and control bits; compression), and unencodable patterns in serial scan mode (test bits only; no compression). T DVreconf igurable is given by: T DVreconf igurable =
N E Sdepth X X j=1
(Pi )
(3)
i=1
where Pi is the number of scan-in pins that deliver the data and control bits (for the selected encoding configuration) in shift cycle i for test pattern j. Finally, the TDV of serial scan is given by: T DVserial = N U × Pi × Sdepth
(4)
CNT=000000
MUX MUX
MUX
0
MUX
0
MUX
0
0
1
0
1
0
MUX
0
MUX
0
1
0
1
1
1
MUX
1
0
0
1
0
1
0
MUX
0
6 24
5 21
4 15
3 9
2 6
1 3
MUX
1
0
1
0
1
1
1
MUX
0
MUX
CNT=111000
0
0
1
0
1
0
P1=0101x1 P2=x01010 P3= ------
P1=0101x1
Shift Cycle # Total # of Tran.
1
0
1
1
1
1
0
1
1
1
1
1
0
1
0
0
0
1
1
1
1
0
0
1
0
1
1
1
1
1
0
0
0
1
0
6 16
5 14
4 12
3 9
2 6
1 3
P2=xx1010
Figure 1: Encodable Pattern: Minimize TDV Chain # 1 2 3 4 5 6
P3= x0x---
Shift Cycle # Total # of Tran.
Figure 2: Encodable Pattern: Minimize Shift Power
Sub-Pattern 0101xx xx1xx0 xxx1x1 xxxxxx xxxxxx x0x010
Table 1: Test Pattern Example
3.2 Example Assume that the test pattern in Table 1 is to be encoded using a reconfigurable scan architecture that supports the following two encoding configurations, where the control signal CN T indicates the configuration for a slice: 1. For higher compression, using 2 pins (P 1 is connected to chains 1, 3 and 5, and P 2 is connected to chains 2, 4 and 6). 2. For higher encodability, using 3 pins (P 1 is connected to chains 1 and 4, P 2 to chains 2 and 5, and 3 and 6). Consider the following encodability options, where postcompression x’s are repeat-filled to reduce shift power: • A single scan configuration that uses 2 pins only, as illustrated in Figure 1. The objective in this encoding is to minimize TDV. • Two scan configurations using 2 or 3 pins, as illustrated in Figure 2. The objective in this encoding is to reduce the number of transitions while shifting in the pattern. The pattern is encoded using 2 pins in the first 3 shift cycles (rightmost 3 scan slices), and 3 pins in the last 3 shift cycles (leftmost 3 scan slices). In Figures 1 and 2, the mapping of a value applied at a scan-in pin to a fragment within a scan slice is illustrated by
Objective Minimize TDV Minimize power
TAT 6 6
TDV 18 21
Peak 24 16
Avg. 13 10
Table 2: TAT, TDV, and Power Comparison shading the cells with the same color. Assuming a previously captured response of all 0’s prior to shift cycles, Table 2 summarizes the characteristics of both encodable patterns in terms of TAT, TDV, peak and average power, where TAT is given in terms of the number of shift cycles (i.e., the depth in Figures 1 and 2), TDV in bits (i.e., the number of data and control bits in Figures 1 and 2), and peak and average power in terms of the number of transitions in the scan cells. This example illustrates that, for this particular reconfigurable scan architecture, test power is reduced at the expense of a small increase in TDV, and without affecting TAT. We note that a tradeoff exists between TAT and power dissipation, as the delivery of patterns in serial scan mode would reduce test power at the expense of an increase in TAT and TDV. Trading off TAT for power reduction is discussed in the next section. At this point, we stress that manipulating the distribution of care bits in some reconfigurable scan architectures is achieved without affecting TDV or TAT [10, 12], yielding an overhead-free power reduction. Our conjecture is that power dissipation can be reduced in reconfigurable scan architectures, while noting that its cost is specific to the implementation under consideration. In this study, we opted to evaluate a non-trivial scan architecture [13], in order to analyze the tradeoff between TDV and power dissipation.
4.
REDUCING TEST POWER IN RECONFIGURABLE SCAN DESIGNS
Given a test set T and an optimization objective F , we describe next an algorithm for encoding test patterns in T
selected and applied in serial scan mode, with the objective of minimizing the cost function under optimization. In other words, each of the encoding configurations can be characterized and annotated with the corresponding design parameters. Hence, constraints on all of these parameters can be used to define various objectives, based on which, the best encoding configuration may be selected. The distribution of care bits can be manipulated with the objective of reducing shift power, capture power, or both simultaneously. Shift power is reduced by minimizing the number of transitions between test patterns/responses and their shifted versions, while capture power is reduced by minimizing the number of transitions between test patterns and their responses. Without loss of generality, we demonstrate in the next section how the manipulation of the distribution of care bits can reduce shift power (patterns and responses), without targeting capture power explicitly.
5.
CASE STUDY
We first describe the reconfigurable scan architecture in [13], used as a case study, along with the various encoding objectives. Subsequently, we present the power reduction results using random and deterministic test sets. Figure 3: Encoding Algorithm - Min(F ) using n encoding configurations such that F is reduced. An optimization objective F is a cost function that may reflect TAT, TDV, and/or power constraints. For each scan slice i in a test pattern t, encoding configuration j, 1 ≤ j ≤ n, is evaluated in terms of its validity (i.e., whether the slice is encodable). If the encoding is valid, the bit values are specified according to encoding configuration j, post-compression x’s are specified using repeat-fill, and the cost of the encoding configuration, Fj , is computed. If no encoding configuration is valid for any slice in pattern t, the pattern is delivered serially. Out of all supported encoding configurations, the one that minimizes Fj is selected1 . Finally, and once the encoding configurations for all slices are selected, TAT, TDV, and power statistics of the test set are updated, and the process is repeated for the remaining patterns in T . The encoding procedure is summarized in Figure 3. Unlike low-power compression-based ATPG methods [16, 17, 18], the proposed method is seamlessly integrated on-top of the design flow of compression-based reconfigurable scan designs, with no impact on the ATPG process. Once the test patterns are generated, the encoding algorithm is applied as a post-processing step. Additionally, higher power reduction levels can be obtained by increasing the number of encoding configurations, as well as by customizing the decompressor for a given test set [13]. Test patterns that dissipate excessive power levels can be delivered in serial scan mode, where x-filling strategies are very effective in reducing power, at the expense of an increase in TAT and TDV. Given constraints on all three parameters, the encoding procedure in Figure 3 can be modified such that a subset of compressible patterns is judiciously 1
When the objective is defined to model a subset of the possible constraints and several encoding configurations yield the minimum cost function, the configuration that minimizes unmodelled constraints is selected.
5.1
Setup
In these experiments, the mapping between pins and chains is as proposed in [13]: every mth chain shares a scan-in pin, where m = 2, 3, 5, or 7. Thus, the reconfigurable scan architecture utilizes seven scan-in pins at most to specify test bits, supports four encoding configurations, and utilizes two additional control pins for control data (to select the encoding configuration). The experiments are performed for three encoding objectives. The first encoding objective, Fcompression , aims at minimizing TDV, similar to that in [13]. Hence, and for each scan slice, the encoding configuration that minimizes the number of scan-in pins for test bits, i.e. Nbits , is selected. The second encoding objective, Fpower , aims at minimizing power, regardless of the increase in TDV. Therefore, a scan slice is encoded such that the number of scan cells that toggle relative to the proceeding slice, i.e. Ntran , is reduced. The final encoding objective, Fcost , attempts to reduce power and TDV simultaneously. A cost function, Fcost = Ntran × Nbits , is computed for each valid encoding configuration, and the one that minimizes Fcost is selected. In comparison to [13], the computational runtime increases for encodable patterns only due to: i) evaluating the validity of all encoding configurations (instead of the first valid configuration), and ii) computing the number of transitions for all valid configurations. While the runtime of the latter step is negligible, the number of encoding configurations directly affects the overall runtime. Nonetheless, and when four encoding configurations are supported (which results in, almost, complete encoding efficiency), the overall runtime increases by 2× relative to the basic encoding method in [13], ensuring the scalability of the proposed method for large circuits.
5.2
Results on Random Test Sets
The first set of experiments is performed using hypothetical test sets: 1000 patterns are randomly generated for a 32×32 and a 64×64 scan architecture. Since no netlist exists in these experiments, responses are assumed to be zero. The
x 95 96 97 98 99
% % % % %
Fcompression [13] TDV Peak Avg. 422587 478 143.33 308184 428 110.06 218322 374 73.22 147737 286 52.10 87577 192 34.90 Average Reduction
TDV 482698 371681 279723 219114 191520 -45.99%
Fpower Peak 294 188 178 192 96 45.97%
Avg. 71.59 58.18 42.96 30.11 14.81 47.66%
TDV 455842 341394 245302 175714 138186 -21.55%
Fcost Peak 294 290 288 208 176 25.87%
Avg. 86.46 69.70 52.73 40.40 24.39 31.38%
Table 3: Random Test Sets (No Responses): 32 × 32 Scan Architecture x 95% 96% 97% 98% 99%
Fcompression [13] TDV Peak Avg. 4088499 2004 917.46 3974975 1852 812.39 3073033 1724 683.71 1281028 1428 470.09 442832 972 181.40 Average Reduction
TDV 4088828 3981448 3132954 1442337 585464 -9.38%
Fpower Peak 996 1015 856 653 452 50.72%
Avg. 497.09 394.33 310.48 198.27 99.14 51.01%
TDV 4088696 3978637 3108231 1382801 515200 -5.11%
Fcost Peak 1220 1223 1086 874 768 33.98%
Avg. 606.34 490.11 390.12 248.36 124.88 38.97%
Table 4: Random Test Sets (No Responses): 64 × 64 Scan Architecture results are summarized in Tables 3 and 4. The first column indicates the percentage of x’s in the test set, and the next three major headings illustrate the TDV, peak, and average number of transitions for the three encoding objectives. The results support the following observations:
• The power reduction levels significantly deteriorate using Fpower and Fcost , where the power reduction is less than 25%. This indicates the significant impact of responses on test power, which dominates the number of transitions produced during shift.
• In the 32 × 32 scan architecture, Fpower reduces peak and average power by an average of almost 50% over Fcompression at the cost of 46% increase in TDV, while Fcost provides an average reduction of 26% (31%) in peak (average) power at the cost of a smaller 21% increase in TDV.
• Reducing the number of transitions produced while shifting out responses translates into higher power reduction levels, as evident by the results produced using Fresponse . On average, peak (average) power is reduced by around 25% (40%).
• The results improve in the 64 × 64 scan architecture, which uses the same 7 scan-in pins as in the 32 × 32 scan design (i.e., the tradeoff between TDV and power improves with higher compression). For an additional TDV of 5% (9%), Fcost (Fpower ) reduces power by an average of 35% (50%) over Fcompression . This observation supports the effectiveness of reconfigurable scan architectures in reducing test power for large designs.
• Similar to the results using hypothetical test sets, the tradeoff between TDV and power reduction improves when the number of scan chains increases from 32 to 64. • Overall, the increase in TDV is higher for the ISCAS circuits compared to that for the hypothetical test sets. We remind the reader that similar power reduction levels can be obtained in other reconfigurable scan architectures without affecting TDV [10, 12].
• The tradeoff between power and TDV improves when the number of supported encoding configurations increases; the results are omitted here due to page limitations.
5.3 Results on Deterministic Test Sets
6.
In this set of experiments, the test sets of the largest ISCAS89 combinational blocks are encoded based on the reconfigurable scan architecture described in section 5.1, where the responses are accounted for by logic simulating the delivered patterns to obtain their responses. The results are summarized in Tables 5 and 6. Post-compression x’s are specified using repeat-fill for the encoding objectives illustrated in the first 3 major headings. The last major heading, Fresponse , corresponds to the objective of selecting encoding configurations that maximize the number of 0’s in the delivered pattern, which has been shown to reduce the number of transitions produced while shifting out the response [3]. The results support the following observations:
Reconfigurable scan architectures have been previously proposed to address encodability challenges in compressionbased scan testing. In this work, we illustrate how different encoding configurations supported by a reconfigurable scan architecture can be exploited to reduce test power. While such power reduction is overhead-free in many reconfigurable scan architectures, we evaluate, as a case study, one nontrivial implementation wherein each encoding configuration necessitates a different number of test bits, i.e., a tradeoff exists between compression and power. Even for such a scan architecture, experimental results using random and deterministic test sets indicate that peak and average power are reduced significantly at the expense of an increase in TDV.
CONCLUSIONS
Circuit Name s9234 s13207 s15850 s38417 s38584
Fcompression [13] TDV Peak Avg. 125211 151 68.53 173378 334 117.45 159672 272 84.02 1537662 814 343.05 994920 769 232.62 Average Reduction
TDV 148724 390267 351611 3222757 2415343 -103.29%
Fpower Peak 127 325 268 812 760 4.30%
Avg. 58.38 92.17 57.46 290.82 180.36 21.13%
TDV 129644 268447 265116 2049007 1478447 -41.25%
Fcost Peak 151 333 272 823 752 0.28%
Avg. 64.70 101.34 67.10 316.17 204.70 11.85%
TDV 146578 294117 271846 2429426 1778364 -58.74%
Fresponse Peak 122 220 162 740 393 30.35%
Avg. 55.51 61.05 43.33 194.06 120.48 41.42%
Table 5: ISCAS89 Test Sets (With Responses): 32 Scan Chains Circuit Name s9234 s13207 s15850 s38417 s38584
Fcompression [13] TDV Peak Avg. 214410 183 84.32 119059 342 127.83 151404 333 100.66 1588046 878 390.72 582510 760 262.75 Average Reduction
TDV 225263 223789 257821 2495401 1415280 -72.68%
Fpower Peak 145 332 285 834 764 8.52%
Avg. 70.27 98.59 65.26 318.33 202.87 23.22%
TDV 215835 151061 198538 1773183 815461 -22.07%
Fcost Peak 183 340 295 850 760 3.04%
Avg. 81.18 112.03 79.87 359.87 233.39 11.18%
TDV 224358 180945 214688 2061744 998763 -39.94%
Fresponse Peak 139 319 242 806 505 19.97%
Avg. 70.59 74.50 56.21 231.22 141.83 37.81%
Table 6: ISCAS89 Test Sets (With Responses): 64 Scan Chains
Acknowledgements The first author would like to thank Jing Ying and Xiaoyu Ma, from Yale University, for their early contribution in the experimentation of this study. This work was supported by Kuwait University, Research Grant No. EO04/09.
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