Modeling and Control Design of the Interleaved Double ... - IEEE Xplore

IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS, VOL. 60, NO. 8, AUGUST 2013

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Modeling and Control Design of the Interleaved Double Dual Boost Converter Fellipe S. Garcia, Member, IEEE, José Antenor Pomilio, Senior Member, IEEE, and Giorgio Spiazzi

Abstract—The interleaved double dual boost (IDDB) is a non-isolated step-up dc–dc converter capable of high voltage gain and suitable to high-power applications. In this paper, the modeling and control design of this converter, valid for an arbitrary number of phases, is presented. The developed approach is then applied to a six-phase IDDB, and experimental results are obtained with a prototype operating with an input voltage of 60 V, an output voltage of 360 V, and with a nominal output power of 2.2 kW. The applications of this converter include electrical vehicles and renewable energy conversion. Index Terms—Control design, dc–dc power converters, electric vehicles, renewable energy.

I. I NTRODUCTION

T

HE GROWING use of renewable energy sources brings new challenges to the energy conversion technology. One of these challenges is related to the fact that some devices that store or produce electrical energy (e.g., batteries, ultracapacitors, fuel cells, and solar panels) are built using low-voltage cells, usually connected in series in order to attain a reasonable voltage. The connection of a large number of cells in series increases the complexity of the system and may reduce its performance, because of the differences among cells (e.g., fabrication variations) and the different working conditions (e.g., temperature). In addition, those sources of electrical energy have a significant variation in the output voltage depending on several factors as, for example, the output current, the state of charge, and the solar radiation. In typical applications, such as driving electrical motors or injecting power into the grid, it is usually necessary or convenient to use a relatively high and stable voltage. When this is the case, a step-up converter can be used to increase the source’s voltage to the level required by the application and to produce a stable output voltage despite variations on the source’s voltage. Manuscript received October 10, 2011; revised January 27, 2012; accepted March 25, 2012. Date of publication June 8, 2012; date of current version April 11, 2013. This work was supported in part by Fundação de Amparo á Pesquisa do Estado de São Paulo, by Conselho Nacional de Desenvolvimento Científico e Tecnológico, by Coordenação de Aperfeiçoamento de Pessoal de Nível Superior, and by Fundo de Apoio ao Ensino, à Pesquisa e à Extensão. F. S. Garcia was with the University of Campinas, Campinas 13083-852, Brazil. He is now with Ekion Electric Vehicle Technologies, Campinas 13083866, Brazil (e-mail: [email protected]). J. A. Pomilio is with the University of Campinas, Campinas 13083-852, Brazil (e-mail: [email protected]). G. Spiazzi is with the University of Padova, 35131 Padova, Italy (e-mail: [email protected]). Color versions of one or more of the figures in this paper are available online at http://ieeexplore.ieee.org. Digital Object Identifier 10.1109/TIE.2012.2203770

Fig. 1. IDDB with two phases.

As an example of application, consider the power electronics in the Toyota Prius, described in [1]. According to this reference, the nominal battery voltage is 206.1 V, and the inverter dc link has a maximum voltage of 500 V. In order to step-up and regulate the DC-link voltage, a classical boost converter was used. This paper explores a topology proposed with the objective of creating a higher voltage gain in comparison with the classical boost converter, i.e., the interleaved double dual boost (IDDB) converter [2]–[6]. This topology was chosen among others that also have highgain properties [7]–[15], because of the possibility of phase interleaving that allows the converter to be scaled to high-power applications. An interesting property of this topology is that the components (switches and capacitors) of the converter can be sized to a voltage lower than the output voltage. This paper presents the linearized dynamic model of the multiphase IDDB, including the problem of parameter dispersion. The results show that the model differs from that of the conventional interleaved boost and that a reduced-order model is a good approximation of the system behavior. II. M ODELING OF THE T WO -P HASE C ONVERTER A. Topology The IDDB with two phases is shown in Fig. 1, where vin is the input voltage and the resistor Ro represents the load. Each of the two phases of the converter is composed by one inductor and its corresponding pair of switches, e.g., phase 1 is comprised by the inductor L1 and switches T1 , D1 and T2 , D2 . Phase 1 and capacitor C1 are here denoted by “module 1,” while phase 2 and capacitor C2 are here denoted by “module 2.”

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The system has only one input, here defined as u = [Vin ].

(6)

Using the state-space averaging method [2] and using the notation δ i = (1 − δi ), the average system matrix is given by ⎤ ⎡ −R −δ 1 0 0 L1 L1 ⎢ δ1 −1 −1 ⎥ ⎥ ⎢ C 0 R o C1 R o C1 ⎥ 1 ⎢ (7) A2_ph = ⎢ −R2 −δ 2 ⎥ 0 ⎣ 0 L2 L2 ⎦ 0

Fig. 2. Two-phase IDDB with ideal switches.

The resistors R1 and R2 represent the parasitic resistance of the inductor and of the switches. This version of the converter where every switch is implemented with a transistor and a diode allows bidirectional power flow, as usually needed for the interface with energy storage devices as batteries and ultracapacitors. The output voltage vo (i.e., the voltage at the load Ro ) is given by vo = v1 + v2 − vin .

−1 R o C2

while the input matrix is given by  1 1 B 2_ph = L1 R o C 1

δ2 C2

1 L2

−1 R o C2

1 Ro C2

 .

(8)

Now, a perfect symmetry among the phases will be considered, i.e.,

(1)

L1 = L 2 = L

(9)

R1 = R2 = R

(10)

C1 = C2 = C.

(11)

Using (1), neglecting all the losses in the converter (R1 = R2 = 0) and with the hypothesis that the phases are operating in continuous conduction mode with the same duty cycle (δ), it can be shown that the static gain of the converter is

In Section V, the validity of approximations (9)–(11) is discussed. In addition, the same voltage reference is going to be used for the voltage of both output capacitors, resulting in

vo 1+δ . = vin 1−δ

V1 = V2 = V.

(2)

The input current of the converter (i.e., the current delivered by the source vin ) is given by iin = i1 + i2 − io

(3)

where io = v0 /R0 is the output current of the converter.

When condition (12) is taken into account, the system matrix can be written as ⎤ ⎡ −δ 1 −R 0 0 L L ⎥ ⎢ δ1 −2 ⎢ C 0 0 ⎥  Ro C ⎥. ⎢ (13) A2_ph = ⎢ −δ 2 ⎥ −R 0 0 ⎣ L L ⎦ 0

0

B. Converter Model and Order Reduction The two-phase IDDB with ideal switches is shown in Fig. 2. It is here defined that the duty cycle δi of the switch Si is referred to as the position that connects the inductor in parallel with the source (vin ). Notice that this definition implies that the duty cycle is related to the conduction of lower transistor for the switch S1 and to the conduction of the upper transistor for the switch S2 . The state-space model of the converter can be written as x˙ = Ax + Bu.

(4)

Considering the two-phase IDDB converter, the system is order four, and the state vector x can be written as in (henceforth, capital letters will be used to represent the average values of the variables) x2_ph = [I1

V1

I2

V 2 ] .

(5)

(12)

δ2 C

−2 Ro C

For the purpose of the control design, the system can now be written as two independent systems of order two, one for each module, the first of them having the following state vector: x2_ph = [I

V ] .

(14)

The reduced system matrix and the reduced input matrix are then given by 

 A2_ph_red =

−R L δ C

−δ L −2 Ro C

B 2_ph_red =

1 L 1 Ro C

.

(15)

This reduced-order system represents a dynamic model for the current of one phase and the voltage of the corresponding module, with the hypothesis that the other module and phase are behaving symmetrically. The variable δ represents the duty cycle, which is the same for both phases.

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The differential equation for the current in each of the N/2 inductors of module 1 is given by 1 d Ik = (−Rk Ik − V1 δ k + Vin ) dt Lk

(17)

for k = 1, . . . , N/2. The differential equation for the current in each of the N/2 inductors of module 2 is given by 1 d Ik = (−Rk Ik − V2 δ k + Vin ) dt Lk

(18)

for k = N/2 + 1, . . . , N . The differential equation for the voltage in C1 is given by ⎡⎛ N ⎞ ⎤ 2 d − V + V −V 1 ⎣⎝  1 2 in ⎦ V1 = (19) Ik δ k ⎠ + dt C1 Ro k=1

while the differential equation for the voltage in C2 is given by ⎡⎛ ⎞ ⎤ N  −V1 − V2 + Vin ⎦ d 1 ⎣⎝ V2 = . (20) Ik δ k ⎠ + dt C2 Ro N k=

Fig. 3.

+1

Now, by exploring the symmetry of the system, it is possible to reduce the order of the system, similar to what has been done with the two-phase IDDB converter model. Thus, consider that

Six-phase IDDB converter.

The model is concerned with the voltages in the capacitors C1 and C2 and not directly with the output voltage. Indeed, it is worthy to notice that the output voltage in this topology is directly dependent on the input voltage, through (1). This means that any input voltage variation reflects into the output voltage and can be compensated by adjusting accordingly the output capacitor voltage references, which requires the measurement of the input voltage. The attempt to control directly the output voltage, ignoring voltages V1 and V2 , would result in an imbalance of these voltages, breaking the symmetry of the converter. III. M ODELING OF THE N -P HASE C ONVERTER As noted, this topology allows the use of more than two phases. In order to maintain the symmetry of the converter, an even number of phases (here denoted by N ) are used. The objective of this section is to extend the modeling of the twophase converter to a general N -phase converter. The combination of the phases that are connected to the capacitor C1 and capacitor C1 itself forms the “module 1.” Analogously, the phases connected to the capacitor C2 and the capacitor C2 form the “module 2.” As an example of the converter with a larger number of phases, the six-phase IDDB converter is shown in Fig. 3. While (1) and (2) do not depend on the number of phases, the input current is now given by iin = i1 + i2 + · · · + iN − io .

2

(16)

The N -phase IDDB has N + 2 state variables, here chosen as the N inductor currents and the two capacitor voltages.

L1 = L 2 = · · · = L N = L

(21)

R1 = R2 = · · · = RN = R

(22)

C1 = C2 = C.

(23)

and

In Section V, the validity of approximations (21)–(23) is discussed. The voltage reference used for V1 and V2 is the same, so the control action, along with the symmetry of the converter, shall ensure that V1 = V2 = V.

(24)

Also, using the same current reference for the currents of each module, the current in every phase is the same, i.e., I1 = I2 = · · · = IN = I

(25)

and the duty cycle is the same for all phases, i.e., δ1 = δ2 = · · · = δN = δ.

(26)

Equations (17) and (18) can then be written as 1 d I = (−RI − V δ + Vin ). dt L In addition, (19) and (20) can then be written as  d 1 N δI −2V + Vin V = + . dt C 2 Ro

(27)

(28)

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TABLE I N OMINAL PARAMETERS

In the state-space form, the state vector is x = [I

V ]

(29)

while the system and input matrices are

  −δ −R L A = NLδ B = −2 2C

Ro C



1 L 1 Ro C

.

(30)

It is interesting to compare this result with the one obtained by the conventional N -phase interleaved boost converter [3]. By adopting the same assumptions of symmetry between phases, the reduced-order model of the N -phase interleaved boost is given by (31), with the state variables chosen as the current in one phase and the output voltage

  Aib =

−δ L −1 Ro C

−R L Nδ C

B in =

1 L

0

.

TABLE II N OMINAL E QUILIBRIUM P OINT

(31)

The main difference between the reduced-order models of the IDDB and the conventional interleaved boost is the presence in matrix B of a term depending on the load resistance. This term comes from the particular connection between the source and the load that also causes the presence of the coefficient 2 in the element a22 of matrix A, while the coefficient 1/2 in the element a21 is caused by splitting the phases between the two modules.

and  B1 = B2 = B =

X eq = −A−1 BU .

(32)

Using (30), the set of equilibrium points can be written as  

2+2δ Ieq 4R+N Ro (1−δ)2 X eq = (33) = 2R+N Ro (1−δ) Vin . Veq 4R+N R (1−δ)2 o

From (1) and (33), the relation between the output voltage and the input voltage is given by (34). Notice that (34) takes into account the resistive losses and therefore is more precise than (2) Vo N Ro (1 − δ 2 ) = Vin 4R + N Ro (1 − δ)2

(34)

Using the state-space averaging method [2], [4] and assuming the small-signal approximation, the equivalent linear system near the equilibrium point is given by  x˙ = A x + [(A1 − A2 )X + (B 1 − B 2 )U ] δ where

 −R A1 =

L

0

0

−2 Ro C

 −R

A2 =

L N 2C

−1 L −2 Ro C

(35)

(36)

1 Ro C

 .

(37)

Using (37), (35) can be simplified to  x˙ = A x + [(A1 − A2 )X] δ.

(38)

The transfer functions of the linearized system around the operating point are given by

A. Small-Signal Model The set of attainable equilibrium points of the converter is given by

1 L

H(s) = (sI − A)−1 (A1 − A2 )X eq .

(39)

Expression (39) can be developed into 

 (2Ro CVeq )S+[4Veq +N Ro (1−δ)Ieq ] Gid (s) 2Ro LCs2 +(2RRo C+4L)s+4R+N Ro (1−δ)2 = −N Ro LIeq s−N Ieq RRo +N Ro (1−δ)Veq Gvd (s) 2Ro LCs2 +(4RRo C+4L)s+4R+N Ro (1−δ)2 (40) where Gid (s) = I(s)/Δ(s) and Gvd (s) = V (s)/Δ(s). From (40), the transfer function Gvi (s) = V (s)/I(s) relating the voltage to the current can be derived as Gvi (s) =

V (s) −N Io LIeq s−N Ieq RRo +N Ro (1−δ)Ieq = . I(s) 2Ro CVeq s+4Veq +N Ro (1−δ)Ieq (41) IV. C ONTROL D ESIGN

In order to show the application of the model for the purpose of control design, a six-phase IDDB converter, as shown in Fig. 3, is considered. The converter’s parameters are presented in Table I. In practice, high values of duty cycle are undesirable because of high current and low efficiency, and therefore, the duty cycle was limited to 0.85. In order to compute the small-signal model of the converter, a nominal equilibrium point that belongs to the set defined by (33) is selected. This point is shown in Table II and indicated in Fig. 4.

GARCIA et al.: MODELING AND CONTROL DESIGN OF THE INTERLEAVED DOUBLE DUAL BOOST CONVERTER

Fig. 4.

Set of attainable equilibrium points for 0 ≤ δ ≤ 0.85.

Fig. 5.

Per-module per-phase model of the control loop.

Using the transfer function of the current to duty cycle, presented in (40), and of the voltage to current, presented in (41), the control loops can be designed, using current mode control [4]. The duty-cycle value is determined by the current controller (internal loop). The average current reference is generated by the voltage controller. The control diagram of the control of the voltage in one module and the current in one phase is shown in Fig. 5. The current-to-duty-cycle transfer function of (40) is evaluated by using the parameters of Tables I and II, resulting in the transfer function presented in Gid (s) =

407 × 103 (s + 134.3) I(s) = 2 . Δ(s) s + 352.5s + 8.9 × 105

(42)

The current controller and the voltage controller are chosen as a proportional–integral controller with a low-pass filter. The transfer function of the controllers is given by       ωp ωp ki ki s+ωz = (43) Gpi (s) = kp + s s+ωp s ωz s+ωp where kp is the proportional gain, ki is the integral gain, ωp is the pole angular frequency, and ωz = ki /kp is the zero angular frequency. In order to calculate the parameters of the current controller, the closed-loop cutoff frequency fci = 1 kHz ≈ fsw /10 and the phase margin P Mi = 80◦ are selected. The current controller [Gic (s)] is then designed according to the k-factor method [5], and the resulting parameters are kic = 10, 02 rad/s, ωzc = 663, 7 rad/s, and ωpc = 59 479 rad/s. Using (41), the voltage-to-current transfer function is evaluated and presented in (44). This transfer function is used in the design of the voltage controller Gvi (s) =

−0.123(s − 1.37 × 104 ) V (s) = . I(s) s + 134.3

(44)

The cutoff frequency of the voltage control loop must be much smaller than the cutoff frequency of the current control loop, in order to consider the latter as having unitary gain and zero phase when designing the former.

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Fig. 6. Control diagram of the implemented controllers.

The closed-loop cutoff frequency and the phase margin of the voltage control loop are selected as fcv = 100 Hz and P Mv = 80◦ . The voltage controller [Gvc (s)] is then designed according to the k-factor method [5], and the resulting parameters are kiv = 40.9 rad/s, ωzv = 107.7 rad/s, and ωpv = 3367 rad/s. The control loops were implemented digitally, based on digital current mode control [6]. The average current of each phase is measured by sampling the signal from the current sensor synchronized with the center of the pulsewidth modulation (PWM) pulse. In order to assure the conditions of equal average voltage in the capacitors (24) and of equal average currents in the phases of the same module (25), the same voltage reference is used for both capacitors and the same current reference is used for the three phases of the same module, as shown in the diagram of Fig. 6. Six current controllers (one for each phase) and two voltage controllers (one for each module) were implemented. The PWM blocks represent the PWM generators of the microcontroller. V. PARAMETER VARIATION E FFECTS The symmetry condition of the converter was utilized to reduce the order of the system and to simplify the analysis, according to (21)–(23). However, in practice, there are unavoidable component tolerances. In order to demonstrate the validity of the adopted simplifications, the full-system model has been considered, taking into account variations in the components. The transfer functions between the duty cycle and current in each phase were calculated using Mathworks MATLAB. The values of the components {L1 , . . . , L6 }, {R1 , . . . , R6 }, and {C1 , C2 } were randomly generated with a uniform distribution in the interval within ±20% of the nominal value presented in Table I.

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Fig. 7. Bode diagram of current loop gain transfer functions, for randomly distributed parameters.

Fig. 8. Experimental setup.

The process was repeated ten times, generating a total of 60 current-to-duty-cycle transfer functions. The resulting loop gains [Ti (s) = Gic (s) ∗ Gid (s)] with the controller designed for the nominal component values were calculated. The corresponding Bode plots are shown in Fig. 7. While the design value of the crossover frequency is 1 kHz, the actual value ranged between 839 and 1232 Hz (depending on the parameters randomly generated). The minimum phase margin is 79.37◦ , and the maximum phase margin is 80.45◦ , very close to the design value of 80◦ . This analysis supports the hypothesis of symmetry, because, for the design considered in this article, variations of the parameter values do not cause a significant change in the performance or the stability of the control loop that was designed for the ideal (nominal) case. The same procedure was adopted for the voltage control loop. The crossover frequency, with design value of 100 Hz, ranged from 76.7 to 129.4 Hz. The phase margin ranged from 72.6◦ to 86.3◦ , and the gain margin ranged from 24.1 to 29.3 dB. VI. E XPERIMENTAL R ESULTS The six-phase IDDB that was experimentally tested is shown in Fig. 8.

Fig. 9.

Experimental waveforms of the currents in the six phases.

The microcontroller is enclosed in the metallic box (A), for reduction of electromagnetic interference. The signals of the current and voltage sensors are received by the signal conditioning board (B) and transmitted to the microcontroller. The board (C) is an auxiliary power supply for the signal conditioning board. The microcontroller is programmed via the emulator Blackhawk USB2000 (D). All the power circuits of the converter (power semiconductors, inductors, capacitors, and sensors) are located in the boards shown in position (E). The control routines were implemented in a Texas Instruments Incorporated microcontroller, model TMS320F28335. The power switches were implemented using two parts of the integrated circuit IRAM20UP60A, manufactured by International Rectifier. The switching frequency of each phase of the converter was set at 11.1 kHz (T = 90 μs). The nominal operating points of the converter are vi = 60 V, vo = 360 V, and Po = 2200 W. The waveforms were acquired with a Tektronix DPO7054 and plotted with Mathworks MATLAB. The currents in the six phases are shown in Fig. 9. Because of the controller action, the currents of every phase have approximately the same average value. The variations in the peak-to-peak value and in the slope of the phase currents are mainly due to differences in the inductors. The ripple is significantly reduced in the input current of each module because of the proper phase displacement, as shown in Fig. 10. The six phases of the converter are displaced by 60◦ , while the three phases of each module are displaced by 120◦ . The input current, filtered by the input capacitors, is shown in Fig. 11, along with the output current. The same effect of ripple cancelation can be noticed in the voltages of each module, which are summed in (1) to produce the output voltage, as shown in Fig. 12. Fig. 13 shows the efficiency of the converter for the input voltage in the range of 40–100 V, in steps of 20 V. The output power ranged from 200 to 3.6 kW, in steps of 200 W (notice that higher input voltage allowed the converter to operate at higher output power). At the nominal operating point, the efficiency of the converter was measured as 92.8%.

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Fig. 10. Experimental waveforms of the currents in the converter. Fig. 14. Load changes from 1013 to 2023 W.

Fig. 11. Input and output currents.

Fig. 15. Load changes from 2023 to 1013 W

Fig. 12. Measurement of input, output, and module voltages.

A positive step load change was applied to the converter, with the load changing from 1013 to 2023 W, and the result is shown in Fig. 14. The opposite step load change, with the load changing from 2023 to 1013 W, is shown in Fig. 15. For the positive load step of Fig. 14, the voltage variation (undervoltage) was approximately 4% and the settling time (95%) was approximately 20 ms, while for negative load step of Fig. 15, the voltage variation (overvoltage) was approximately 8.5% and the settling time (95%) was approximately 25 ms.

VII. C ONCLUSION

Fig. 13. Efficiency in function of the output power and input voltage for the output voltage of 360 V.

This paper has described the modeling of the general N -phase IDDB and the derivation of its small-signal model. The control design for this converter was illustrated for a sixphase IDDB, which was experimentally verified. The symmetry of the converter and the control action were utilized in order to reduce the complexity of the model, while the validity of the approximations was discussed. Experimental results were provided in support of the theoretical analysis.

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[18] R. W. Erickson and D. Maksimovic, Fundamentals of Power Electronics. New York: Springer-Verlag, 2000. [19] H. D. Venable, “The k factor: A new mathematical tool for stability analysis and synthesis,” in Proc. 10th Int. Solid State Power Electron. Conf., San Diego, CA, 1983, pp. H1–H12. [20] S. Buso and P. Mattavelli, Digital Control in Power Electronics. Princeton, NJ: Morgan & Claypool, 2006.

Fellipe S. Garcia (M’11) was born in Campinas, Brazil, in 1984. He received the B.S. and M.S. degrees in electrical engineering from the University of Campinas, Campinas, Brazil, in 2007 and 2010, respectively. In 2009–2010, he was a Visiting Researcher with the University of Padova, Padova, Italy. Since 2010, he has been with Ekion Electric Vehicles Technologies, Campinas, Brazil, where he develops power converters for electric vehicle application. His main interests include electric vehicles, renewable energy sources, nonlinear control, and dc–dc converter design and control.

José Antenor Pomilio (M’92–SM’02) was born in Jundiaí, Brazil, in 1960. He received the B.S., M.S., and Ph.D. degrees in electrical engineering from the University of Campinas, Campinas, Brazil, in 1983, 1986, and 1991, respectively. From 1988 to 1991, he was the Head of the Power Electronics Group, Brazilian Synchrotron Light Laboratory. He was a Visiting Professor with the University of Padova, Padova, Italy, in 1993 and with the University of Rome III, Rome, Italy, in 2003. He is a Professor with the School of Electrical and Computer Engineering, University of Campinas, where he has been teaching since 1984. His main interests are switching-mode power supplies, power-factor correction, and active power filters. Dr. Pomilio was the President of the Brazilian Power Electronics Society in 2000–2002 and a member of the Administrative Committee of the IEEE Power Electronics Society in 1997–2002. He is currently an Associate Editor of the IEEE T RANSACTIONS ON P OWER E LECTRONICS.

Giorgio Spiazzi received the B.S. degree (cum laude) in electronic engineering in 1988 and the Ph.D. degree in industrial electronics from the University of Padova, Padova, Italy. In 1993, he started working as a Researcher with the Department of Information Engineering, University of Padova, where he has been an Associate Professor since 2001. His main research interests are in the fields of high-power-factor rectifiers, softswitching techniques, electronic ballasts, renewable energy applications, and electromagnetic compatibility in power electronics.