Modeling and Design of Power-Factor-Correction

The Hong Kong Polytechnic University Department of Electronic and Information Engineering

Modeling and Design of Power-Factor-Correction Power Supplies by

Grace Miu-Lai CHU

A thesis submitted in partial fulfillment of the requirements for the degree of Doctor of Philosophy

July 2009 i

Certificate of Originality I hereby declare that this thesis is my own work and that, to the best of my knowledge and belief, it reproduces no material previously published or written, nor material that has been accepted for the awards of any degree or diploma, except where due acknowledgement has been made in the text.

(Signed)

Grace Miu-Lai CHU

(Name of Student)

ii

To Devon

iii

Abstract Nowadays, with the increasing concern in environmental protection and energy conservation, more emphasis has been put in maintaining the power quality of AC power lines and further boosting the efficiency of end-user devices. This demands a high power factor in the end-user device. Following this worldwide trend, the tightening of international standards and regulations on current harmonics limits further increases such demands in the off-line devices’ market. Power factor correction (PFC) is an inevitable solution to address these ever-increasing demands for high power quality in the delivery of electric power from the generating ends to the end users. In medium to high power off-line applications, PFC has even become a mandatory feature in order to comply with the tightened regulatory standards. Typically a PFC power supply consists of two stages. The first stage is the boost PFC pre-regulator which is responsible for providing PFC function. The cascading second stage is a dc-dc converter which is responsible for providing tight output regulation and fast transient response. The purpose of this thesis is to address the stability and performance issues of such a system. A simple yet effective modeling solution will be introduced to analyze and predict the occurrence of the line-frequency instability phenomenon. The criteria for the onset of this phenomenon and its effect on the power factor will be illustrated. Experimental results will be provided to verify the theoretical analysis. In addition, the thesis will cover stability analysis of PFC pre-regulators terminated with other load terminations for completeness and relevance of the study. After that, we will focus on control design methodologies for improving system performances. A unified and systematic approach will be introduced to generate robust control rules for boost PFC converters. Under this approach, the control parameters can be designed according to the desired steady-state and transient-response performances. Experiments are conducted and simulations are performed to evaluate the performances of the resulting

iv

control solutions. Furthermore, the current loop control will be re-examined from a sliding mode viewpoint. This approach results in additional constraints for the design of control parameters and leads to a better understanding of the relationship between the sliding-mode approach and other common derivation approaches. This thesis contains eight chapters. The first two chapters provide an introduction of the boost PFC converter and an overview of the development of PFC technologies. The rest of the thesis reports the tasks accomplished in this research project. These tasks share a common objective, which is to provide useful guidelines to facilitate the control design of boost PFC power systems for ensuring stability and at the same time embracing performance improvement. For each task, theoretical derivation, analysis and practical implementation methods will be detailed. Simulation and experimental results will also be presented to verify the theoretical analysis. It is hoped that this thesis can serve as a useful reference for practicing engineers to design high-performance PFC converters.

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Publications Journal Papers 1. G. Chu, C. K. Tse, and S. C. Wong, “Line-frequency instability of PFC power supplies,” IEEE Transactions on Power Electronics, vol. 24, no. 2, pp. 469-482, Feb. 2009. 2. G. Chu, C. K. Tse, S. C. Wong, and S. C. Tan, “A unified approach for the derivation of robust control for boost PFC converters,” IEEE Transactions on Power Electronics, to appear. 3. G. Chu, S. C. Tan, C. K. Tse, and S. C. Wong, “Robust current control for boost PFC converters from a sliding mode viewpoint,” International Journal of Circuit Theory and Applications, submitted.

Conference Papers 1. G. Chu, S. C. Tan, C. K. Tse, and S. C. Wong, “General control for boost PFC converters from a sliding mode viewpoint,” IEEE Power Electronics Specialists Conference, (PESC 2008), Rhodes, Greece, pp. 4452-4456, Jun. 2008. 2. G. Chu, C. K. Tse, and S. C. Wong, “A model for stability study of PFC power supplies,” IEEE Power Electronics Specialists Conference, (PESC 2007), Florida, USA, pp. 1298-1303, Jun. 2007. 3. O. Dranga, G. Chu, C. K. Tse, and S. C. Wong, “Stability analysis of two-stage PFC power supplies,” IEEE Power Electronics Specialists Conference, (PESC 2006), Jeju, Korea, pp. 594-598, Jun. 2006. vi

Acknowledgements First of all, I would like to express my immense gratitude to my supervisor Prof. Michael Tse. He has offered me a valuable chance to learn from him and to experience academic research. Under his patient guidance and sustained encouragement, my knowledge has been enriched and my horizon broadened not only in the field of power electronics, but also in academic publication, technical writing and presentation. I would also like to thank my co-supervisor Dr. S. C. Wong. His informative instructions and stimulating advices have helped me overcome numerous difficulties in my study. Under his guidance I have acquired many practical skills in simulation and analysis. I would also like to thank Dr. Siew-Chong Tan for his kind advices and constructive suggestions on my research works. All these knowledge and experiences will not only be useful to my future career, but also be beneficial to my whole life. These four years of study in the EIE department have been a memorable experience, for I have met wonderful friends who are always kind and helpful. They include Martin Cheung, Alan Lun, Dillian Wong, Ben Cheng, Chen Xi, Junfeng Sun, Xiaohui Qu, Sufen Chen, Siu-Hong Wong, Herbert Iu, Ming Li, Xiaofan Liu, Jing Liu, Paula Wu, Gary Tam, King-Hong Chung, Kwok-Wai Wong and Shu-Yuen Lam. They have shared with me their valuable research experiences and provided a lot of ideas and assistance to my study. I also wish to thank Mr. S. C. Ip for his help in building the hardware for my research project. Finally, many thanks go to my family, whose encouragement and support have given me the strong will to accomplish the study. Without these people, the completion of this research project is next to impossible. Their kindness and help will always be remembered.

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Contents

Abstract

iv

Publications

vi

Acknowledgements

vii

1 Introduction

1

1.1

Motivation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

1

1.2

Literature Review . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2

1.2.1

Topologies for PFC converters . . . . . . . . . . . . . . . . .

3

1.2.2

Control Methods . . . . . . . . . . . . . . . . . . . . . . . .

5

1.2.2.1

Multiloop multiplier approach . . . . . . . . . . . .

5

1.2.2.2

Cycle-by-cycle integration approach . . . . . . . .

7

1.2.2.3

Single loop approach . . . . . . . . . . . . . . . .

9

1.2.2.4

Sliding mode control approach . . . . . . . . . . .

9

1.2.3

Improvements in ACM Control . . . . . . . . . . . . . . . .

11

1.2.4

Modeling and Stability analysis . . . . . . . . . . . . . . . .

12

1.2.4.1

The quasi-static approach . . . . . . . . . . . . . .

12

1.2.4.2

The continuous averaged model . . . . . . . . . . .

13

1.2.4.3

The discrete time model . . . . . . . . . . . . . . .

14

Objective . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

15

1.3

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1.4

Outline of the Thesis . . . . . . . . . . . . . . . . . . . . . . . . . .

2 Overview of the Boost PFC Converter

15 18

2.1

Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

18

2.2

The Power Factor . . . . . . . . . . . . . . . . . . . . . . . . . . . .

18

2.3

Regulations and Standards . . . . . . . . . . . . . . . . . . . . . . .

23

2.3.1

IEC61000-3-2 . . . . . . . . . . . . . . . . . . . . . . . . .

23

2.3.2

IEEE STD 519-1992 . . . . . . . . . . . . . . . . . . . . . .

23

2.3.3

RTCA DO-160 . . . . . . . . . . . . . . . . . . . . . . . . .

24

Fundamentals of the Boost PFC Converter . . . . . . . . . . . . . . .

27

2.4.1

Basic switching operation . . . . . . . . . . . . . . . . . . .

27

2.4.2

The operation mode . . . . . . . . . . . . . . . . . . . . . .

28

2.4.3

PFC operation under ACM control . . . . . . . . . . . . . . .

31

2.5

Problems in Modeling and Analysis . . . . . . . . . . . . . . . . . .

35

2.6

Modeling and Analysis of the Boost PFC Converter . . . . . . . . . .

35

2.6.1

Inner current loop modeling . . . . . . . . . . . . . . . . . .

36

2.6.2

Outer voltage loop modeling . . . . . . . . . . . . . . . . . .

38

General Design Procedures . . . . . . . . . . . . . . . . . . . . . . .

44

2.7.1

Design of the power stage . . . . . . . . . . . . . . . . . . .

44

2.7.2

Design of control parameters . . . . . . . . . . . . . . . . . .

45

2.7.2.1

Protection functions and house-keeping functions .

45

2.7.2.2

Compensation of current amplifier . . . . . . . . .

46

2.7.2.3

Compensation of voltage amplifier . . . . . . . . .

47

Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

48

2.4

2.7

2.8

3 Line-Frequency Instability of PFC Power Supplies

49

3.1

Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

49

3.2

Line-frequency Instability: A Sustained Oscillation Viewpoint . . . .

52

ix

3.3

Modeling with Constant Power Sink . . . . . . . . . . . . . . . . . .

53

3.4

Derivation of Stability Criterion . . . . . . . . . . . . . . . . . . . .

55

3.4.1

Generalized averaged model . . . . . . . . . . . . . . . . . .

55

3.4.2

Fourier series expansion . . . . . . . . . . . . . . . . . . . .

56

3.5

Design-Oriented Stability Boundaries . . . . . . . . . . . . . . . . .

61

3.6

Simulation Results . . . . . . . . . . . . . . . . . . . . . . . . . . .

64

3.7

Experimental Measurements . . . . . . . . . . . . . . . . . . . . . .

68

3.7.1

Line-frequency instability and its detection . . . . . . . . . .

69

3.7.2

Comparison of resistor terminated and constant-power-sink ter-

3.7.3

minated PFC Converters . . . . . . . . . . . . . . . . . . . .

72

Verification of the stability boundaries

. . . . . . . . . . . .

72

3.8

Applications

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

76

3.9

Discussion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

78

3.10 Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

80

4 Line-Frequency Instability with Constant Current Sink Termination

81

4.1

Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

81

4.2

Derivation of Stability Criterion . . . . . . . . . . . . . . . . . . . .

82

4.3

Stability Boundaries

. . . . . . . . . . . . . . . . . . . . . . . . . .

85

4.4

Simulation Results . . . . . . . . . . . . . . . . . . . . . . . . . . .

88

4.5

Further Comparison . . . . . . . . . . . . . . . . . . . . . . . . . . .

90

4.6

Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

92

5 The Feedback Linearization Approach for Current Loop Control 5.1

93

Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

93

5.1.1

Control objectives of PFC converters . . . . . . . . . . . . .

94

5.1.2

Decoupling of the dynamics . . . . . . . . . . . . . . . . . .

95

5.1.3

Problems addressed by the derivation approach . . . . . . . .

96

x

5.2

Feedback Linearizatoin . . . . . . . . . . . . . . . . . . . . . . . . .

97

5.2.1

Basic idea of feedback linearization . . . . . . . . . . . . . .

97

5.2.2

Applications of feedback linearization in the control of power converters . . . . . . . . . . . . . . . . . . . . . . . . . . . .

99

5.2.3

Advantages of feedback linearization . . . . . . . . . . . . .

99

5.2.4

Limitations of feedback linearization . . . . . . . . . . . . . 100

5.3

Derivation of the Current Loop Control . . . . . . . . . . . . . . . . 101

5.4

Frequency Response Analysis . . . . . . . . . . . . . . . . . . . . . 103

5.5

Practical Implementation . . . . . . . . . . . . . . . . . . . . . . . . 106

5.6

Experimental Results . . . . . . . . . . . . . . . . . . . . . . . . . . 109

5.7

Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111

6 The Feedback Linearization Approach for Voltage Loop Control 6.1

114

Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114 6.1.1

Problems of the existing voltage loop control . . . . . . . . . 114

6.1.2

Application of the feedback linearization to the voltage loop control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115

6.2

Derivation of the Voltage Loop Control . . . . . . . . . . . . . . . . 116

6.3

Sample-and-Hold Function . . . . . . . . . . . . . . . . . . . . . . . 118

6.4

Frequency Response Analysis . . . . . . . . . . . . . . . . . . . . . 119

6.5

Transient Response . . . . . . . . . . . . . . . . . . . . . . . . . . . 122

6.6

Practical Implementation . . . . . . . . . . . . . . . . . . . . . . . . 124

6.7

Experimental Results . . . . . . . . . . . . . . . . . . . . . . . . . . 127 6.7.1

6.8

Voltage loop control evaluation . . . . . . . . . . . . . . . . 127

Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129

7 Re-Visit of Robust Current Control From a Sliding Mode Viewpoint 7.1

132

Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132 xi

7.2

Sliding Mode Control . . . . . . . . . . . . . . . . . . . . . . . . . . 133 7.2.1

Main idea of sliding mode control . . . . . . . . . . . . . . . 133

7.2.2

General SM control derivation . . . . . . . . . . . . . . . . . 134

7.3

Theoretical Derivation . . . . . . . . . . . . . . . . . . . . . . . . . 135

7.4

The Existence Condition . . . . . . . . . . . . . . . . . . . . . . . . 139

7.5

7.4.1

Saturation of duty cycle . . . . . . . . . . . . . . . . . . . . 139

7.4.2

Transient response of the current error . . . . . . . . . . . . . 140

Practical Implementation . . . . . . . . . . . . . . . . . . . . . . . . 142 7.5.1

Modulation methods . . . . . . . . . . . . . . . . . . . . . . 142

7.5.2

Trailing edge modulation . . . . . . . . . . . . . . . . . . . . 142

7.5.3

Leading edge modulation . . . . . . . . . . . . . . . . . . . . 143

7.5.4

Implementation using TEM controllers . . . . . . . . . . . . 144

7.5.5

Implementation using LEM controllers . . . . . . . . . . . . 146

7.6

Simulation Results . . . . . . . . . . . . . . . . . . . . . . . . . . . 151

7.7

Discussion

7.8

Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155

8 Conclusion 8.1

159

Work Accomplished . . . . . . . . . . . . . . . . . . . . . . . . . . 159 8.1.1

Investigation of line-frequency instability in boost PFC converters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159

8.1.2

Introduction of a unified approach to derive robust control for boost PFC converters . . . . . . . . . . . . . . . . . . . . . . 161

8.1.3

Re-examination of robust control from a sliding mode viewpoint162

8.2

Future Research

. . . . . . . . . . . . . . . . . . . . . . . . . . . . 162

8.3

Contributions of the Thesis . . . . . . . . . . . . . . . . . . . . . . . 163

xii

List of Figures 1.1

A review of the boost PFC converter in terms of modeling approach, stability analysis and control methodology.

2.1

. . . . . . . . . . . . . .

3

The decomposition of the input current waveform into 50 Hz fundamental component and its higher order harmonics. The y-axis is input current in [A] and the x-axis is time in [s] . . . . . . . . . . . . . . .

2.2

The overall power factor consists of (a) the displacement factor and (b) the distortion factor . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.3

27

Inductor current waveform during (a) CCM operation, (b) DCM operation and (c) BCM operation . . . . . . . . . . . . . . . . . . . . . .

2.6

22

(a) The boost converter and the equivalent circuits during (b) the onstage and (c) the off-stage. . . . . . . . . . . . . . . . . . . . . . . .

2.5

22

Phasor diagrams showing the relationships between (a) different types of power (b) different types of impedance . . . . . . . . . . . . . . .

2.4

19

29

Simulated waveform of inductor current illustrating the occurrence of DCM operation over a rectified line cycle. . . . . . . . . . . . . . . .

30

2.7

Block diagram of a typical PFC pre-regulator. . . . . . . . . . . . . .

31

2.8

Simplifed schematic of the boost PFC pre-regulator under ACM control. 32

2.9

Simulated waveforms of the boost PFC converter using the full switching model: (a) input voltage vi , (b) inductior current iL , (c) output voltage vo , (d) output current io , (e) output of voltage amplifier vva and (f) output of current amplifier via . . . . . . . . . . . . . . . . . . . . . . xiii

33

2.10 Simulated waveforms of the boost PFC converter using the averaged model: (a) input voltage vi , (b) inductior current iL , (c) output voltage vo , (d) output current io , (e) output of voltage amplifier vva and (f) output of current amplifier via . . . . . . . . . . . . . . . . . . . . . .

34

2.11 The inner current loop of the boost PFC pre-regulator using ACM control. 36 2.12 Frequency response of the current loop’s loop gain Gi . . . . . . . . .

39

2.13 The outer voltage loop of the boost PFC pre-regulator using ACM control. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

39

2.14 Frequency response of the voltage loop’s loop gain Gv . . . . . . . . .

41

3.1

Unstable waveforms of a boost PFC pre-regulator: (a) the output voltage (upper trace) and the inductor current (lower trace) (b) the phase plane trajectory of the output voltage (y-axis) against the inductor current (x-axis). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

50

3.2

Perturbation in rectified input current of PFC converter. Tm = 2π/ωm .

52

3.3

Schematic of (a) the two-stage PFC power supply, and (b) the proposed model using a constant-power-sink termination. . . . . . . . . . . . .

3.4

Circuit schematic of the proposed model consisting of a boost PFC stage terminated by a constant power sink. . . . . . . . . . . . . . . .

3.5

53

54

Stability boundaries of the resistor terminated model and the proposed constant-power-sink terminated model. (a) C = 66 µF, τF = 9 ms; (b) GF = 12 A, τF = 9 ms; (c) GF = 12 A, C = 66 µF. . . . . . . . . .

3.6

62

Stability boundaries of the proposed constant-power-sink terminated model plotted in various parameter planes. (a) GF –VPFC plane with τF = 9 ms; (b) C–VPFC plane with GF = 12 A; (c) τF –VPFC plane with C = 66 µF. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . xiv

63

3.7

Simulated waveforms of line frequency oscillation occurred in (a) the two-stage PFC power supply model with forward converter termination; (b) the PFC converter model terminated with constant power sink. 1st row: Rectified input voltage vi [V]; 2nd row: Inductor current iL [A]; 3rd row: PFC converter output voltage VPFC [V]; 4th row: PFC converter output current iPFC [mA]; . . . . . . . . . . . . . . . . . .

3.8

65

Stability boundaries plotted on the PFC stage’s output voltage VPFC against the output power Po . The circuit parameters are: GF = 11.6, C = 69 µ F, τF = 8.6 ms. Each figure corresponds to only one parameter change. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3.9

66

Stability boundaries plotted on the PFC stage’s feedback gain GF against the PFC stage’s output power Po . The circuit parameters are: VPFC = 240 V, C = 69 µ F, τF = 8.6 ms. Each figure corresponds to only one parameter change.

. . . . . . . . . . . . . . . . . . . . . . . . . . .

3.10 Experimental circuit of the complete two-stage PFC power supply.

67

.

68

3.11 Detailed schematic of PFC controller circuit. . . . . . . . . . . . . . .

68

3.12 Symbolic representation of different operating regions of the PFC converter. Region A is stable region. Regions B, C, D are unstable regions, with gradual increase in severity of line-frequency oscillations.

. . .

69

3.13 Measured data for operations in (a)-(b) region A; (c)-(d) region B; (e)(f) region C; and (g)-(h) region D. Upper trace of left panels is output ripple voltage (10 V/div); lower trace of left panel is rectified input current (500 mA/div). Panels on the right are histograms of input current harmonics and waveforms before rectification. In the x-axis, “0” represents the dc component, “1” represents 50 Hz component, etc. . .

71

3.14 Performance degradation due to line-frequency instability. (a) Power factor; (b) output ripple voltage; and (c) peak input current.

. . . . .

73

3.15 Experimental verification and comparison of stability boundaries between the resistor terminated model and the complete two-stage system. (a) GF = 11.6 A, C = 66 µF, τF = 8.6 ms; (b) GF = 9.86 A, C = 66 µF, τF = 8.6 ms; (c) GF = 11.6 A, C = 83 µF, τF = 8.6 ms; (d) GF = 11.6 A, C = 66 µF, τF = 10.6 ms. xv

. . . . . . . . . . . . .

74

3.16 Experimental verification of stability boundaries of the constant-powersink terminated model in various parameter space. (a) GF –vPFC plane with τF = 8.6 ms; (b) C–vPFC plane with GF = 11.6 A; (c) τF –vPFC with C = 66 µF. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

75

3.17 Design aid to verify stability of the PFC converter . . . . . . . . . . .

77

3.18 Synchronization between the boost PFC stage and the downstream converter with (a) 0◦ phase shift; (b) 90◦ phase shift; (c) 135◦ phase shift and (d) 270◦ phase shift. Ts is the switching cycle, dPFC and dDS are the duty cycles of the boost PFC stage and the downstream converter respectively. . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.1

Circuit schematic of a boost PFC stage terminated by a constant current sink. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4.2

79

82

Stability boundaries of the constant-current-sink terminated model plotted in various parameter planes. (a) GF –VPFC plane with τF = 8.6 ms; (b) C–VPFC plane with GF = 12 A; (c), (d) τF –VPFC plane with C = 66 µF. For (a), (b) and (c), Io = 0.2 A. . . . . . . . . . . . . . .

4.3

86

Stability boundaries of the constant-current-sink terminated model and the constant-power-sink terminated model. (a) C = 66 µF, τF = 8.6 ms; (b) GF = 12 A, τF = 8.6 ms; (c) GF = 12 A, C = 66 µF. . .

4.4

87

Simulation results of stability boundaries between the constant-currentsink terminated model and the complete two-stage system. (a) GF – VPFC plane with τF = 8.6 ms; (b) C–VPFC plane with GF = 12 A; (c), (d) τF –VPFC plane with C = 66 µF. For (a), (b) and (c), Io = 0.2 A. .

4.5

88

Simulation results of stability boundaries of the constant-current-sink terminated model and the constant-power-sink terminated model. (a) C = 66 µF, τF = 8.6 ms; (b) GF = 12 A, τF = 8.6 ms; (c) GF = 12 A, C = 66 µF. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4.6

89

Comparison of stability boundaries among converters with different types of load terminations: (a) constant power sink termination; (b) constant current sink termination; (c) pure resistive load. C = 66 µF, τF = 8.6 ms; GF = 12 A. . . . . . . . . . . . . . . . . . . . . . . . . xvi

91

5.1

Boost PFC converter with the control based on the multi-loop control structure. The inner current loop is highlighted to indicate the use of the proposed derivation approach. . . . . . . . . . . . . . . . . . . .

94

5.2

Ideal waveforms of the boost PFC converter.

95

5.3

Separation of time scale and the modeling approach for the current

. . . . . . . . . . . . .

loop and the voltage loop. . . . . . . . . . . . . . . . . . . . . . . . .

96

5.4

Boost PFC converter with the derived inner-loop current control rule. . 101

5.5

(a) Block diagram of the current error dynamics under the derived current control rule; (b) block diagram in general form. . . . . . . . . . . 103

5.6

Computed frequency responses of G0i with various combinations of control parameters: (a) Ki1 is varying with Ki2 fixed at 4 × 109 ; (b) Ki2 is varying with Ki1 fixed at 6 × 104 . . . . . . . . . . . . . . . . . 105

5.7

Simplified schematic of the boost PFC converter with the derived control rules implemented as individual control circuitries. . . . . . . . . 108

5.8

Simplified schematic of the control circuit implementing conventional ACM control using UCC3817. . . . . . . . . . . . . . . . . . . . . . 108

5.9

Experimental and theoretical Bode plots of the current loop gain with Ki1 = 6 × 104 , Ki2 = 4 × 109 . . . . . . . . . . . . . . . . . . . . . . 110

5.10 Experimental waveforms resulting from (a) the conventional ACM control and (b) the proposed general current control at f = 800 Hz. Inductor current: [0.5 A/div]; input voltage [100 V/div]. . . . . . . . . . 111 5.11 Experimental waveforms of inductor current and input voltage under various operating conditions: line frequency of (a) 300 Hz and (b) 800 Hz; input voltage of (c) 80 V and (d) 130 V; output power of (e) 120 W and (f) 50 W. Inductor current: (a)–(d), (f) [0.5 A/div], (c) [1 A/div]. Input voltage: [100 V/div]. . . . . . . . . . . . . . . . . . . . . . . . 112 5.12 Power factor measured under the variations of (a) line frequency, (b) input voltage and (c) output power. . . . . . . . . . . . . . . . . . . . 113 xvii

6.1

Boost PFC converter with the control based on the multi-loop control structure. The voltage control loop is highlighted to indicate the adoption of the proposed derivation approach. . . . . . . . . . . . . . . . . 115

6.2

Boost PFC converter with the derived outer-loop voltage control rule.

6.3

(a) Block diagram of the voltage error dynamics under the derived volt-

118

age control rule; (b) block diagram in general form. . . . . . . . . . . 119 6.4

Computed frequency responses of Gv with various combinations of control parameters: (a) Kv1 is varying with Kv2 fixed at 4.5 × 104 ; (b) Kv2 is varying with Kv1 fixed at 380. . . . . . . . . . . . . . . . . . . 121

6.5

Transient response of the error voltage with various combinations of control parameters: (a) Kv1 is varying with Kv2 fixed at 4.5 × 104 ; (b) Kv2 is varying with Kv1 fixed at 380. . . . . . . . . . . . . . . . . . . 123

6.6

Boost PFC converter with complete control scheme.

. . . . . . . . . 124

6.7

Simplified schematics of the boost PFC converter with the derived control rules implemented as individual control circuitries. . . . . . . . . 126

6.8

Experimental and theoretical Bode plots of the voltage loop gain with control parameters Kv1 = 381 and Kv2 = 4.51 × 104 .

6.9

. . . . . . . . 127

Transient response waveforms under (a) the ACM control and (b) the derived voltage control. Output voltage: (a) [2 V/div], (b) [1 V/div]. Output current for both (a) and (b): [0.2 A/div]. Time scale: [10 ms/div]. 128

6.10 Transient response waveforms with various combinations of Kv1 and Kv2 : (a) Kv1 = 380 and Kv2 = 4.5 × 104 ; (b) Kv1 = 220 and Kv2 = 4.5 × 104 ; (c) Kv1 = 510 and Kv2 = 4.5 × 104 ; (d) Kv1 = 380 and Kv2 = 2.5 × 104 . Output voltage: [1 V/div]. Output current: [0.2 A/div]. Time scale: [10 ms/div]. . . . . . . . . . . . . . . . . . . 129 6.11 Transient response waveforms at various operating conditions: line voltage at (a) 140 Vrms and (b) 80 Vrms; stepping load-current of (c) 0.4 A to 0.14 A and (d) 0.2 A to 0.14 A. Output voltage: [1 V/div]. Output current: [0.2 A/div]. Time scale: [10 ms/div]. . . . . . . . . . 130 xviii

7.1

A boost PFC converter with the inner loop current control. . . . . . . 136

7.2

A boost PFC converter with the current loop employing the derived control rule. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137

7.3

Calculated waveforms of (a) u¯eq and (b) iL and iref during the saturation period. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140

7.4

Calculated transient waveforms of (a) x˙ 1 and (b) u¯eq just after the saturation of duty cycle. . . . . . . . . . . . . . . . . . . . . . . . . . . 142

7.5

Illustrations of the control signal vic and the PWM output vgs in (a) TEM scheme and (b) LEM scheme. . . . . . . . . . . . . . . . . . . 144

7.6

Feedforward implementation of the derived current control using (a) TEM controllers and (b) LEM controllers. . . . . . . . . . . . . . . . 147

7.7

Simplifed schematic for the feedforward implementation of the derived control using the TEM PFC controller UC3854. . . . . . . . . . . . . 149

7.8

Simplifed schematic for the feedforward implementation of the derived control using the LEM PFC controller UCC3817. . . . . . . . . . . . 150

7.9

Simulated waveforms of (a) inductor current and (b) output voltage of the converter model with feedforward implementation using the TEM controller. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151

7.10 Simulated waveforms of (a) inductor current and (b) output voltage of the converter model with feedforward implementation using the LEM controller. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151 7.11 Comparison of the simulated inductor current waveforms between converter models with ACM control (left column) and the feedfoward implementation of the derived control rule (right column) under various operating conditions: (a)(b) line frequency of 800 Hz; (c)(d) input voltage of 130 V; (e)(f) output power of 50 W. Both the models adopt the TEM controller UC3854. . . . . . . . . . . . . . . . . . . . . . . . . 153 xix

7.12 Comparison of simulated inductor current waveforms between converter models with ACM control (left column) and the feedfoward implementation of the derived control rule (right column) under various operating conditions: (a)(b) line frequency of 800 Hz; (c)(d) input voltage of 130 V; (e)(f) output power of 50 W. Both the models adopt the LEM controller UCC3817. . . . . . . . . . . . . . . . . . . . . . . . 154 7.13 Simulated inductor current of the converter model with feedforward implementation of the derived control using the TEM controller UC3854 under various operating conditions: line frequency of (a) 300 Hz and (b) 800 Hz; input voltage of (c) 80 V and (d) 130 V; output power of (e) 120 W and (f) 50 W.

. . . . . . . . . . . . . . . . . . . . . . . . 157

7.14 Simulated inductor current of the converter model with feedforward implementation of the derived control using the LEM controller UCC3817 under various operating conditions: line frequency of (a) 300 Hz and (b) 800 Hz; input voltage of (c) 80 V and (d) 130 V; output power of (e) 120 W and (f) 50 W. 8.1

. . . . . . . . . . . . . . . . . . . . . . . . 158

An overview of the completed research work. . . . . . . . . . . . . . 160

xx

List of Tables 1.1

Typical commercial PFC controller ICs . . . . . . . . . . . . . . . .

10

2.1

IEC61000-3-2 Harmonic current limits for Class A equipment . . . .

25

2.2

IEEE-519 odd current harmonics limits for system rated at 120 V to 69 kV

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.3

DO-160 Harmonic current limits for airborne equipments

. . . . . .

2.4

Comparison between DO-160 standard and IEC61000-3-2 Class A

25 26

standard . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

26

2.5

Parameters used in the PFC converter model . . . . . . . . . . . . . .

43

3.1

Circuit parameters used in experiments . . . . . . . . . . . . . . . . .

69

3.2

Summary of performance tradeoffs for stability improvement

. . . .

78

4.1

Circuit parameters used in simulation . . . . . . . . . . . . . . . . .

85

5.1

Circuit parameters used in the experiments . . . . . . . . . . . . . . . 109

6.1

Circuit parameters used in the experiments . . . . . . . . . . . . . . . 131

7.1

Nominal conditions and circuit parameters in the simulation . . . . . 148

xxi

Nomenclature List Unless otherwise specified, some commonly-used symbols in the thesis are defined as follows.

Symbol

Description

vi , Vi

Rectified line voltage, peak of the rectified line voltage

Vi,rms

Rms value of the rectified line voltage

fs

Switching frequency

Ts

Switching period

f, fm

Nominal line frequency in Hz

ω, ωm

Nominal line frequency in rads−1

T, Tm

Nominal line period

vPFC , vo VPFC,ref , Vref d, d¯

Output voltage of PFC converter Reference output voltage Duty cycle, inverse of duty cycle

L

Inductance

iin

Rectified input current

iL , IL iref , Iref

Inductance current, peak of the inductance current Reference current, peak of the reference current

iD

Diode current

ic

Capacitor current

iPFC , io

Load current

R

Resistive load

Pi , Po

Input power, output power

C

Output capacitance

Rs

Sensing resistor

vramp , Vm

Ramping signal, amplitude of the ramping signal

xxii

Chapter 1 Introduction 1.1 Motivation Nowadays, power factor correction (PFC) is playing an increasingly important role in ensuring high power quality in the delivery of electrical power from the generating ends to the end users. Traditional capacitor rectifiers generate large input current distortion and phase shift between the voltage and current, leading to undesirable reactive power which limits the real power delivered from the mains to the load. PFC solves this problem by boosting up the power factor and eventually improves the power quality and energy efficiency delivered from the AC mains. In addition, agency standards, such as the IEC 61000-3-2 [1] and the IEEE-519, impose mandatory requirements to limit the line current’s harmonic contents of mains-connected appliances. Therefore, in order to comply with the regulations as well as to meet the increasing demand for better power quality and energy utilization, PFC has become a mandatory function for medium to high power off-line power supplies. In general, the design of control in power converters focuses on addressing the basic requirement of stability and the performance specifications. Although the technology of power converters appears to be fairly mature, there remains some unsolved problems in PFC converters in terms of these two criteria. For the concern of stability, conventional approaches of stability analysis for PFC converters heavily rely on the techniques used in dc-dc converters, in which Jacobian linearization is applied and the ac input voltage is approximated by a fixed dc value. In consequence, instability 1

1. Introduction

2

phenomena associated with the ac line voltage and the converter’s nonlinear dynamics cannot be analyzed properly. In some analyses, even though large signal and ac input voltage are considered, resistive load termination is usually assumed, leading to results that are inconsistent with the actual practical PFC power supply, which is terminated by a downstream converter equivalent to a constant power sink. Another problem lies in the performance of the PFC converter. Although the performance of average current mode (ACM) control is considered adequate to meet most standard regulations for terrestrial 50–60 Hz applications, the performance needs to be further improved in order to achieve a high performance PFC converter. For example, if more stringent regulations, such as those for aerospace applications [2], are required to be met. Conventional ACM control exhibits zero-crossing distortion in the input current under high operating line frequency. It also results in rather poor transient response in output voltage during load change. In the literature, numerous methods have been proposed to improve the control performance. However, most of them aim at tackling a particular undesirable phenomenon in either the current loop or the voltage loop. A systematic derivation approach applicable to both loops is still missing. Specifically, in feedforward control schemes, the resulting closed-loop systems become too complex for analysis and formal study of their large-signal behaviors. This necessitates the use of trial-and-error procedures in the design of the control parameters, with the design constraints and the optimal solution remained unknown. In order to get a clear perspective of the stability constraints in practical PFC power supplies, it is essential to examine the stability of PFC power supplies with constant power sink terminations. Further, with the aim at improving the performance of the existing ACM control, a unified approach to generate robust control rules for both the current loop and voltage loop will be of practical importance. All these are the motivations of the present research work.

1.2 Literature Review This section presents a literature review of the development of PFC technologies. The purpose of this review is to provide a historical background as well as some complementary information relevant to the research work. The review will be divided into several subsections which cover various aspects of PFC technologies as shown in

1.2 Literature Review

3

PFC topologies

Buck

Cuk

Boost

Control

Modeling & stability analysis Single-loop

Continuous time model

Discrete time model

DPC

Large signal

Small signal Double averaging

SEPIC

Zeta

Buckboost

Sliding mode Cycle-by-cycle integration

Multi-loop multiplier

OCC Hysteretic ACM

Improved ACM

PCM

NLC OCC

Borderline

Figure 1.1: A review of the boost PFC converter in terms of modeling approach, stability analysis and control methodology. Fig. 1.1. This survey may offer some insights into the future development of the PFC technologies and inspire its potential applications in other areas.

1.2.1 Topologies for PFC converters The usual form of active PFC implementation is the use of switching mode power converters with PFC control. Technically, any power converter can be employed to perform PFC. The three basic topologies: the boost converter, the buck converter and the buck-boost converter are some common choices for non-isolated PFC implementations [3], [4], [5], [6], [7]. Considering continuous conduction mode (CCM) operation

1. Introduction

4

for medium to high power applications, the boost converter is the most popular topology for PFC applications [8]. There are several reasons for this: 1. Comparing to buck converters and buck-boost converters delivering the same amount of power, boost converters impose less current stress on the power components. A smaller peak current means less switching loss and hence higher efficiency. 2. The boost converter employs a ground-reference switch which is more convenient to drive than the floating switch in the buck and the buck-boost topologies. 3. Due to the continuous nature of the input current, the boost converter allows the tightest control over the line-current waveform and injects only a modest amount of high-frequency noise in the line. On the other hand, the buck converter and the buck-boost converter have discontinuous input current, which is less favorable in terms of achieving a unity power factor and results in higher differential-mode EMI current. 4. The limitation in the conversion ratio of the simple buck converter makes it unfavorable for PFC applications. When the input voltage is inevitably lower than the output voltage, line-current distortion occurs. 5. In general, the buck converter and the buck-boost converter require a relatively large inductor in order to reduce the harmonic components included in the line input current, resulting in poor load transient response. However, there are also limitations in the boost topology. Since the boost converter has no controlled switch between the line and the output, housekeeping functions such as inrush-current limiting and short-circuit protection are not available, thus necessitating the use of extra protection circuitries. Another drawback is that the output voltage is always higher than the peak input voltage, which necessitates the use of another converter to step down the output voltage to a usable level. ´ converter, the zeta converter and the SEPIC converter are also potential The Cuk ´ converter were proposed by Le-Huy et candidates. Ac-dc converters based on the Cuk al. [9] and Brković et al. [10]. The isolated SEPIC PFC converter has been introduced by Canesin et al. [11] and Sebastián et al. [12]. These topologies have continuous


5

input current even when operating in discontinuous conduction mode (DCM). However, they are less popular in practical applications due to the higher circuit complexity comparing to the boost converter. Also, they generally have higher voltage and current stresses [13], and require the use of more expensive output capacitors, leading to higher failure rates [14]. Overall, the numerous advantages offered by the boost converter make it the most preferable choice for medium to high power PFC converters. Up to now it is still the most widely-used PFC topology in the power electronics industry. In the rest of this thesis, we will focus on the boost PFC converter and its related topics.

1.2.2 Control Methods The objectives of the control circuit for PFC pre-regulator are two-fold. First, a near unity power factor should be maintained at the inside side. Second, a consistent average voltage should be maintained across the output storage capacitor. Literature is abounded with novel PFC control methods that address these objectives. For ease of elaboration, these control methods are divided into a few categories in terms of their structures and implementation approach. They are the multi-loop multiplier approach, the cycle-by-cycle integration approach, the single-loop control approach and the sliding mode control approach. Under these categories, some common PFC control methods are reviewed. We try to cover some development history of typical control methods, which is followed by discussions of advantages and disadvantages of these methods. Typical controller ICs are given as examples. In additional to the various control methods, some innovative strategies to improve the existing average current mode (ACM) control are also discussed.

1.2.2.1 Multiloop multiplier approach Multi-loop multiplier approach refers to the use of a multiplier together with cascading control loops: an outer voltage loop and an inner current loop. The outer voltage loop is responsible for output voltage regulation. It produces a voltage error signal which is fed into the multiplier to determine the amplitude of a sinusoidal envelope corresponding to the reference current. Moreover, the current loop is responsible to program the input current to follow this envelope. Some commonly-used control methods, such as

1. Introduction

6

the average current mode (ACM) control, the peak current mode (PCM) control, the hysteretic control and the borderline control, fall into this category. This category of control methods have similar outer voltage loops and multiplier circuitries. However, they vary in the ways the inductor current is programmed, which will be discussed in more detail as follows. PCM control is one of the earliest control methods used in PFC converters. It programs the peak of the inductor current to follow the predefined reference current profile. It is characterized by direct comparison of the sensed current with the reference using a comparator, which generates pulses to a flip-flop to produce the pulse-widthmodulated (PWM) gate drive signal. Although there are only a limited number of publications that provide a historical view of the early implementation, the application of PCM in PFC converters is obviously linked to its diffused use in current-programmed dc-dc converters [15]. The first commercial PFC controller IC implementing PCM control appeared early in 1989 [16], [17], which is the ML4812 by Fairchild semiconductor (formerly Micro Linear). A detailed analysis and design trade-offs were presented by Zhou et al. [18]. PCM offers the advantages of simple implementation and effective control. However, since a duty cycle larger that 50 % is inevitable in PFC operation, compensation ramp is required for a stable operation. Moreover, PCM control exhibits poor noise immunity and a relatively high input current distortion. These make it less attractive to PFC applications comparing to the ACM control. ACM control [19] is the most widely-used control method for PFC converters. It is characterized by the use of a current amplifier to program the averaged inductor current (averaged over a few switching cycles) to follow a predefined reference profile. The earliest implementation of this concept was reported in 1982 by Kocher and Steigerwald [20]. Then the major research work of ACM control was conducted by VPEC (Virginia Power Electronics Center of Virginia State University ) under the sponsorship of Lambda Electronics in the early 1990’s. In 1990, the first ACM PFC controller IC was developed by Texas Instrument (formerly Unitrode Corporation) with the introduction of the UC1854 family [21]. Within years, with the abundant availability of ACM controllers from various manufactures (Table 1.1), ACM control has become widely adopted in PFC converters [22], [23]. Comparing to PCM control, ACM control offers several advantages. First, it does not require the use of slopecompensation. Second, it provides more accurate current tracking and hence lower


7

current distortion. Third, it offers better noise immunity with the use of a sawtooth waveform in the PWM modulator. Hysteretic control is an alternative to the fixed-frequency PWM control. It employs two current reference profiles, namely, the upper reference and the lower reference, to shape the peak and the valley of the inductor current. The main switch is turned off when the inductor current reaches the upper current reference and turned on when the current falls and reaches the lower reference current. The earliest application of hysteretic control in PFC converters dated back to 1986 [24], [25], [26], [27]. A detailed analysis and design guideline were presented by Zhou et al. [28] in 1990. The advantages of the hysteretic control are the elimination of compensation ramp and low input current distortion. But it suffers from the disadvantages of variable switching frequency and the control-sensitivity to commutation noise, which complicate the design procedure and induce excessive switching losses. Borderline control is a control methodology in which the converter is operating at the boundary conduction mode (BCM) or sometimes called “the transition mode” between CCM and DCM. In the early version, the main switch is turned off after the switch current has reached the reference current. It is turned on when the inductor current drops to zero. Therefore, this method is sometimes considered as a particular case of hysteretic control with the lower reference being zero [3]. Later, some modified versions have emerged [29], [30], [31], in which the main switch is turned off after a fixed duration of on-time depending on the output of the voltage error amplifier. In these cases the multiplier and the switch current sensing can be eliminated. The converter model and its analysis under this control method were presented by Choi [32]. This method reduces the switching loss by zero current switching of the power diode and the main switch. However, it suffers from the same disadvantage as hysteretic control that the switching frequency is variable. The resulting high current stress also limits its application to low power devices.

1.2.2.2 Cycle-by-cycle integration approach There are multi-loop control methods that do not require the use of multiplier. They also consist of similar voltage loops for output voltage regulation. However, the multiplier is eliminated as no explicit reference current profile is generated. Instead, input

1. Introduction

8

current shaping is accomplished by comparing the sensed current with the cycle-bycycle integration of a mixture of instantaneous signals [33]. Based on this concept, a new PWM control method was developed by Smedley et al. [34], [35] in 1991, which is known as the one-cycle control (OCC). After a few years, Smedly and Lai et al. successfully applied OCC to different PFC converter topologies [36], [37], [38]. In this control method, the clock signal triggers the flip-flop to begin a switching cycle. During the on time, the output of the voltage error amplifier is integrated and then compared with the real-time signal associated with the inductor current. When the two inputs of the comparator equal, the flip-flop is reset to end the on-time interval. Meanwhile, all the integration processes are stopped by resetting the integrators’ output to zero. The integrators’ output are maintained at zero until the next switching cycle begins. The OCC offers the advantage of the elimination of the multiplier and input voltage sensing, which simplifies the control implementation and reduces the cost. However, it suffers from the disadvantage that the control is sensitive to switching noise. It also exhibits higher input current distortion comparing to ACM control under light load and high line conditions. In the meantime, another similar control method called nonlinear carrier control (NLC) is proposed by Maksimonvic et al. [39]. In this work, the error voltage is integrated twice to generate the reference signal for current tracking, which is referred to as the nonlinear carrier signal. For the current shaping, instead of directly using the sensed switch current for comparison, the sensed current is integrated to obtain an averaged value before being compared with the nonlinear carrier signal. This enhances the noise immunity and reduces the input current distortion. However, its physical realization is more complex than the OCC due to the use of more integrators. A generalized derivation of PFC control laws based upon cycle-by-cycle integration technique was described by Rajagopalan et al. [40]. They introduced a general procedure that systematically leads to a number of control law candidates, which cover the afore-mentioned approaches. Recently, Chen et al. [41] have proposed a nonlinear current control (NCC) that combines the idea of OCC with the feedforward compensation. In their work, feedforward signals of input voltage and output voltage are added to the sensed current signal as well as the voltage error signal before undergoing the cycle-by-cycle integration and the subsequent comparison. The feedforward scheme results in lower input current dis-


9

tortion comparing to the OCC. However, it requires the use of mixed-signal circuitries such as multipliers and digital controllers, which increases the implementation cost and complexity.

1.2.2.3

Single loop approach

Unlike the multi-loop approach, some control methods only consist of a single voltage control loop to regulate the output voltage. The input current shaping is accomplished in an open-loop manner, in which the duty cycle patterns are predefined by considering ideal PFC operation. One example is the duty phase control (DPC) proposed by Chen [42], [43]. In this method, a phase shift is deliberately introduced to the stored duty cycle patterns. The output voltage is regulated by adjusting this phase shift using the output of the voltage error amplifier, which is termed “the duty phase”. This approach eliminates the current loop and simplifies the control structure. It also succeeds in producing a sinusoidal input current without the need to sense the input current. However, the control suffers from the disadvantage of complex circuit implementation, which requires the use of PLL as well as digital circuitries to store and retrieve the duty cycle patterns and the lookup tables. The stored duty cycle pattern also limits its performance in non-ideal situation where the input voltage is not perfectly sinusoidal. Moreover, the input current distortion is subject to the effects of parasitic parameters. Another example of single loop approach is the input current sensorless control method proposed by Sivakumar et al. [44]. The method eliminates the instantaneous input current sensing in the expense of additional sensing of the slowly-varying load current. However, the constraint that the duty cycle must be smaller than unity restricts the achievable current shaping performance.

1.2.2.4 Sliding mode control approach Sliding mode (SM) control is a class of nonlinear control methods for controlling variable structure systems (VSS) [45], [46], [47], [48]. Its applications in power converter dated back to the early 1980s’ [49], [50]. This spurred a large amount of research interests towards the applications of SM control not only in dc-dc converters [51], [52], but also in PFC converters [53], [54], [55]. Under the multi-loop cascaded control structure, a SM scheme for the outer voltage loop control was introduced by Jezernik

1. Introduction

10 Table 1.1: Typical commercial PFC controller ICs control method

controller ICs

PCM

ML4812 (Fairchild) TK84812 (Toko)

ACM

UC1854/A/B family (Texas Instruments) L4981A/B (STMicroelectronics) TK3854A (Toko) ML4821 (Fairchild) TDA4815, TDA4819 (Siemens) LT1248, LT1249 (Linear Technology) TA8310 (Toshiba)

Hysteretic control

CS3810 (ON Semiconductor)

Borderline control

TDA4814, TDA4816-8 (Siemens) ML4812 (Fairchild) L6560 (STMicroelectronics) UC1852 (Texas Instruments) MC33261-2 (Motorola)

One-cycle control

IR1150 (International Rectifier)

et al. in 1993 [56]. Later in 1999, he presented a discretized SM approach for the inner current loop control [57]. A SM control employing the cycle-by-cycle integration was proposed by López et al. [58] in 2001. Like OCC, it eliminates the multiplier comparing to the methods of Jezernik et al. [56], [57]. Integrated SM schemes for controlling both the output voltage and input current were introduced by Silva [59], [60] in 1997, in which the α − β space-vectors are used to control a three-phase boost PFC converter based on power balance. SM control offers the advantages of excellent transient response and robust performance. However, the variable switching frequency limits its practical application as it induces excessive switching losses and complicates the magnetic design. Although some SM control schemes with limited switching frequency [61], [62], [63] have emerged to address this problem, the issues of noise-sensitivity of the control and complex implementation still remain a barrier for its mainstream adoption in PFC converters. In the power electronics industry, commercial PFC controllers implementing different control methods are available from various manufacturers. Some typical examples are listed in Table 1.1.


11

Despite the emergence of new PFC control methods, ACM control has been and is still the mainstream control method widely adopted by medium to high power PFC converters due to the numerous advantages it offers. For this reason, we will continue to focus on ACM control and explore the possibility of its further improvement in our research work.

1.2.3 Improvements in ACM Control After the discussion of various control methodologies, we now return our focus to the ACM control. Despite its popular use in PFC applications, the ACM control has several performance issues that need to be further improved. One is the poor transient response performance in the event of load change. Another is the zero crossing distortion under high operating frequency. Besides searching for new alternative control methods, much research effort has been put in improving the existing ACM control. Based on the original ACM framework, various improvement schemes have emerged with better performance in current tracking and transient response. With a bandwidth much higher than the line frequency, the existing current loop control appears to be more than adequate for current tracking for most of the terrestial 50–60 Hz applications. However, under high line frequency condition, such as those in aerospace applications, zero-crossing distortion is reported by Sun [64]. High line and light load conditions make the situation even worse. This issue spurred a series of research interest towards the elimination of such a distortion. In the same work, Sun proposed a solution by adding a phase delay in the reference current to compensate the leading phase of the current. Alternatively, Wall et al. [65] feedforwarded the input voltage and output voltage signal to the current error to reduce the input current distortion. Later, Chen et al. [66] presented a more complete feedforward scheme by including the derivative of the reference current in the feedforward signal. Recently, Louganski et al. [67] presented a method of adding an extra RC network in the current amplifier compensation network to compensate the phase lead in the current signal. In the outer voltage loop, due to the limited bandwidth, the output voltage has sluggish transient response with a relatively large overshoot. Over the past decade, numerous attempts have been made to improve the transient response performance. One approach aims at removing the rectified line frequency ripple in the feedback signal,

1. Introduction

12

which allows a further increase in the voltage loop’s bandwidth without deteriorating the input current distortion. The use of an analog notch filter to filter the line frequency ripple was first reported by William [68]. With the advent of DSP technology, the digital implementation of the notch filter and its variants enables sophisticated filtering functions to be realized conveniently [69], [70], [71], [72]. Besides the filtering method, the line frequency ripple can also be compensated by inserting a nonlinear function in the voltage loop, which is also known as active ripple cancellation [73], [74], [75]. Other approaches focus on maintaining the output voltage within a predefined regulation band. When the output voltage goes beyond the regulation band in the event of a step load, certain actions will be taken to bring the output voltage back to the regulation band [68], [76], [77]. Besides, the voltage feedforward control also provides an effective method to improve the transient response performance. For example, Figueres et al. [78] feedforwarded the load-current signal to the output of the voltage error amplifier. There are also improvement schemes that aim at reducing energy consumption and boosting efficiency under light load condition. One example is the green-mode function reported by Hwang and Chee [79], [80]. In their work, when the output power of a two-stage PFC power supply goes below a certain threshold, the proposed greenmode function turns off the PFC converter intermittently and operates the cascading dcdc converter in pulse-skipping mode in order to reduce the energy loss in the converter.

1.2.4 Modeling and Stability analysis As fast and slow scale instabilities have been reported in power converters [81], there is no exception for boost PFC converters [82], [83], [84], [85]. In order to ensure stable operation, it is of practical significance to model the converter properly and analyze its stability conditions. In the literature, there are several common approaches to study the stability of the boost PFC converter.

1.2.4.1 The quasi-static approach The quasi-static approach is commonly applied in the analysis of PFC converters. The concept was introduced in the early 1980s’ in the works of Schlecht, Kocher et al. and Hudson et al. [86], [87], [20], [88]. The main idea is that under the assumption that


13

the line frequency is usually much lower than the switching frequency, the ac input voltage can be approximated by a constant voltage in a few consecutive switching periods. Such approximation is justified by the fact that under the changing input voltage, the converter will try to reach its steady state under a stable control law. Even though it may never reach the switching frequency steady state, it is operating in the neighborhood of the steady state, which is known as “the quasi-steady state”. This approach simplifies the modeling and analysis of PFC converters. More importantly, the quasi-fixed operating point allows the application of powerful modeling tools such as small-signal analysis and frequency response analysis.

1.2.4.2

The continuous averaged model

Based upon the concept of quasi-steady state, Henze and Mohan [24] presented a control-output model of a PFC converter that consists of a controlled current source feeding the load capacitor and resistor. However, a few years later, the model was proved to be incomplete by Ridley [89]. In his work, Ridley derived small-signal transfer functions of the voltage loop by power balance, with the consideration of cases with resistive load and constant power load. Later, a more complete small-signal model was presented by Huliehel et al. [90], which considered also the interactions between the line frequency ripple and other state variables. However, the validity of the sampling function in the current loop transfer function is doubted by some researchers [91], [92]. Based on these small-signal linear models, techniques used in dc-dc converters are applied to PFC converters to analyze the behaviors and predict the onset of slow-scale instabilities. Tools such as Bode plots, Routh-Hurwitz criterion, Nyquist criterion and the associated impedance analysis [93] have been utilized to obtain the stability criteria. This small-signal approach simplifies the modeling and analysis of PFC converters. Also, analytical stability criteria can be obtained. However, as regards to practical operation, the results only correspond to the behaviors of the PFC converter at a particular point of input voltage along the ac line cycle. Moreover, the averaging process limits the results’ validity up to half the switching frequency, depending on the sampling period. Therefore, it is insufficient to detect the fast-scale instability such as the period doubling phenomenon. The assumption of a constant input voltage also indicates that this approach cannot be used to detect instability phenomena associated with the AC input voltage.

1. Introduction

14

There are only limited number of publications about large-signal modeling of boost PFC converters. In 1998, Sun et al. [94] presented a large-signal model for the inner current loop control. In his work, although the input voltage was still assumed to be constant, the effects of the output ripple component on the state variables were considered by using the KBM (Krylov-Bogoliubov-Mitropolsky) method. In 2004, Sun [64] presented another large-signal current loop model with varying input voltage. In that model, instead of the rectified input voltage, the non-rectified sinusoidal input voltage was used as an input variable, leading to a linear large-signal model. In the same year, Lu et al. [95] also presented a large signal equivalent circuit based on general averaging, which is applicable to both boost dc-dc converters and PFC converters. However, the proposed model only covered the boost power stage and the closed-loop behavior was not described. In order to have a clear perspective of the line frequency instability phenomenon reported by Orabi et al. [82], a double-averaging approach was introduced by Wong et al. [96]. The approach is based on the concept of harmonic balance. In this approach, the averaged state variables are decomposed into sinusoids of the line frequency and its harmonics by Fourier series. The variables are further averaged by eliminating the higher order components. This method has succeeded in predicting the low-frequency oscillation and has resulted in analytical stability. But the mathematical manipulation is non-trivial and the intensive averaging processes may incur large averaging errors. In the subsequent chapters, this method will be further exploited to analyze the stability of PFC power supplies.

1.2.4.3 The discrete time model Alternative to the continuous averaged model, discrete-time models are frequently used to study the stability of power converters by cycle-by-cycle iteration of the state variables [97], [98], [99], [100]. The system stability can be reflected by locating the eigenvalues of the Jacobian matrix at a fixed operation point. A discrete-time analysis was presented by Dranga et al. [84] to study the stability of a PCM-controlled PFC converter. Based on his work, Iu et al. [85] investigated the period-doubling bifurcation in ACM-controlled PFC converter. In their work, the sinusoidal reference current is regarded as a dc reference with time-varying compensation ramp, which allows the direct application of techniques used in [84]. It is possible to detect both

1.3 Objective

15

fast-scale period-doubling and slow scale bifurcation using the discrete time method [101]. However, this method is inefficient in detecting oscillations of relatively low frequency due to the intensive computational process involved. Moreover, since most of the calculation process rely on numerical methods, it does not lead to analytical results or practical design procedures.

1.3

Objective

In our research work, we focus on the boost PFC converter under the ACM control because such combination is widely adopted in practical PFC implementations. There are several objectives to be achieved. First, we aim at providing an overview on the stability study and the control development associated with the boost PFC converter. Second, through investigating the line frequency oscillation in PFC power supplies, we attempt to clarify the inconsistency between theoretical and practical results, as well as to provide a simple yet effective modeling solution for stability study of practical PFC power supplies. Apart from the stability analysis, we try to derive a unified approach for generating robust control rules that bring performance improvements to the existing ACM control. In order to further explore the generation of robust control rules from diverse perspective, the control law is re-iterated from a sliding mode control theory viewpoint. On the overall, these topics share a common ultimate objective, which is to provide useful guidelines to facilitate the design of high-performance PFC power systems, that would ensure stability and at the same time embrace performance improvement.

1.4 Outline of the Thesis The thesis is organized as follows. Chapter 1: Introduction. Chapter 1 provides a literature review of the development of PFC converters in terms of control methodologies and stability studies. The motivation and objective of the research work are also described. The purpose of this chapter is to provide a historical background as well as recent research discoveries in PFC converter control technology.

1. Introduction

16

Chapter 2: Overview of the Boost Converter with Power Factor Correction. Chapter 2 provides an introduction to the working principles of the basic boost dcdc converter and a typical control method for implementing power factor correction. Conventional modeling and design approaches are described. Chapter 3: Line-Frequency Instability of PFC Power Supplies. The phenomenon of line frequency instability is examined. A simplifying modeling approach of using a constant power sink is introduced. Based on the double averaging approach, the stability of the system is analyzed. The stability criterion and the design trade-offs are discussed. Chapter 4: Line-Frequency Instability with Constant Current Sink Termination. The stability analysis performed in Chapter 3 is extended to PFC boost converters terminated with constant current sink. The stability criterion of the constantcurrent-sink terminated model is derived and compared with that given by the constantpower-sink terminated model. Chapter 5: The Feedback Linearization Approach for the Derivation of Robust Current Loop Control. The concept of feedback linearization is introduced in Chapter 5. Based on this concept, a systematic approach to generate robust current control law is described. The behavior of the closed-loop system is studied and the design of control parameters is discussed. Experimental results are presented to evaluate the performance of the derived control. Chapter 6: The Feedback Linearization Approach for the Derivation of Robust Voltage Loop Control. In this chapter, the approach introduced in Chapter 5 is extended to the voltage loop. A robust voltage loop control is derived using a unified approach. Likewise, the behavior of the closed-loop system is studied and the design of control parameters is discussed. Experiments are conducted to verify the analytical results. Chapter 7: Re-Visit of Robust Current Control From a Sliding Mode Viewpoint. The concept of sliding mode control is introduced in Chapter 7. Based on the sliding mode control theory, an alternative method to generate the current control law is described. The relationship between the sliding-mode derivation approach and other common derivation approaches is discussed.

1.4 Outline of the Thesis

17

Chapter 8: Conclusion. Chapter 8 concludes the thesis. A summary of the completed tasks will be given. Further development and potential research areas are also discussed.

Chapter 2 Overview of the Boost PFC Converter 2.1 Introduction In this chapter, a review of the fundamentals of boost PFC converters is given. We will begin with a brief introduction of power factor and some common regulations and standards on current harmonics. Then we will proceed to the basic operation of boost PFC converters under ACM control. After that, small-signal models of the PFC converter will be derived, which will be followed by a discussion on the general design procedures. Finally, a conclusion will be given in the end of the chapter.

2.2 The Power Factor If we connect a load to the AC power line, the input current drawn from the power line can deviate from a sine wave even with perfect sinusoidal supply voltage, because the input current waveform depends on the characteristics of the load’s impedance. Nevertheless, using Fourier series, any arbitrary current waveform can be decomposed into sine waves consisting of a fundamental frequency component and its higher order harmonics. For example, with 50 Hz supply voltage, the input current can be decomposed into sine waves with the fundamental frequency component at 50 Hz, the second harmonics at 100 Hz and so on, as illustrated in Fig. 2.1. The phase shift between the supply voltage and the fundamental frequency component of the input current is denoted by φ, as shown in Fig. 2.2(a). The cosine of φ is 18

2.2 The Power Factor

19

defined as “the displacement factor ” denoted by PFp , i.e., PFp = cos φ.

(2.1)

It follows that 0 < PFp < 1. The higher the PFp , the smaller the phase shift between the input current and the input voltage. On the other hand, the amount of the higher order harmonics relative to the fundamental frequency component is indicated by the “total harmonic distortion THD”, which is defined as sµ ¶ µ ¶2 µ ¶2 2 i3 in i2 + + ... + THD = i1 i1 i1

(2.2)

where in denotes the nth harmonic component of the input current. Based on the calculated THD, the distortion factor PFt measures the deviation of the current waveform from a pure sinusoid as shown in Fig. 2.2(b). It is represented by

1 PFt = p . 1 + THD2

(2.3)

1

2

Original waveform

0.01

0.02

-2 0

0 -1 0

+

=0

0

-2 0

2

Fundamental component 50 Hz

2nd harmonics 100 Hz

1

0.02

0.02

0.01

0.02

+ 3rd harmonics 150 Hz

0 -1 0

0.01

0.01

+

Higher order harmonics

Figure 2.1: The decomposition of the input current waveform into 50 Hz fundamental component and its higher order harmonics. The y-axis is input current in [A] and the x-axis is time in [s]

2. Overview of the Boost PFC Converter

20

It follows that 0 < PFt < 1. The higher the PFt , the better the input current resembles a pure sine wave. The overall power factor (PF) can be derived by considering the power transfer from the utility line to the loading device. In general, the line current can be represented by Fourier series as i(t) = Io +

∞ X √ 2Ik sin (kωt + φk ) ,

(2.4)

k=1

where Io is the dc value of i(t). The coefficients Ik and the angle φk (for k = 1, 2, ...) are the rms values and the phase shift of the k th current harmonics respectively. Angular frequency ω is the fundamental frequency of the line voltage. By Parseval’s theorem, the mean-square expression of i(t) is given by v u ∞ X u 2 t Ik2 . Irms = Io +

(2.5)

k=1

The line voltage is a pure sinusoid given by √ v(t) = 2V1 sin ωt,

(2.6)

where V1 is the rms value of the amplitude of the fundamental component. Clearly, Vrms = V1 .

(2.7)

The real power is the average power consumed by the device over an arbitrary interval of time T . In terms of the above variables, the real power is given by Z 1 T v(t)i(t)dt, P = T 0 Z ∞ X 1 T√ 2V1 I0 sin ωt + 2V1 sin ωt = Ik sin (kωt + φk ) dt, T 0 k=1 = V1 I1 cos φ1 = V1 I1 cos φ.

(2.8) (2.9) (2.10)

The apparent power is the product of the rms values of v(t) and i(t) given by S = Vrms Irms , v u ∞ X u 2 t Ik2 = V1 Io + k=1

(2.11) (2.12)

2.2 The Power Factor

21

Power factor (PF) is defined as the ratio of real power to apparent power. Using (2.10) and (2.12), PF is given by PF =

P , S

I1 cos φ . = p P 2 Io2 + ∞ I k k=1

(2.13) (2.14)

If i(t) contains no dc component, Io = 0. Then PF becomes I1 cos φ PF = pP∞ 2 k=1 Ik cos φ = r ³ ´2 P Ik 1+ ∞ k=2 I1 = PFp · PFt .

(2.15) (2.16) (2.17)

It is straightforward to see that PF also varies between 0 and 1. The higher the PF, the smaller the phase shift between the input voltage and the input current, and the lower the input current distortion. Therefore, in order to maintain a high power quality and energy efficiency delivered from the power line, a high PF is desirable and it is the objective of power factor correction (PFC). The ultimate goal of PFC is to achieve unity power factor with PF = 1, so that the input current is a perfect sine wave and exactly in phase with the sinusoidal input voltage. In the context of electrical engineering, both the input voltage and the input current are assumed to be pure sinusoids. Therefore, the power factor is simply attributed to PFp , i.e., PF = PFp = cos φ

(2.18)

In practice, when the input current is lagging the supply voltage, the power factor is described as “lagging power factor”. The reverse is true for the “leading power factor”. Considering the power dissipation for a combination of resistive load and reactive load with rms supply voltage Vrms and rms input current Irms , as mentioned above, the apparent power delivered from the ac supply is simply the product of the two rms values given by S = Vrms Irms .

(2.19)


22

But the real power or the active power is the actual power dissipated in the resistive component, which is given by P = Vrms Irms cos φ.

(2.20)

Therefore, it follows that PF = cos φ =

P S

(2.21)

which is shown in Fig. 2.3(a). Besides, PF also represents the ratio of resistance to reactance for loads connected in series. Considering a RLC circuit with resistance R, inductance L and capacitance C connected in series, the phasor diagram of the impedances is shown in Fig. 2.3(b) .

current

ideal current

distorted current

time

time

voltage

(a)

(b)

Figure 2.2: The overall power factor consists of (a) the displacement factor and (b) the distortion factor

Reactive power Q [Var]

Apparent power S [VA] Real power P [W] (a)

Reactance XC + XL

Impedance Z[ ]

[ ]

Resistance R[ ] (b)

Figure 2.3: Phasor diagrams showing the relationships between (a) different types of power (b) different types of impedance

2.3 Regulations and Standards

It follows that PF = cos φ =

23

R XC − XL

where XC is the capacitor’s reactance calculated by

1 ωm C

(2.22) and XL is the inductor’s

reactance calculated by ωm L, with ωm being the line frequency in rads−1 . Based on the above discussion, PFC effectively makes the connected circuit behave like a pure resistor with apparent power equal to real power.

2.3 Regulations and Standards Besides power factor, harmonic components in the input current are commonly-adopted indicators of power quality. Regulations and standards on current harmonics limits vary in different countries.

2.3.1 IEC61000-3-2 The IEC61000-3-2 [1] is an European standard adopted worldwide for limiting input current harmonics in medium power off-line equipments. The standard categorizes the equipments into four classes, namely Class A, Class B, Class C and Class D. Each class has different harmonics limits. Specifically, Class A includes motor driven equipments, most domestic appliances and virtually all three phase equipments. Equipments that cannot be fitted into other three classes are also considered Class A. PFC converters are generally categorized as Class A equipments. The harmonics limits for this class are shown in Table 2.1 [102].

2.3.2 IEEE STD 519-1992 Another widely-adopted documentary for power quality is the IEEE STD 519-1992 [103]. Unlike the IEC standards, IEEE STD 519-1992 is not a standard but a set of recommendations or practice guidelines for engineers to control harmonic distortion problems [104]. The harmonics limits vary with the level of loading current. They are based on the ratio of the fundamental component of load current Iload to short circuit current Isc at the point of common coupling (PCC). Stricter limits are recommended for

24


heavy load than light load. Table 2.2 shows the recommendations of IEEE 519-1992 on odd harmonics limits and distortion limits in medium power equipments [102].

2.3.3 RTCA DO-160 Apart from regulations for terrestrial 50–60 Hz applications, there are specific regulations imposing harmonics limits on aerospace applications. One example is the DO-160 [2]. DO-160 is a standard for environmental test of airborne equipment released by the Radio Technical Commission for Aeronautics (RTCA, Inc.), which is recognized as a standard in the aviation industry. The documentary specifies the maximum allowable input current harmonics for equipments on a commercial aircraft, such as power supplies for the in-flight entertainment system. The limits for single-phase devices and three-phase devices are listed in Table 2.3 [105]. A direct comparison between the DO-160 (Version E) standard and the IEC61000-3-2 Class A standard is also shown in Table 2.4. A device with 100 W input power and fundamental harmonic current of 1A is used for comparison. From the tables, it is obvious that DO-160 imposes more stringent limits on current harmonics than the IEC standard. The variation of the harmonics limits with the power level makes it even more restrictive. To comply with such a demanding standard, a relatively low current distortion is required under high operating line frequency (400 Hz), which is difficult to achieve using the existing simple control methods such as the ACM control. Therefore, some extra efforts need to be put into further improving the performance of the PFC control, some of which have already been discussed in the previous chapter and will be further explored in our research work.

2.3 Regulations and Standards

25

Table 2.1: IEC61000-3-2 Harmonic current limits for Class A equipment Order of harmonics n

Harmonic current limits [A]

Odd harmonics 3

2.3

5

1.14

7

0.77

9

0.4

11

0.33

13

0.21

15 − 39

0.15

Even harmonics 2

1.08

4

0.43

6

0.3

8 − 40

0.23

Table 2.2: IEEE-519 odd current harmonics limits for system rated at 120 V to 69 kV Isc /Iload [%] Order of harmonics n

< 20

20 − 50

50 − 100

100 − 1000

> 1000

< 11

4

7

10

12

15

11 − 17

2

3.5

4.5

5.5

7

17 − 23

1.5

2.5

4

5

6

23 − 35

0.6

1

1.5

2

2.5

> 35

0.3

0.5

0.7

1

1.4

THD

5

8

12

15

20


26

Table 2.3: DO-160 Harmonic current limits for airborne equipments Order of harmonics n

Limits for single phase

Limits for three phase

3, 9, ..., 39 (odd triplen)

0.15I1 /h

0.1I1 /h

5, 7, 11, 13

0.3I1 /h

0.05I1

17, 19

0.3I1 /h

0.04I1

23, 25

0.3I1 /h

0.03I1

29, 31, ..., 37 (Other odd non-triplen)

0.3I1 /h

0.3I1 /h

2, 4

0.01I1 /h

0.01I1 /h

6, 8, ..., 40 (Other even harmonics)

0.0025I1 /h

0.0025I1 /h

Odd harmonics

Even harmonics

Table 2.4: Comparison between DO-160 standard and IEC61000-3-2 Class A standard Order of harmonics n

IEC61000-3-2 Class A

DO-160 (version E)

2

1.08

0.005

3

2.3

0.05

4

0.43

0.005

5

1.14

0.06

6

0.3

0.005

7

0.77

0.043

8

0.23

0.005

9

0.4

0.017

10

0.18

0.003

11

0.33

0.027

12

0.15

0.005

13

0.21

0.023

2.4 Fundamentals of the Boost PFC Converter

27

2.4

Fundamentals of the Boost PFC Converter

2.4.1

Basic switching operation

Since the ac input voltage is rectified before feeding into the boost converter, the operation of the boost PFC converter can be regarded as dc-to-dc with varying input voltage. In this subsection, the basic switching operation of the boost converter is reviewed. The boost converter is depicted in Fig. 2.4(a). The time interval 0 < t < dTs is defined as the on-stage, where d is the duty cycle and Ts is the switching period. The equivalent circuit during the on-stage is illustrated in Fig. 2.4(b). During the on-stage, the main switch is turned on and the right hand side of the inductor is shorted to ground. The inductor is charged up by the input voltage. The diode is open due to the reverse-bias. With the inductor being disconnected from the output, the loading current is solely supplied by the output capacitor. The dynamics of the inductor current iL and the capacitor voltage vc during the on-stage can be described by vi diL = ; dt L dvc = −io dt

(2.23) (2.24)

where vi is the input voltage, vo is the output voltage and io is the output current. L

D

vo Io

iL S

vi

R

C

(a) L iL C

(b)

R

vo

iL

io

iC

vi

L

vo

vi

iC

io R

C

(c)

Figure 2.4: (a) The boost converter and the equivalent circuits during (b) the on-stage and (c) the off-stage.


28

¯ s is defined as the off-stage, where d¯ = 1 − The time interval dTs < t < dT d. The equivalent circuit during the off-stage is illustrated in Fig. 2.4(c). During the off-stage, the main switch is turned off and the inductor is disconnected from the ground. The voltage across the inductor reverses and allows the conduction of the diode, which connects the charged up inductor back to the output. Then the inductor starts to discharge its energy to the output to support the load as well as to charge up the output capacitor. The dynamics of the inductor current and the capacitor voltage during the off-stage can be described by 1 diL = (vi − vo ) ; dt L dvc = iL − io . dt

(2.25) (2.26)

The switching cycle repeats itself at the switching frequency.

2.4.2 The operation mode There are three operation modes, namely the continuous conduction mode (CCM), the discontinuous conduction mode (DCM) and the boundary conduction mode (BCM), which are characterized by the inductor current waveforms shown in Fig. 2.5. Referring to Fig. 2.5(a), in CCM operation, the inductor current iL does not drop ¯ s . As a result, a positive inductor current to zero during the off-stage interval of dT is always maintained. The CCM operation offers the advantages of high efficiency and lower current stress on the power devices, which are suitable for medium to high power applications. However, comparing to DCM, it requires a separate control for input-current shaping. On the other hand, the inductor current in DCM operation is shown in Fig. 2.5(b). In DCM, there is an extra stage of zero inductor current because the inductor current has dropped to zero during the off-stage. The current remains zero for an interval of (1 − d − d0 )Ts before the start of the next switching cycle. Variable d0 Ts is the off-stage interval. The interval (1 − d − d0 )Ts is also known as the “dead time” interval. During this interval, the dynamics of the inductor current and the capacitor voltage become diL = 0; dt dvc = −io dt

(2.27) (2.28)


29

Under a high conversion ratio, DCM offers the advantage of automatic PFC in a simple boost converter, which means that the average nput current is inherently in phase with the input voltage without any control for current shaping. This property is very useful in single-stage PFC converters, where the duty cycle control is occupied for output regulation and current shaping is accomplished automatically by the DCM operation alone [106] or with the aid of frequency modulation [107]. However, it suffers from the disadvantages of higher current and voltage stresses, necessitating the use of more expensive components and leading to higher failure rates. The high current and voltage spikes also lead to higher differential-mode EMI comparing to CCM. Boundary conduction mode (BCM) is characterized by the inductor current reaching zero right before the next switching cycle as shown in 2.5(c). It is sometimes considered as a particular case of CCM or a transition between CCM and DCM. It is also known as the critical conduction mode or the transition mode. While the boost converter is performing PFC, the operation mode is not only determined by circuit parameters such as the inductor and the load, but also the timevarying input voltage. For the boost PFC converter, the criteria for CCM and DCM T

s

i

L

dT

s

T

s

i

L

t dT

dT

s

s

d'T

s

(1-d-d')Ts

(a)

t

(b) T

s

i

L

dT

s

t dT

s

(c)

Figure 2.5: Inductor current waveform during (a) CCM operation, (b) DCM operation and (c) BCM operation


30

operation are [108]: For CCM: Ka >

M − | sin ωm t| ; 2M 3

(2.29)

Ka

1 . 2M 2

(2.31)

Due to the advantages it offers, CCM is more preferable for medium-to-high power applications. For this reason, CCM operation will be adopted in our research work. tran2.i(l1) 1.4

1.2

1.0

0.8 i

L 0.6

0.4

0.2

0.0

-0.2 130.0

132.0

DCM

134.0 time

136.0

138.0

140.0

mS

CCM

DCM

Figure 2.6: Simulated waveform of inductor current illustrating the occurrence of DCM operation over a rectified line cycle.


2.4.3

31

PFC operation under ACM control

The usual form of a PFC pre-regulator is a boost converter controlled by ACM control. A block diagram is shown in Fig. 2.7. As mentioned in the previous chapter, the ACM control consists of a slow control loop and a fast control loop. The slow one is known as the outer voltage loop and is responsible for regulating the output voltage. The fast one is known as the inner current loop and is responsible for programming the input current so that it follows the same sinusoidal waveform as the input voltage. A simplified schematic of the ACM-controlled boost PFC pre-regulator is shown in Fig. 2.8. The output voltage loop regulates the output voltage by comparing the sensed output voltage with a dc reference voltage using a voltage error amplifier. The resulting error signal is then fed to the multiplier, where it is multiplied with the rectified sinusoidal input voltage to generate a reference current profile. Additionally, the input voltage is also feedforwarded to the multiplier to enhance the regulation performance over a wide range of line voltage. Then the reference current profile is employed by the current loop for input current shaping. In the current loop, the sensed inductor current is compared with the reference current profile using a current error amplifier. The resulting error signal is then fed into the PWM modulator, where the logical gate drive signal is produced by comparing the current error with a fixed-frequency sawtooth. In this way the inductor current is programmed by the current loop to follow the sinusoidal envelope of the input voltage and a near unity PF is achieved. Also, the current’s amplitude is adjusted by the voltage loop to achieve output voltage regulation. i

v

L

v

i

o

Boost converter

C

R

v

gs

ACM control Figure 2.7: Block diagram of a typical PFC pre-regulator.


32

The ACM controlled-boost PFC converter is simulated using WinSPICE [109], [110] with parameters shown in Table 2.5. Some selected waveforms are shown in Fig. 2.9 for the switching model and Fig. 2.10 for the averaged model.

L

vi

D

The boost converter vo io

vgs

R

C

S iL

comparator

current error amp.

PWM

Lowpass iref

1 / x2 Vff

vca vva

multiplier vi

The ACM control

Vm

Voltage error amp.

Vo, ref

Figure 2.8: Simplifed schematic of the boost PFC pre-regulator under ACM control.


33

160

2

140 1.5

Inductor current iL [A]

Input voltage vi [V]

120 100 80 60 40

1

0.5

0 20 0 130

135

140

145

-0.5 130

150

135

Time [ms]

(a)

Output current io [A]

Output voltage vo [V]

145

150

145

150

0.4

280

270

260

0.3

0.2

0.1

250

135

140

145

0 130

150

135

Time [ms]

140

Time [ms]

(c)

(d) 5

Output of current amplifier via [V]

5

Output of voltage amplifier vva [V]

150

0.5

290

4

3

2

1

0 130

145

(b)

300

240 130

140

Time [ms]

135

140

145

150

4

3

2

1

0 130

135

140

Time [ms]

Time [ms]

(e)

(f)

Figure 2.9: Simulated waveforms of the boost PFC converter using the full switching model: (a) input voltage vi , (b) inductior current iL , (c) output voltage vo , (d) output current io , (e) output of voltage amplifier vva and (f) output of current amplifier via .


34

160

2

140 1.5


Input voltage vi [V]

120 100 80 60 40

1

0.5

0 20 0 130

135

140

145

-0.5 130

150

135

Time [ms]

(a)

Output current io [A]


145

150

145

150

0.4

280

270

260

0.3

0.2

0.1

250

135

140

145

0 130

150

135

Time [ms]

140

Time [ms]

(c)

(d) 5

Output of current amplifier via [V]

5

Output of voltage amplifier vva [V]

150

0.5

290

4

3

2

1

0 130

145

(b)

300

240 130

140

Time [ms]

135

140

145

150

4

3

2

1

0 130

135

140

Time [ms]

Time [ms]

(e)

(f)

Figure 2.10: Simulated waveforms of the boost PFC converter using the averaged model: (a) input voltage vi , (b) inductior current iL , (c) output voltage vo , (d) output current io , (e) output of voltage amplifier vva and (f) output of current amplifier via .

2.5 Problems in Modeling and Analysis

2.5

35

Problems in Modeling and Analysis

Although literature is abounded with analytical and computer-based methods to analyze power converters, no single tool or technique can produce a complete yet efficient analysis of the behaviors of PFC converters. Specifically, the boost PFC converter under ACM control is difficult to be modeled and analyzed due to the following reasons [111]. 1. The multi-loop structure of ACM control complicates the analysis. Since the control signal produced by the outer loop propagates to the inner loop in order to generate the final control to the power stage, the closed-loop dynamics is high order and complex to be analyzed if interactions between the two loops are considered. 2. Different time scales are involved in the two control loops. The inner current loop operates at the switching frequency, while the outer voltage loop operates at the line frequency, which is typically much lower than the switching frequency. Therefore, a single technique or analysis method specified at a single time scale cannot be applied efficiently to both control loops. 3. The sinusoidal input voltage leads to nonlinear dynamics. Since the input voltage is time varying, the system does not have a fixed operating point. This invalidates the crucial assumption of small-signal linearizaton. Although a large signal model can still be formulated, it is nonlinear and too complex for further analysis. These issues motivate the search of a simple and robust approach for modeling and analyzing the PFC converter. Some ideas have already been discussed in the previous chapter and will be further extended in the research work.

2.6 Modeling and Analysis of the Boost PFC Converter In this section, the basic modeling and analysis of the ACM-controlled boost PFC converter are discussed. Prior to the derivation, several assumptions are made:


36

1. All the components are ideal without parasitics. 2. The sensing resistor Rs is very small such that it has negligible effect on the power stage’s dynamics. 3. The converter is operating in CCM over the entire line cycle.

2.6.1 Inner current loop modeling The current loop of the boost PFC converter under ACM control is depicted in Fig. 2.11. Applying general averaging over a switching period, the power stage can be described by ¢ 1¡ diL ¯o ; = vi − dv dt L dvo ¯ L − io . = di dt

(2.32) (2.33)

We further assume that the current loop has a much higher bandwidth than the voltage loop, and a large enough output capacitor is used, such that the output voltage can be approximated by a constant voltage Vo in several consecutive switching cycles. In this

vi

L

iL

D

vo io

d

S Rs Ril

R

iL Cip

Riz

iref

C

Ciz

PWM via

Current amplifier Voltage loop & multiplier Inner current loop Figure 2.11: The inner current loop of the boost PFC pre-regulator using ACM control.

2.6 Modeling and Analysis of the Boost PFC Converter

37

way the dynamics of the power stage can be simplified as ¢ 1¡ diL ¯ o ; = vi − dV dt L dvo = 0. dt

(2.34) (2.35)

By applying quasi-static approach, the time varying vi is approximated by a slowly varying dc input voltage of its rms value vi,rms . Then (2.34) becomes ¢ 1¡ diL ¯ o . = vi,rms − dV dt L

(2.36)

Representing (2.36) in the s-domain gives siL (s) =

¢ 1¡ ¯ vi,rms (s) − d(s)V o . L

(2.37)

In the subsequent text, the notation “(s)” for denoting s-domain variables will be omitted for brevity of presentation. With a fixed operating point assumed under the quasisteady state, perturbation and small-signal linearization can be applied to (2.37) to give ´ 1³ ˜¯ v˜i,rms − dV (2.38) s˜iL = o . L With v˜i,rms = 0, the small-signal control-to-output transfer function of the current loop is

¯ ˜iL ¯ ¯ ¯ ˜ ¯ d v˜

i,rms =0

=−

Vo , sL

(2.39)

which is a first-order transfer function with a single integrating pole. Considering the control section, the output of the current amplifier (using leading edge modulation) can be represented by vca = (Rs iL − Ril imo ) Hca ,

(2.40)

where Rs is the sensing resistor, imo is the current generated by the multiplier and Hca is the transfer function of the current amplifier shown in Fig. 2.11. Transfer function Hca can be represented by

´ ³ Kio 1 + ωsiz ´ , ³ Hca = s s 1 + ωip

(2.41)

1 1 1 ; ωiz = ; ωip = . (Cip + Ciz )Ril Ciz Riz (Cip k Ciz ) Riz

(2.42)

where Kio =


38

The variables Cip , Ciz , Ril and Riz are network components defined in Fig. 2.11. With Vm being the amplitude of the ramping signal in the modulator, the inverse duty cycle generated from the modulator is 1 vca = (Rs iL − Ril imo ) Hca . d¯ = Vm Vm

(2.43)

Under the quasi-static approach, the reference current imo can also be considered constant among a few switching cycles. After performing perturbation and small-signal linearization on (2.43), the small-signal current-to-control transfer function is obtained as

Rs Hca d˜¯ . (2.44) = Vm i˜L Closing the loop by combining the equations of the power stage (2.39) and the control section (2.44), the overall loop gain of the current loop is Gi = −

Rs Vo Hca Vm sL

(2.45) ³

´ s 1 + ωiz Rs Vo Kio ´. ³ = − Vm L s2 1 + s ωip

(2.46)

The frequency response of Gi is plotted in Fig. 2.12 with the converter parameters shown in Table 2.5.

2.6.2 Outer voltage loop modeling The voltage loop of the boost PFC converter under ACM control is depicted in Fig. 2.13. It is assumed that the converter has a very high efficiency with η ≈ 1. By power balance, the averaged diode current iD (t) can be represented as iD (t) =

Vi IL sin2 ωm t, vo (t)

(2.47)

where Vi represents the peak of the input voltage vi (t) and IL the peak of the inductor current iL (t). It is worthy to mention that despite the use of capital letters, Vi , IL and the subsequent Iref are slowly varying variables. We further assume that the output capacitor is large enough to guarantee a small line frequency ripple in the output voltage, such that the average of iD (t) over a rectifier line cycle iD =

IL Vi . 2vo

T 2

can be approximated by (2.48)


39

Here we denote x as the average value of x(t) over a rectified line cycle. ¯ L (t). The behavior of the output voltage can By general averaging, iD (t) = di

Gain [dB]

100 50 0 −50 2 10

3

4

10

5

10

10

Frequency [Hz]

Phase [deg]

−120 −140 −160 −180 2 10

3

4

10

5

10

10

Frequency [Hz]

Figure 2.12: Frequency response of the current loop’s loop gain Gi . L

D

vi

vo io

S

d

C

R

Cvf

Rvl

iL

Current loop & modulator Lowpass 1 / x2 Vff

Rvf

iref

multiplier Rac

vi

vva

Vo, ref

Voltage error amp.

Outer voltage loop Figure 2.13: The outer voltage loop of the boost PFC pre-regulator using ACM control.


40

thus be described by

1 dvo (t) = (iD (t) − io (t)) (2.49) dt C The operating point of this system is time-varying as vo (t) and iD (t) are changing at the rectified line frequency. In order to have a fixed operating point, (2.49) is further averaged over a rectifier line cycle to become 1 dvo = (iD − io ) dt C

(2.50)

Here we notice that d is no longer the control input for the voltage loop under ACM control. Instead, the control input is iD which is related to IL by (2.48). Substituting (2.48) into (2.50), the averaged model of the power stage over a rectified line cycle µ ¶ 1 Vi IL dvo = − io . (2.51) dt C 2vo Since the current loop has a relatively much higher bandwidth, it can be considered becomes

ideal with IL = Iref , where Iref is the peak of the reference current iref . Iref can be regarded as the control input of the voltage loop. If the converter is terminated by a resistive load, (2.51) becomes 1 dvo = dt C

µ

Rearranging (2.52) gives 1 1 dvo2 = 2 dt C

Vi Iref vo − 2vo R

µ

¶

Vi Iref v2 − o 2 R

.

(2.52)

¶ .

Equation (2.53) can be expressed in the s-domain as ¶ µ 2 2 = Vi Iref . vo sC + R

(2.53)

(2.54)

This large-signal model is considered nonlinear if we are interested in the state variable vo instead of vo2 . Nevertheless, this problem can be solved by applying perturbation and small-signal linearization, which is justified by the fixed operating point created by the line-frequency averaging process. The resulting small-signal voltage loop dynamics is ¶ µ 2 = Vi I˜ref + Iref V˜i . (2.55) 2Vo võ sC + R Assuming constant ac input voltage, the resulting small-signal control-to-output transfer function is

¯ Vi R võ ¯¯ = . ¯ I˜ref V˜i =0 2Vo (sCR + 2)

(2.56)


41

Next, we consider the control section. The control voltage generated by the voltage error amplifier can be described by vva (s) = Hv (vo − Vref )

(2.57)

where Hva is the transfer function of the voltage error amplifier shown in Fig. 2.13. Transfer function Hva can be represented by

where GF =

Hva =

GF τF s + 1

(2.58)

Rvf ; Rvl

τF = Rvf Cvf .

(2.59)

The reference current is given by iref = imo Rvl .

(2.60)

Referring to the multiplier’s description in the datasheet [21], imo =

vva Vi | sin ωm t| 2 km β 2 Vi,rms Rac

(2.61)

with km being the multiplier gain constant, β being a scaling factor of

V ff Vi,rms

and Rac

being the resistor connecting the input voltage to multiplier. Substituting (2.61) into

Gain [dB]

50

0

−50

−100 0 10

1

2

10

10

3

10

Frequency [Hz]

Phase [deg]

0 −50 −100 −150 −200 0 10

1

2

10

10

3

10

Frequency [Hz]

Figure 2.14: Frequency response of the voltage loop’s loop gain Gv .


42

(2.60), the amplitude of the reference current becomes 2Kvva Vi

(2.62)

Ril . km β 2 Rac

(2.63)

Iref = where K=

Substituting (2.57) into (2.62) and performing perturbation and small-signal linearization give

2K . I˜ref = Hva võ Vi As a result, the small signal output-to-control transfer function is obtained as ¯ 2KHva I˜ref ¯¯ = . ¯ võ ¯ ˜ Vi

(2.64)

(2.65)

Vi =0

Similarly, by combining the equation of the power stage (2.56) and the control equation (2.65), the overall loop gain of the voltage loop is KRHva Vo (sCR + 2) KRGF ¢ ¡ . = = (τF s + 1) 2Vo 1 + sCR 2

Gv =

(2.66) (2.67)

The frequency response of Gv is plotted in Fig. 2.14 with the parameters shown in Table 2.5.


Table 2.5: Parameters used in the PFC converter model Parameters of PFC converter

Values

Rectified line voltage Vi,rms

110 V

Output reference voltage Vo,ref

270 V

Nominal line frequency fm

50 Hz

Switching frequency fs

100 kHz

Inductance L

1 mH

Output capacitance C

100 µF

Nominal resistive load R

600 Ω

Modulation ramp amplitude Vramp

5V

Sensing resistor Rs

0.25 Ω

Current amp. compensation value : Ril , Riz , Ciz , Cip

3.9 kΩ, 20 kΩ, 1 nF, 86 pF respectively

Voltage amp. compensation value : Rvl , Rvf , Cvf

510 kΩ, 160 kΩ and 56 nF respectively

Other implementation circuit constants : Rac , β, km

620 kΩ, 0.0236 and 1 respectively

43


44

2.7 General Design Procedures In general, the design of power converters can be divided into the power stage design and the subsequent control section design. The former determines the major framework of a power converter by defining the output voltage, the switching frequency and the choice of power components, whereas the latter dictates the converter performance by the choice of control parameters.

2.7.1 Design of the power stage The design of a typical boost PFC converter begins with the power stage. The critical procedures are shown step-by-step as follows [23]: Step 1: Determining the reference output voltage The output voltage of the boost converter should be higher than the peak of the maximum input voltage and a 5 to 10 % margin is recommended for reducing input current distortion during high line and light load conditions. Step 2: Determining the switching frequency The switching frequency should be high enough to achieve low input current distortion and minimize the size of the magnetic components. However, the trade-off is the efficiency because high switching frequency induces excessive switching losses in power devices and hysteresis losses in magnetic components. Step 3: Choosing the inductor The inductor value determines the switching ripple of the input current, which is directly linked to the peak input current flowing through the power components. It also affects the size of the input filter for attenuating the high frequency ripple. The inductor value can be calculated by L=

Vi,min (Vo,ref − Vi,min ) Vo,ref (fs ∆i)

(2.68)

with Vi,min being the peak of the minimum line voltage, Vo,ref the reference output voltage, ∆i the desired current ripple and fs the switching frequency. Step 4: Choosing the capacitor In practice, the capacitor value is mainly determined by the hold-up time ∆Th

2.7 General Design Procedures

45

required by the specification. The hold-up time requirement is related to the minimum output voltage Vo,min the converter needs to offer and the loading condition during the absence of input voltage. The capacitance can be determined by Co =

2Po ∆Th 2 Vo,ref − Vo,min

(2.69)

with Po being the output power. In conjunction with the hold-up time, the output voltage ripple and the ripple current handling capabilities should also be considered. Overall, the choice of the capacitor is a trade-off between performance, cost and space.

Step 5: Selecting the power devices The power switch and the power diode must be at least rated at the maximum peak input current and the maximum output voltage. In practice, 80% derating is recommended to leave safety margins for inrush current and voltage overshoot during startup and transient conditions. Moreover, a power diode with fast recovery is essential for PFC converter to prevent excessive reverse current flowing from the output to the power switch.

2.7.2 Design of control parameters After the power stage is preliminarily designed, we proceed to the control section. The design of the control circuit mainly involves configuring the protection functions and compensation of the error amplifiers.

2.7.2.1 Protection functions and house-keeping functions Most typical PFC controllers provide basic protection functions and house-keeping functions such as peak current limit, over-voltage protection and soft-start function. The configuration of these functions are generally controller-specific and will not be detailed here. Interested readers can refer to the relevant datasheets or application notes for details [23].


46

2.7.2.2 Compensation of current amplifier On the other hand, the design of compensation network depends mainly on the power stage’s parameters and the desired performance such as current distortion and transient response. The design rules are similar among typical PFC controllers. Here we focus on the current amplifier’s compensation first. Referring to Fig. 2.11, a typical PI compensation is adopted with an additional capacitor for high-frequency filtering. The step-by-step procedures are as follows: Step 1: Finding the maximum mid-frequency gain In ACM control, the current amplifier’s output is associated with the inverted waveform of the inductor current. Since this output has to be compared with the ramping signal in the modulator, it is important to ensure that the down-slope of the sensed inductor current is always smaller than the slope of the ramping signal for stable operation. The maximum gain can thus be determined by Vm fs L Riz = . Ril Vo,ref Rs

(2.70)

Hence, Riz can be determined with an arbitrary choice of Ril . Step 2: Deciding the crossover frequency Based upon the current loop gain (2.46) derived in the previous section, the magnitude of the loop gain can be approximated by |Gi | =

Rs Vo Riz , Vm Lωm Ril

(2.71)

assuming that the frequency ω of interest is high enough (> 1 kHz) and the additional pole frequency is located at a much higher frequency. By setting the magnitude of the loop gain to 1, the crossover frequency can be located by ωic =

Rs Vo Riz . Vm L Ril

(2.72)

Step 3: Locating the zero frequency of the PI network The zero of the PI network can be located at wic to ensure a 45◦ phase margin. Hence, the value of Ciz can be computed by Ciz =

1 . ωic Riz

(2.73)

2.7 General Design Procedures

47

Step 4: Locating the pole frequency of the PI network The pole frequency ωip should be located between

fs 2

and fs to filter the high

frequency switching noise. For example, if ωip is chosen to be Cip can be calculated by Cip =

fs , 2

the value of

1 . πfs Riz

(2.74)

2.7.2.3 Compensation of voltage amplifier For the voltage error amplifier, a low-pass filter compensation is adopted as shown in Fig. 2.13. The compensation parameters are designed in the following steps: Step 1: Estimating the output voltage ripple The amplitude of the output voltage ripple can be estimated by Vo,ripple =

Pi,max 2f CVo,ref

(2.75)

with Pi,max being the maximum input power and fm the line frequency in Hz. Step 2: Determining the gain for the output voltage ripples The gain at the rectified line frequency 2ωm determines how much input current distortion will be contributed by the voltage feedback path. For example, in order to limit the second harmonics of the error amplifier output to x %, the maximum gain at 2ωm can be determined by |G2ωm | =

x∆vva 100Vo,ripple

(2.76)

with ∆vva being the output range of the error amplifier. Step 3: Deciding the value of Cvf With the gain at 2ωm being known, the value of Cvf can be decided by Cvf =

1 2ωm |G2ωm |Rvl

(2.77)

Step 4: Locating the crossover frequency Based upon the power stage gain (2.56) derived in the previous section and the result in Step 2, the crossover frequency ωvc can be located graphically.


48

Step 5: Locating the pole frequency The pole frequency of the compensation network can be set to the loop gain’s crossover frequency ωvc to result in a 45◦ phase margin. Then the value of Rvf can be computed by Rvf =

1 ωvc Cvf

(2.78)

In general, the design of the voltage loop is dominated by restricting the input current distortion. This means that the bandwidth of the voltage loop is deliberately constrained to a very low frequency (typically less than half the line frequency) in order to reduce the contamination of the reference current by the output voltage ripple. This usually leads to an excessive phase margin and poor transient performance. These conventional design approaches are simple and straight-forward. They serve to provide a framework and a starting point for practical converter design. However, there are limitations in these approaches. First, a considerable amount of trialand-error and fine-tuning procedures are usually required before achieving the desired steady state and transient response performance. Second, these approaches rely mainly on Bode plots to ensure the control loop stability, which implies that phenomena that cannot be detected by Bode plots are completely ignored. One example is the line frequency oscillation, which is a kind of sustained oscillation associated with the ac line input voltage. Moreover, the issues of poor transient response and the zero-crossing distortion under high operating line frequency are not addressed. Possible solutions to these issues will be explored in this research work.

2.8 Conclusion In this chapter, we have reviewed the definitions of power factor and some common regulatory standards for limiting current harmonics. The fundamentals of the PFC boost converter, including the working principles, the modeling and design procedures, have also been re-visited. On the basis of this discussion, we will move forward to the more advanced research work in the rest of the thesis, in which some unsolved problems related to the boost PFC converter will be examined in detail.

Chapter 3 Line-Frequency Instability of PFC Power Supplies 3.1 Introduction In Chapter 2, we have briefly mentioned about the phenomenon of line frequency instability reported in boost PFC converters and introduced some related works in the literature. In this chapter, we will re-examine the nature of this phenomenon and investigate the conditions of its occurrence in PFC power supplies. As the PFC converter is driven by a sinusoidal voltage source at line frequency which is usually much lower than the switching frequency, the stability phenomenon becomes complicated as forced subharmonic oscillation at half the line frequency may occur due to the nonlinearity of the system. Such forced oscillation was first reported by Orabi et al. [82] through experiments and computer simulations. The oscillation waveforms are captured and shown in Fig. 3.1. Although it has been recognized as a form of “period-doubling” phenomenon, the underlying mechanism can in fact be explained in terms of nonlinear forced oscillation, in which the nonlinearity of the system admits a unity loop gain at half the frequency of the forcing function (rectified line input) that causes oscillation at the line frequency, as analyzed thoroughly by Wong et al. [96] using a generalized averaging technique. Moreover, the literature abounds with methods for studying the stability of the PFC boost converter, such as small-signal methods, large-signal methods, and generalized averaging methods [82], [96], [112], 49

3. Line-Frequency Instability of PFC Power Supplies

50

[95], [32]. In these previous studies, however, a crucial simplifying assumption about the form of load of the PFC boost converter has been made. Essentially, the PFC boost converter has been assumed to be terminated by a resistive load. This assumption has been found causing significant discrepancies in the stability information produced [113]. Specifically, in practice, the PFC boost converter is always terminated by a downstream dc/dc converter which is tightly controlled to produce a well regulated DC output voltage. The difference in stability information between resistor terminated PFC boost converter and the actual two-stage PFC power supply has been reported in [113]. In this chapter, we re-examine the actual two-stage PFC power supply and propose a simple model for the downstream dc/dc converter, the aim being to produce an analytically tractable model for stability analysis and performance evaluation. For the analysis of converters cascaded with downstream dc/dc converters, the load impedance viewpoint has been conventionally used. For instance, the work of Middlebrook [114] addressed the input filter design for switching converters, Ridley [89] considered the stability of the PFC converter with a downstream converter using a small-signal impedance analysis, and Wildrick et al. [93] and Feng et al. [115] studied the stability of distributed power systems using a load impedance approach. These impedance-based analyses, however, are essentially small-signal analyses which rely on the validity of the assumptions of a fixed biasing point and small ripple magnitude in the derivation of all small-signal transfer functions. Under such assumptions, all

(a)

(b)

Figure 3.1: Unstable waveforms of a boost PFC pre-regulator: (a) the output voltage (upper trace) and the inductor current (lower trace) (b) the phase plane trajectory of the output voltage (y-axis) against the inductor current (x-axis).

3.1 Introduction

51

nonlinear terms and the time dependence of the line voltage are ignored. Thus, results produced from such small-signal analyses are not expected to cover the instability phenomena mentioned above in the actual PFC power supplies which do not have a fixed DC biasing point and contain nonlinearities in the interaction of the two cascading stages. From the above brief introduction, we can identify two basic problems in the analysis of PFC power supplies, the first one being the large-signal operation that invalidates analyses with small-signal assumptions, and the second one being the inclusion of downstream dc/dc converters. Although solutions were reported in the literature for the two problems, they were tackled separately. For instance, the large-signal analyses reported previously [95] did not consider downstream converters, and the load impedance analysis for cascaded converters [114], [89] relied on a small-signal assumption. In the rest of this chapter, we extend the work of Wong et al. [96], where largesignal generalized averaging is applied to model PFC converters. The method was very accurate in predicting the stability of single PFC boost converters. However, since a resistively terminated PFC boost converter was considered, the results were not consistent with the actual two-stage PFC power supplies, as pointed out and analyzed in [113]. Our purpose here is to tackle the problem by appropriately modeling the downstream dc/dc converter such that the complete system model can be conveniently and accurately analyzed for stability and performance evaluations. Specifically, we will re-examine the PFC boost converter with a cascaded downstream forward converter. A constant power sink is used to model the downstream forward converter, resulting in a nonlinearly loaded PFC boost converter under average current mode control. We will compare in detail the stability information produced from the proposed model with that found from the actual two-stage system. Simulations and experimental measurements will be used to verify the results. Furthermore, we will demonstrate the use of the proposed model in evaluating the power factor and harmonic distortion performances.


52 iin(t)

∆I ∆I I1 I2 t Tm /2

0

Tm

3 Tm /2

2 Tm

Figure 3.2: Perturbation in rectified input current of PFC converter. Tm = 2π/ωm .

3.2 Line-frequency Instability: A Sustained Oscillation Viewpoint Line-frequency instability is characterized by an apparent “period doubling” of the input current or output voltage waveform. It originates from some perturbation in the environment that propagates through a system’s feedback path which sustains a selected oscillation at the line frequency. The phenomenon can basically be described by the usual Barkhausen’s oscillation criteria. Referring to Fig. 3.2, the perturbed rectified input current waveform can be expressed as ( I1 sin ωm t 0 < t < Tm /2 iin (t) = −I2 sin ωm t Tm /2 < t < Tm

(3.1)

where ωm is the angular line frequency. The rectified input current can be expressed in terms of exponential Fourier series expansion as iin (t) =

∞ X

cn ejnωm t .

(3.2)

n=−∞

The nth harmonic coefficient of the perturbed rectified input current, cn , is 1 cn = Tm

Z

Tm

iin (t)e−jnωm t dt.

(3.3)

0

Thus, the coefficient of the fundamental component, c1 , is c1

1 = Tm

Z

Tm /2

I1 sin(ωm t)e 0

−jωm t

1 dt − Tm

Z

Tm Tm /2

I2 sin(ωm t)e−jωm t dt

3.3 Modeling with Constant Power Sink

53 v PFC

boost PFC converter

average current-mode control

dc/dc forward converter

feedback control tightly regulated dc/dc converter

(a)

boost PFC converter

Po

v PFC constant power sink

average current-mode control

(b)

Figure 3.3: Schematic of (a) the two-stage PFC power supply, and (b) the proposed model using a constant-power-sink termination. ¸ I1 − I2 . = 0−j 4 ·

(3.4)

Also, |c1 |2 = a21 /4+b21 /4, where a1 and b1 are the amplitudes of the fundamental cosine and sine components of the following general Fourier series expansion respectively. ∞

a0 X + [an cos(nωm t) + bn sin(nωm t)] . iin (t) = 2 n=1

(3.5)

Thus, the magnitude of the disturbance at the line frequency (i.e., half the frequency of the rectified sine wave) is q I1 − I2 = ∆I a21 + b21 = 2|c1 | = 2

(3.6)

where ∆I is the amplitude of the disturbance. Equation (3.6) reflects that the oscillation observed in the input current can be associated with the amplitude of sine wave signal at line frequency. If the system has a loop that could sustain oscillation at the line frequency (half the frequency of the rectified sine wave), oscillation occurs and manifests itself as doubling of the period. The analysis can therefore be proceeded by finding the loop gain at the line frequency. This simple approach will be adopted. The gist of the solution is the derivation of accurate Fourier components using a generalized averaging approach [96], as will be demonstrated in Section 3.4.

3.3 Modeling with Constant Power Sink A typical two-stage PFC power supply consists of a PFC pre-regulator which is cascaded by a downstream dc/dc converter, as depicted in Fig 3.3 (a). This cascade structure has become a very popular configuration for achieving both unity power factor


54

and tight output voltage regulation [8]. The complete system is of relatively high order, with four main storage circuit elements (two from the boost PFC stage and two from the downstream forward converter) and two first or second-order compensators (one from the boost PFC stage and another from the downstream forward converter). Analysis is thus rather complicated. In this section we propose a major simplifying step, which drastically reduces the complexity and yet preserves the essential features. As pointed out earlier, the downstream dc/dc converter was treated as a resistive load in some previous studies of the PFC boost power supply. The results were found to be inconsistent with the experimentally observed behavior. Our job here is to produce a low-frequency model of the downstream dc/dc converter such that a convenient overall model can be used to study the system. We first observe that the downstream dc/dc converter has a tightly regulated output voltage. Regardless of the fluctuation in its input voltage (i.e., output voltage of the PFC boost stage), the downstream dc/dc converter maintains a well regulated DC output. In other words, its output power is constant under a fixed loading condition. The input power should also be constant on the average. Thus, if we consider lowfrequency behavior, the downstream dc/dc converter is simply a constant power sink,

L

vPFC

D

iPFC vi

C

S1

Po v PFC

iL

current amplifier compensator iref p

GF

τ F s +1

Lowpass 1 / x2

VPFC, ref

Figure 3.4: Circuit schematic of the proposed model consisting of a boost PFC stage terminated by a constant power sink.

3.4 Derivation of Stability Criterion

55

as shown in Fig. 3.3 (b). As there are two output voltages involved in a PFC power supply, we use vPFC to denote the output voltage of the PFC stage and vo the output voltage of the downstream converter to avoid the mixup of variables. Suppose the load is fixed, and the power output is Po . Then, the current drawn by the downstream converter can be expressed as

Po (3.7) η vPFC (t) vPFC (t) where η is the efficiency of the dc/dc converter. To simplify the calculation, we assume iPFC (t) =

Po

≈

η ≈ 1. Based on this simplified model, analysis of the converter’s stability can be readily performed. It is worth mentioning that as the downstream dc-dc converter is modeled as an ideal constant power load and the whole system by a low-frequency model, we will confine our studies to line-frequency instability. It is thus understood that this model is not capable of predicting instability at high frequencies.

3.4 Derivation of Stability Criterion 3.4.1 Generalized averaged model For the boost PFC stage, only CCM is considered here as it is commonly used for medium to high power applications. Average current-mode control is adopted for its better noise immunity and its popularity in industry. Fig. 3.4 shows the simplified schematic of our proposed model. The input current of the boost converter is forced to follow the sinusoidal input voltage envelope under average current-mode control. The “ideally shaped” input current waveform can be expressed as √ p(t) 2 |sin ωm t| iin (t) = Vi,rms p(t) vi (t) = 2 Vi,rms

(3.8) (3.9)

where p(t) is a control variable which is physically analogous to instantaneous power. By averaging over the switching period, the power stage can be modeled as diin (t) dt Po dvPFC (t) + (1 − d)iin (t) = C . dt vPFC (t)

(1 − d)vPFC (t) = vi (t) − L

(3.10) (3.11)


56

After combining (3.10) and (3.11) and eliminating d, we get L diin (t)2 C dvPFC (t)2 = −Po + iin (t)vi (t) − . 2 dt 2 dt

(3.12)

The energy stored in the inductor L is negligible compared to the energy stored in the capacitor C operating near the line frequency, i.e.,

C dvPFC (t)2 2 dt

À

L diin (t)2 . 2 dt

Thus, we

have C dvPFC (t)2 ≈ −Po + 2p(t) sin2 ωm t 2 dt = −Po + p(t)(1 − cos 2ωm t)

(3.13) (3.14)

For the voltage feedback compensation, a simple first-order filtering is employed. Hence, the feedback loop can be modeled as P (s) −GF = VPFC (s) τF s + 1

(3.15)

where GF is the overall dc gain, and τF is the time constant of the voltage error amplifier. The implementation of GF and τF depends on the choice of the actual feedback circuit. A particular implementation will be shown in Section 3.8, where GF and τF will be given in terms of practical component values. In the time domain, (3.15) is written as

dp(t) + p(t) = −GF (vPFC (t) − VPFC,ref ). dt Thus, the system is described completely by (3.14) and (3.16). τF

(3.16)

3.4.2 Fourier series expansion As mentioned earlier, instability in the PFC stage manifests as oscillation at ωm , which is half the frequency of the input rectified sine wave and hence has been regarded as a “period-doubling” phenomenon. Such an oscillation appears also in the control signal and the output voltage waveform. In this section, we will derive the loop gain corresponding to this particular frequency, from which a stability criterion of the PFC boost stage can be derived. We begin with taking the Fourier series expansion of every state variable with the fundamental frequency being the line frequency, ωm . To simplify the calculation, we consider the first three terms, namely, the dc component, the fundamental frequency


57

component at ωm , and the second harmonic component at 2ωm . In general, a variable c(t) is expressed as c(t) = co + c1 ejωm t + [c1 ejωm t ]∗ + c2 ej2ωm t + [c2 ej2ωm t ]∗ where superscript ∗ denotes complex conjugation, and Z ωm t x(τ )e−jnωm τ dτ cn = 2π t− ω2π

(3.17)

(3.18)

m

where n = 0, 1, and 2. Adopting the terminology used in the prior work [96], we will refer to such truncation of Fourier series as “second averaging” to distinguish it from the first averaging which has been performed over the switching period. The complex Fourier coefficients of the square function c(t)2 can be expressed in terms of cn by £ £

c(t)2

¤ 0

= c2o + 2|c1 |2 + 2|c2 |2

¤ c(t)2 1 = 2 [co c1 + c1i c2i + c1r c2r + j (c1r c2i − c1i c2r )] £ ¤ c(t)2 2 = c21 + 2co c2

(3.19) (3.20) (3.21)

with [.]n representing the nth harmonic coefficient of the variable in the bracket. Likewise, the Fourier coefficients of the derivative function

dc(t) dt

can also be ex-

pressed in terms of of cn by ¸ dco dc(t) = dt 0 dt ¸ · dc1 dc(t) = + jωm c1 dt 1 dt ¸ · dc2 dc(t) = + 2jωm c2 dt 2 dt ·

(3.22) (3.23) (3.24)

To avoid confusion due to possible mix-up of subscripting indices, we denote the nth harmonic coefficient of vPFC (t) by xn , and the nth harmonic coefficient of p(t) by yn , with n = 0, 1 and 2. Hence, the complex Fourier expansions of vPFC (t) and p(t) are expressed as vPFC (t) = xo + x1 ejωm t + [x1 ejωm t ]∗ + x2 ej2ωm t + [x2 ej2ωm t ]∗ p(t) = yo + y1 ejωm t + [y1 ejωm t ]∗ + y2 ej2ωm t + [y2 ej2ωm t ]∗

(3.25) (3.26)


58

Each coefficient is a complex number which can be expressed in Cartesian form as xn = xnr + jxni

(3.27)

yn = ynr + jyni

(3.28)

where xnr , ynr refer to the real parts and xni , yni refer to the imaginary parts. Applying (3.19)–(3.21) and (3.22)–(3.24) to (3.14) results in three equations corresponding to the dc component, the fundamental frequency component and the second harmonic component: ¢ C d ¡ 2 x0 + 2x21r + 2x21i + 2x22r + 2x22i + Po = yo − y2r 2 dt

(3.29)

C d (x0 x1 + x1r x2r + x1i x2i + j(x1r x2i − x1i x2r )) 2 dt jωm C y1 (y1 )∗ (x0 x1 + x1r x2r + x1i x2i + j(x1r x2i − x1i x2r )) = − (3.30) + 2 2 4 ¢ ¡ ¢ C d ¡ y0 2x0 x2 + x21 + jωm C 2x0 x2 + x21 = y2 − . (3.31) 2 dt 2 Likewise, putting (3.18) in (3.16) results in τF

dy0 + y0 = −GF (x0 − VPFC,ref ) dt

dy1 + (jωm τF + 1) y1 = −GF x1 dt dy2 + (j2ωm τF + 1) y2 = −GF x2 . τF dt τF

(3.32) (3.33) (3.34)

In the steady state, all time derivatives are zero. Thus, (3.30) can be simplified as jωm C [xo x1 + x1r x2r + x1i x2i + j (x1r x2i − x1i x2r )] = y1 − By equating coefficients of real parts and imaginary parts, we get ¸ · 3xo y1i − 3x2r y1i + x2i y1r x1r = − 2ωm C (x22i − x2o + x22r ) ¸ · −3x2i y1i − xo y1r − x2r y1r , x1i = − 2ωm C (x22i − x2o + x22r )

(y1 )∗ . 2

(3.35)

(3.36) (3.37)

which can be put in the following matrix form: " #" " # # 0 x2i 3xo − 3x2r x1r y1r −1 = 0 2ωm C (x22i + x22r − x2o ) −xo − x2r 3x2i x1i y1i x1 = A · y10 .

(3.38)


59

Here y1 is denoted as y10 in order to distinguish the power signal from the one that propagates through the control loop. Clearly, A is the signal transfer function of the boost power stage. Now, to find the loop gain, we need to find the signal transfer function for the feedback circuit which is the other constituent part of the closed loop in addition to the boost power stage. Enforcing the steady-state condition to (3.33), we have (jωm τF + 1)(y1r + jy1i ) = −GF (x1r + jx1i ),

(3.39)

which gives "

y1r y1i

#

−1 = 2 1 + τF2 ωm

"

GF

GF τF ωm

−GF τF ωm

GF

#"

x1r

#

x1i

y1 = B · x1

(3.40)

where B is the signal transfer function of the feedback circuit. Substituting (3.38) into x1r and x1i of (3.40), we have y1 = B · Ay10 = My10

(3.41)

Thus, from (3.41), M is defined as the round-trip signal transfer function given by M = B·A " # G G τ ω −1 F F F m = 2 2 1 + τF ωm −GF τF ωm GF " # x2i 3xo − 3x2r −1 . · 2ωm C (x22i + x22r − x2o ) −xo − x2r 3x2i

(3.42)

Since the magnitude of the ωm component is much smaller than that of the 2ωm component or the dc components, (3.29) and (3.31) can be approximated as C d 2 (xo + 2x22r + 222i ) + Po = yo − y2r 2 dt d yo C (xo x2 ) + jωm C(2xo x2 ) = y2 − . dt 2

(3.43) (3.44)

Combining (3.32), (3.34), (3.43) and (3.44), and imposing the steady-state condition,


60

we get G2F (VPFC,ref − xo ) 2 x + 4C 2 ω 2 (1 + 4τ 2 ω 2 )x2 ) 2 (G2F − 8CGF τF ωm o m F m o 2 GF ωm (VPFC,ref − xo ) (−GF τF + C(1 + 4τF2 ωm )xo ) = 2 2 2 2 2 2 GF − 8CGF τF ωm xo + 4C ωm (1 + 4τF ωm )x2o 2 G2F (VPFC,ref − xo ) (GF − 4CτF ωm xo ) = 2 2 x + 4C 2 ω 2 (1 + 4τ 2 ω 2 )x2 ) 2 (GF − 8CGF τF ωm o m F m o 2 −GF ωm C (VPFC,ref − xo ) xo = . 2 2 x + 4C 2 ω 2 (1 + 4τ 2 ω 2 )x2 GF − 8CGF τF ωm o m F m o

x2r =

(3.45)

x2i

(3.46)

y2r y2i

(3.47) (3.48)

With the assumption of xo = VPFC,ref , all the second harmonic components become zero. Thus, (3.42) can be further simplified as GF M= 2 ) 2xo ωm C(1 + τF2 ωm

"

τF ωm

−3

1

3τF ωm

# .

(3.49)

The magnitude of the total loop gain of the line frequency component y1 is denoted by |Ty1 |, which is obtained from the eigenvalue of M. The two eigenvalues are given by p 2 2GF τF ωm + GF −3 + τF2 ωm λ1 = . 2 ) 2ωm xo C(1 + τF2 ωm p 2 2GF τF ωm − GF −3 + τF2 ωm λ2 = . 2 ) 2ωm xo C(1 + τF2 ωm

(3.50) (3.51)

By substituting the practical values used in experiments shown in Table 3.1, λ2 yields a value of around 0.5, while λ1 yields a value of around 1. Therefore, λ1 is the eigenvalue of interest and thus, p 2 2GF τF ωm + GF −3 + τF2 ωm |Ty1 | = . 2 ) 2ωm xo C(1 + τF2 ωm

(3.52)

|Ty1 | < 1.

(3.53)

For stable operation,

Thus, the stability criterion of the PFC stage terminated with a constant power sink, which effectively represents the two-stage PFC power supply, is given by ´ ³ p 2 GF 2τF ωm + −3 + τF2 ωm , xo > 2 ) 2ωm C(1 + τF2 ωm

(3.54)

3.5 Design-Oriented Stability Boundaries

61

which differs significantly from the stability criterion derived in [96] for the PFC boost converter terminated with a resistive load. For convenience of comparison, we reproduce the stability criterion for the PFC boost converter terminated with a resistive load as follows [96]: q i h 1 2 2 2 2 2 2 2 2 2 GF R ωm CRτF − 2 + 1 − 4ωm CRτF − 3ωm τF + 4 ωm C R (ωm τF − 3) xo > . 2 C 2 R2 )(1 + ω 2 τ 2 ) (4 + ωm m F (3.55) By inspecting (3.54) and (3.55), both criteria reveal that the line-frequency stability is dependent upon GF , τF , C and xo . However, for the resistor terminated PFC boost converter, the load resistance R or equivalently the output power affects the stability, whereas for the constant-power-sink terminated PFC boost converter, the output power does not play a role in determining the stability.

3.5 Design-Oriented Stability Boundaries For ease of comparison and for facilitating practical design, we present the stability criterion in various perspectives of the parameter space. Basically we present (3.54) and (3.55) graphically with y-axis being VPFC and x-axis being a particular choice of parameter. Then, the stability boundaries clearly show the lower limits of VPFC below which the system will become unstable and exhibit oscillation at the line frequency. Fig. 3.5 shows the stability boundaries plotted on the R–VPFC plane with different parameters and compares the two models of the resistor terminated PFC boost converter and constant-power-sink terminated PFC boost converter. From the results, we generally observe that the constant-power-sink terminated PFC boost converter has a more restricted stable region. To probe further, Fig. 3.6 shows the stability boundaries on a few other parameter planes.


62

320

320

GF = 14 A

STABLE

300

280

280

GF = 12 A

C = 66 µF

260

240

VPFC [V]

VPFC [V]

260

GF = 10 A

220 200

240 220

C= 83 µF

200

180

180

UNSTABLE

UNSTABLE

Resistive load terminated Constant power sink terminated

160 140 600

C = 56 µF

STABLE

300

800

1000

1200

1400

1600


160

1800

140 600

2000

800

Equivalent resistive load R [Ω]

1000

1200

1400

1600

1800

2000


(a)

(b) 320

STABLE 300 τF = 8 ms

280

VPFC [V]

260 τF = 10 ms

240 220

τF = 12 ms

200 180

UNSTABLE


160 140 600

800

1000

1200

1400

1600

1800

2000


(c)

Figure 3.5: Stability boundaries of the resistor terminated model and the proposed constant-power-sink terminated model. (a) C = 66 µF, τF = 9 ms; (b) GF = 12 A, τF = 9 ms; (c) GF = 12 A, C = 66 µF.

3.5 Design-Oriented Stability Boundaries

63

450

450

400

400

STABLE

C = 56 µF

STABLE

C = 66 µF

VPFC [V]

VPFC [V]

τF = 8 ms

350

350 300

C = 83 µF 250

τF = 10 ms

300

τF = 12 ms

250 200

200

UNSTABLE

UNSTABLE

150

150

100

100 9

10

11

12

13

14

15

50

16

60

70

80

GF [A]

90

100

110

120

C [µF]

(a)

(b) 450 400

VPFC [V]

STABLE

GF = 14 A

350 300

GF = 12 A

250

GF = 10 A

200

UNSTABLE

150 100 6

7

8

9 τF [ms]

10

11

12

(c)

Figure 3.6: Stability boundaries of the proposed constant-power-sink terminated model plotted in various parameter planes. (a) GF –VPFC plane with τF = 9 ms; (b) C–VPFC plane with GF = 12 A; (c) τF –VPFC plane with C = 66 µF.

64


3.6 Simulation Results Simulations using WinSPICE are performed to verify the accuracy of our modeling solution. Two averaged models, namely, the PFC converter model terminated with the constant power sink and the two-stage PFC power supply model terminated with a forward converter are constructed. Both models are set to exhibit line frequency oscillation deliberately under the similar circuit parameters such as the input voltage, output power and compensation parameters in the voltage error amplifier for fair comparison. The simulated waveforms of the two model are shown in Fig. 3.7. Comparing the waveforms between Figs. 3.7(a) and (b), the inductor current waveform of the constant power sink terminated system resembles that of the two stage system with small deviation in the current amplitude. Further, the accuracy of the proposed modeling solution is evaluated by comparing the stability boundaries given by the two models. The resulting boundaries are plotted in various perspectives of the parameter space in Fig. 3.8 and Fig. 3.9. From the figures, the stability boundaries given by the two models are consistent. Therefore, the simulation results verified that our modeling solution of using a constant power sink provides an accurate portrait of the stability of the two-stage PFC power supply.

3.6 Simulation Results

65

(a)

(b)

Figure 3.7: Simulated waveforms of line frequency oscillation occurred in (a) the twostage PFC power supply model with forward converter termination; (b) the PFC converter model terminated with constant power sink. 1st row: Rectified input voltage vi [V]; 2nd row: Inductor current iL [A]; 3rd row: PFC converter output voltage VPFC [V]; 4th row: PFC converter output current iPFC [mA];


66

300

280

Boost stage output voltage VPFC (V)


300

STABLE 260

GF1 = 11.6

240

GF1 = 9.86

220

200

UNSTABLE Forward converter terminated. Constant power sink terminated.

180

160

280

STABLE 260

C1 = 69 uF

240

220

C1 = 83 uF

200


180

160 0

50

100

150

200

0

50

PFC converter output power Po (W)

100

150

200


(a)

(b)


300

280

STABLE 260

TF1 = 8.6 ms

240

TF1 = 10.6 ms

220

200


180

160 0

50

100

150

200


(c)

Figure 3.8: Stability boundaries plotted on the PFC stage’s output voltage VPFC against the output power Po . The circuit parameters are: GF = 11.6, C = 69 µ F, τF = 8.6 ms. Each figure corresponds to only one parameter change.


67

14

16

UNSTABLE

12

VPFC = 240V

11

10

VPFC = 210V

9

STABLE 8

Forward converter terminated. Constant power sink terminated.

7

UNSTABLE

15

Boost stage feedback gain GF1


13

C1 = 83 uF

14

13

12

C1 = 69 uF

11

STABLE 10


9

6

8 0

50

100

150

200

0

50


100

150

200


(a)

(b) 16

UNSTABLE


15

14

TF1 = 10.6 ms 13

12

TF1 = 8.6 ms

11

STABLE 10


9

8 0

50

100

150

200


(c)

Figure 3.9: Stability boundaries plotted on the PFC stage’s feedback gain GF against the PFC stage’s output power Po . The circuit parameters are: VPFC = 240 V, C = 69 µ F, τF = 8.6 ms. Each figure corresponds to only one parameter change.


68

3.7 Experimental Measurements A two-stage PFC power supply prototype has been constructed for verification purposes. The schematic of the experimental circuit is shown in Fig. 3.10. The PFC pre-regulator is a non-isolated boost converter under average current-mode control accomplished by UC3854A PFC controller, as detailed in Fig. 3.11. The downstream converter is a standard double-wheeler forward converter using conventional voltagemode control accomplished by a standard UC3825N PWM controller. The key circuit parameters are shown in Table 3.1. 1mH

IRFL460 vPFC(t) STW26NM60 APT15D L 0.01mH MUR 60B 460 STW26 3:1 NM60 540u APT15D 66u 60B C

0.1u 50Hz 70V,rms vi(t)

MUR4 60

0.25

da o L

STW26NM60

Rs PWM Control UC3825N

PFC Control UC3854A

Figure 3.10: Experimental circuit of the complete two-stage PFC power supply. 0.25

Rs Rmo

1N5819

Ril

3.9k

560pF

1.8k

3.9k

10k

20k 6nF

Vcc 18V 5

vi(t)

22k 100 F

Rff1

470k

Vff Cff1

0.1 F

Rac Rff2 47k

Rff3

22.5k

620k

Vref

2.2 F

250pF 4

3

2

MC34152

9 16

15

driver 1N5819

10

UC3854A

7

6

Cvf

Rvf

180k

8

13

Cff2

14

12

1

1 F

1 F

560pF

200pF

15k

47nF

11

Rvd

vPFC

Rvl 510k

5k

Figure 3.11: Detailed schematic of PFC controller circuit.

3.7 Experimental Measurements

parameter y

69

stable region

A

PFC performance degrades as linefrequency oscillation becomes severe

B C D unstable region

parameter x

Figure 3.12: Symbolic representation of different operating regions of the PFC converter. Region A is stable region. Regions B, C, D are unstable regions, with gradual increase in severity of line-frequency oscillations.

3.7.1 Line-frequency instability and its detection When line-frequency instability occurs, “period-doubling” waveforms can be observed in the input current and the output voltage. However, at the early stage of instability, the phenomenon is not obvious and the effect on the PFC converter performance is subtle. The performance deteriorates gradually as the circuit parameters move deeper into the unstable region. The operation can be divided into 4 regions in the parameter space, as shown symbolically in Fig. 3.12.

Table 3.1: Circuit parameters used in experiments Parameters of PFC stage

Values

Rectified line voltage Vin,rms

70 Vrms, 50 Hz

PFC stage reference output voltage VPFC,ref

240 V

Switching frequency fsw1

100 kHz

Inductance L

1 mH


66 µF

Nominal voltage feedback gain GF

11.6 A

Nominal feedback time constant τF

8.6 ms

Forward converter reference output voltage Vo,ref

24 V

Forward converter switching frequency fsw2

100 kHz


70

Region A The converter is under normal stable operation. The set of parameters is within the “stable region”.

Region B As the parameters move across the stability boundaries, the converter begins to show slight oscillation. The input current and output ripple start to lose their stability as a rectified sinusoidal waveform. Besides inspection of waveforms, such instability is also reflected by a more than 50% increase in the 2nd harmonic of the input current.

Region C As the circuit parameters move further into the unstable region, the oscillation becomes vigorous, along with a significant increase in the 2nd harmonic amplitude of the output ripple voltage and in the input current.

Region D As the parameters move deeper into the unstable region, the voltage error amplifier “saturates” with its output swung below a certain threshold voltage for half of the line period. Once saturation occurs, the input current goes to zero for half of the line period. The power factor drops abruptly by 20% to 30%. The output voltage ripple and the peak input current increase drastically. At this stage, the PFC converter is under very high current stress due to the high peak input current, as well as high voltage stress due to the large output voltage ripple. In Fig. 3.13, panels on the left show the measured waveforms of the rectified iin and vPFC for Regions A to D; and panels on the right show the corresponding input current harmonics and waveforms before rectification.


71 Stage A 1.2 2 Input current [A]

Input current [A]

1 0.8 0.6

1 0 -1

0.4

-2 -15 -10 -5

0.2

0

5

10

15

Time [ms]

0 -1

0

1

2

3

4

5

6

7

8

9 10 11 12 13 14 15 16

Nth Harmonics

(a)

(b) Stage B 1.2 2 Input current [A]

Input current [A]

1 0.8 0.6

1 0 -1

0.4

-2 -15 -10 -5

0.2

0

5

10

15

Time [ms]

0 -1

0

1

2

3

4

5

6

7

8

9 10 11 12 13 14 15 16

Nth Harmonics

(c)

(d) Stage C 1.2 2 Input current [A]

Input current [A]

1 0.8 0.6

1 0 -1

0.4

-2 -15 -10 -5

0.2

0

5

10

15

Time [ms]

0 -1

0

1

2

3

4

5

6

7

8

9 10 11 12 13 14 15 16

Nth Harmonics

(e)

(f) Stage D 1.2 3 Input current [A]

Input current [A]

1 0.8 0.6

2 1 0

0.4

-1 -15 -10 -5

0.2

0

5

10

15

Time [ms]

0 -1

0

1

2

3

4

5

6

7

8

9 10 11 12 13 14 15 16

Nth Harmonics

(g)

(h)

Figure 3.13: Measured data for operations in (a)-(b) region A; (c)-(d) region B; (e)-(f) region C; and (g)-(h) region D. Upper trace of left panels is output ripple voltage (10 V/div); lower trace of left panel is rectified input current (500 mA/div). Panels on the right are histograms of input current harmonics and waveforms before rectification. In the x-axis, “0” represents the dc component, “1” represents 50 Hz component, etc.


72

3.7.2 Comparison of resistor terminated and constant-power-sink terminated PFC Converters Line-frequency instability degrades the PFC converter performance, as mentioned previously. Specifically, the power factor decreases, the output ripple voltage increases, and the peak input current also increases. Fig. 3.14 presents the deterioration of these performance parameters as the system goes from the stable region to deep unstable region. We also compare the conventional resistor terminated PFC converter and the complete two-stage PFC power supply. Both systems operate at the same output power and with the set of same circuit parameters. For the complete two-stage system, the degradation begins at a much lower value of GF than the resistor terminated system. This once again verifies that the two-stage system is more prone to line-frequency instability.

3.7.3 Verification of the stability boundaries In this subsection, the stability boundaries derived in Section 3.4 are verified experimentally. Measured data are plotted along with the analytical results to facilitate comparison, as shown in Figs. 3.15 and 3.16. The measured data generally match well with the analytical results. The small discrepancies can be attributed to the following problems. First, in our analysis approach, only the first three harmonics are considered. Errors are introduced due to the omission of higher order harmonics. Second, in our analysis it has been assumed that xo = VPFC,ref , which incurs a small DC offset. Third, in the practical circuit, the internal multiplier gain varies slightly as the load changes, resulting in error in the loop gain calculation. The measured results are therefore expected to deviate slightly from the analytical results.


73

A

0.95

B

Percentage increase in output voltage ripple [%]

220

A

1

C

B C

Power factor

0.9 0.85 0.8 0.75

D 0.7 0.65

D Resistive load terminated Forward converter terminated

0.6

Resistive load terminated Forward converter terminated

200 180

D

160

D

140 120 100 80 60 40 20

A

0

B C

A

B C

-20 8

9

10

11

12 GF [A]

13

14

15

16

8

9

10

(a)

11

12 GF [A]

13

14

15

16

(b)

Percentage increase in peak input current [%]

120 Resistive load terminated Forward converter terminated

100

D D

80 60 40 20

A

B

9

10

C

A

B

C

0 8

11

12 GF [A]

13

14

15

16

(c)

Figure 3.14: Performance degradation due to line-frequency instability. (a) Power factor; (b) output ripple voltage; and (c) peak input current.


74

280

STABLE

280 Forward converter terminated

260

260

240

240

220

220

STABLE

VPFC [V]

VPFC [V]

Forward converter terminated Resistive load terminated 200 180

200 180

Resistive load terminated

UNSTABLE 160

160 Analytical results Experimental data

140 120 600

800

1000

1200

1400

1600

1800

140 120 600

2000

800


1000

1200

1400

1600

1800

2000


(a)

(b)

280

280

STABLE

260

STABLE

260

240


200 180

Forward converter terminated

220

VPFC [V]

220

VPFC [V]

Analytical results Experimental data

UNSTABLE

200 Resistive load terminated

180 Resistive load terminated

160

160

120 600


UNSTABLE

140

800

1000

1200

1400

1600


(c)

1800

2000

120 600


UNSTABLE

140

800

1000

1200

1400

1600

1800

2000


(d)

Figure 3.15: Experimental verification and comparison of stability boundaries between the resistor terminated model and the complete two-stage system. (a) GF = 11.6 A, C = 66 µF, τF = 8.6 ms; (b) GF = 9.86 A, C = 66 µF, τF = 8.6 ms; (c) GF = 11.6 A, C = 83 µF, τF = 8.6 ms; (d) GF = 11.6 A, C = 66 µF, τF = 10.6 ms.


75

360

340 340

320

STABLE 320

C = 55.35 µF

280 VPFC [V]

300

VPFC [V]

STABLE

300

280

C = 66 µF

260

τF = 6.4 ms

260 240 220

240

UNSTABLE

180


200 10

11

12

13


160

180 9

τF = 8.6 ms

UNSTABLE

200

220

14

50

15

55

60

65

GF [A]

70

75

80

85

90

C [µF]

(a)

(b) 340 320

STABLE

300 VPFC [V]

280

GF = 14.24 A

260 240 220

GF = 11.6 A

200

UNSTABLE

180


160 6

7

8

9

10 τF [ms]

11

12

13

14

(c)

Figure 3.16: Experimental verification of stability boundaries of the constant-powersink terminated model in various parameter space. (a) GF –vPFC plane with τF = 8.6 ms; (b) C–vPFC plane with GF = 11.6 A; (c) τF –vPFC with C = 66 µF.


76

3.8 Applications In this section, we attempt to apply the stability criterion derived earlier to the design of the voltage feedback loop in PFC converters. We will develop some guidelines for ensuring stable operation of PFC converters. The design and optimization of boost PFC converters has been widely discussed in the literature [22], [23], [116], [117]. Essentially, for simple first-order voltage loop compensation, for instance, the design begins with determining the output capacitor value according to the hold-up time requirement. Then, the output voltage ripple at 2ωm can be calculated. Since this ripple is the main contributor to the 3rd harmonic component in the input current, the error amplifier gain at 2ωm has to be restricted according to the required 3rd harmonic tolerance level. Based on the error amplifier gain, the required feedback capacitor and the feedback resistor can then be determined. Typically, the resulting voltage loop bandwidth is half or less than the line frequency, resulting in rather poor transient response. To improve the transient performance without adding extra circuitry, input current distortion is the usual trade-off considered [68], [118]. In fact, when the voltage loop gain is increased to a certain level, the input current distortion may increase, and the converter may become unstable, as indicated in the criterion presented in (3.54). Thus, during the design process, stability need to be thoroughly evaluated. Based on the analysis and experimental results presented in the foregoing sections, the results predicted by the conventional resistor terminated model have turned out to be over-optimistic. In practice, the proposed constant-power-sink terminated model should be more accurate in providing stability information of PFC converters, especially when the output capacitance is limited to a small value. For a quick reference, normalized stability boundaries can be plotted for predicting the PFC converter’s stability, which is shown in Fig. 3.17. For comparison, GF and τF have to be mapped to the actual circuit parameters. From Fig. 3.11 and the UC3854A IC datasheet, we have GF τF

Rvf Rmo = Rvi Rs Rac = Rvf Cvf

µ

Vi,rms Vff

¶2 km

(3.56) (3.57)

where all component variables mentioned above are shown in Fig. 3.11, i.e., Rvf are

3.8 Applications

77 35

C = 47 µF

-1

VPFC/GF [VA ]

STABLE 30

C = 56 µF

25

C = 68 µF

20

C = 82 µF C = 100 µF

15

C = 120 µF C = 150 µF

10

UNSTABLE 5 6

7

8

9 τF [ms]

10

11

12

Figure 3.17: Design aid to verify stability of the PFC converter

Rvi are the feedback resistor and input resistor of the voltage error amplifier, respectively; Cvf is the feedback capacitor; Ril is the input resistor of the current amplifier; Rs is the current sensing resistor; Rac is the resistor converting the input voltage envelope into current, which is fed into the multiplier input; Vff is the feedforward voltage analogous to the filtered input voltage; and km is the internal gain of the multiplier which has been found experimentally to be 1.12 V. To improve stability, an effective way is to increase the output capacitor value, the price to pay being the higher component cost and extra space. Besides, the overall dc gain and the time constant can be adjusted at the expense of degraded transient and regulation performances. In some cases where the output voltage of the pre-regulator stage is not tightly specified, the reference output voltage can be increased to improve stability. Table 3.2 summarizes the tradeoffs for stability improvement.


78

Table 3.2: Summary of performance tradeoffs for stability improvement Parameters

Adjusting

Increase/decrease

components

for stability

Other benefits

Performance tradeoffs

improvement C

C

Increase

Smaller output ripple

Cost

Lower current distortion

Space

Smaller Transient overshoot Longer holdup time GF

Rvf , Rvi ,

Decrease


Rmo , Rs

Regulation Transient response

Rff1 , Rff2 Cff1 , Cff2 Rff3 , Rac τF

Cvf , Rvf

Increase


Transient response

VPFC

Rvi , Rvd

Increase

Longer holdup time

Voltage stress

3.9 Discussion In a two-stage PFC power supply, sometimes the downstream converter is synchronized with the PFC pre-regulator in order to reduce the electromagnetic interference (EMI) and the switching noise generated by two different switching frequencies. Some synchronization schemes are also introduced to reduce the current ripple flowing into the output capacitor of the PFC converter [119]. Thus it becomes an interesting question whether these synchronization methods affect the low-frequency stability of the PFC pre-regulator. A series of tests by simulations and experiments have been conducted, in which the downstream converter is synchronized with the PFC pre-regulator in a way such that the two main switches turn on with a certain degree of phase shift. Different degree of phase shifts (0◦ , 90◦ , 180◦ and 270◦ ) have been attempted, as shown in Fig. 3.18. It turns out that the effect of these synchronization schemes on the lowfrequency stability is insignificant. Although reduced ripple current can be observed under the synchronization with 180◦ phase shift, the output voltage level and the line frequency ripple remain unchanged. The reason for this can be explained by the decoupling of the control loop dynamics due to the difference in time scale. Considering that the line frequency instability is exhibited in the voltage loop which has a narrow bandwidth lower than the line frequency, the slow dynamic response effectively makes it

3.9 Discussion

79

immune to any input disturbance at the switching frequency. The concept of dynamics decoupling will be further discussed in the later chapters on the control design. v

gs

v

gs

T

s

d

T

s

t

T

t d

DS s

T

DS s

d

PFCTs

0o phase shift

d

(a) v

gs

90o phase shift

PFCTs

(b) v

T

s

gs

T

s

t d

d

t

T

DS s

135o phase shift

T

PFC s

(c)

d

T

PFC s

d

T

DS s

270o phase shift

(d)

Figure 3.18: Synchronization between the boost PFC stage and the downstream converter with (a) 0◦ phase shift; (b) 90◦ phase shift; (c) 135◦ phase shift and (d) 270◦ phase shift. Ts is the switching cycle, dPFC and dDS are the duty cycles of the boost PFC stage and the downstream converter respectively.

80


3.10 Conclusion In this chapter, the low-frequency instability in boost PFC converters is examined in the light of sustained oscillation at the line frequency. A simple model of a two-stage PFC power supply has been introduced to simplify the analysis. Essentially the downstream dc/dc converter is modeled as a constant power sink which is cascaded with the PFC boost stage. Using this model, we have applied the double-averaging approach to derive the closed-form loop gain of the line frequency component. This simple procedure succeeds in capturing the stability information in terms of a closed-form stability condition, which can be visualized graphically in terms of design-oriented stability boundaries. Stable regions and unstable regions are identified and comparison is made between the resistor terminated model and the proposed model. Our results show that the two-stage PFC power supply has a more restricted stability region and is more prone to line-frequency instability. Furthermore, the resistor terminated PFC converter can be easily “stabilized” by increasing its power consumption, whereas the stability of the two-stage PFC power supply is independent of the output power. The graphical stability boundaries have been verified by experimental measurements. As an application, the derived stability criterion can be used to generate design guidelines for stable operation along with possible design tradeoffs. At the end, different synchronization schemes between the PFC pre-regulator and the downstream converter, as well as the possible effects on the line-frequency stability, are discussed to provide some extra information.

Chapter 4 Line-Frequency Instability with Constant Current Sink Termination 4.1 Introduction In Chapter 3, we have analyzed the phenomenon of line frequency instability associated with the two-stage PFC power supply. In this chapter, we will extend our studies to the PFC converter terminated with constant current sink. This study is motivated by the frequent use of constant current sink termination in practical design and testing processes. For example, most power supplies’ specifications define loading condition by constant current sink, such as the stepped load condition for testing transient response of the output voltage. The stability criterion of the constant-current-sink terminated system will be derived and compared with that of the constant-power-sink terminated system. The objective of this study is to show the inconsistency in the stability information provided by the constant-current-sink terminated model and the actual two-stage PFC power supply. The simplified schematic of the PFC converter terminated with constant current sink is shown in Fig. 4.1.

81

82

4. Line-Frequency Instability with Constant Current Sink Termination

4.2 Derivation of Stability Criterion Under the constant current sink termination, the averaged model of the power stage can be represented by diin (t) ; dt dvPFC (t) + Io , (1 − d)iin (t) = C dt

(1 − d)vPFC (t) = vi (t) − L

(4.1) (4.2)

where Io is the dc current drawn by the constant current sink. After combining (4.1) and (4.2) and eliminating d, we get L diin (t)2 C dvPFC (t)2 = −vo (t)Io + iin (t)vi (t) − . 2 dt 2 dt

(4.3)

Using the same assumption about the energy storage of the inductor as in the previous section, (4.3) can be simplified as C dvPFC (t)2 ≈ −vPFC (t)Io + 2p(t) sin2 ωm t 2 dt = −vPFC (t)Io + p(t)(1 − cos 2ωm t)

(4.4) (4.5)

Following similar procedure as in the case of constant power sink termination and adopting the same set of notations defined in the previous chapter, the three equations L

vPFC

D

iPFC vi

C

S

Io iL

current amplifier compensator iref p Lowpass 1 / x2

GF τ F s +1 VPFC, ref

Figure 4.1: Circuit schematic of a boost PFC stage terminated by a constant current sink.


83

corresponding to the dc component, the fundamental frequency component and the second harmonic component are represented as follows: ¢ C d ¡ 2 x0 + 2x21r + 2x21i + 2x22r + 2x22i + xo Io = yo − y2r 2 dt

(4.6)

C d [x0 x1 + x1r x2r + x1i x2i + j(x1r x2i − x1i x2r )] + x1 Io 2 dt jωm C y1 (y1 )∗ [x0 x1 + x1r x2r + x1i x2i + j(x1r x2i − x1i x2r )] = − (4.7) + 2 2 4 ¢ ¡ ¢ C d ¡ y0 2x0 x2 + x21 + jωm C 2x0 x2 + x21 + x2 Io = y2 − . (4.8) 2 dt 2 In the steady state, (4.7) can be simplified as jωm C [xo x1 + x1r x2r + x1i x2i + j (x1r x2i − x1i x2r )] + Io (x1r + jx1i ) = y1 −

(y1 )∗ . 2 (4.9)

By equating the coefficients of the real parts and imaginary parts of (4.9), we get · ¸ 3Cωm y1i (−xo + x2r ) − y1r (Io + Cωm x2i ) x1r = − (4.10) 2 (−x2 + x2 + x2 ) 2Io2 + 2C 2 ωm 2r o 2i ¸ · 3y1i (−Io + Cωm x2i ) + Cωm y1r (xo + x2r ) . (4.11) x1i = − 2 (−x2 + x2 + x2 ) 2Io2 + 2C 2 ωm 2r o 2i Equations (4.10) and (4.11) can be re-arranged into the following matrix form: " # x1r −1 = 2 2 2 2Io + 2C ωm (−x22i + x2o + x22r ) x1i " #" # 0 −Io − Cωm x2i 3Cωm (−xo + x2r ) y1r · 0 Cωm (xo + x2r ) 3(−Io + Cωm x2i ) y1i x1 = A · y10 ,

(4.12)

Similar to the derivation process in Chapter 3, y1 is denoted as y10 in order to distinguish the power signal from the one that propagates through the control loop. A is the transfer function of the boost power stage with constant current sink termination, and " # −Io − Cωm x2i 3Cωm (−xo + x2r ) −1 . A= 2 2 (−x2 + x2 + x2 ) 2Io + 2C 2 ωm Cωm (xo + x2r ) 3(−Io + Cωm x2i ) 2r o 2i (4.13) In a likewise manner, we denote the transfer function of the feedback circuit by B and y1 = B · x1 . Since the equations of the feedback control are unaffected by the changed load termination, we can directly apply the derived expression of B in the previous chapter, which gives

84


−1 B= 2 1 + τF2 ωm

"

GF

GF τF ωm

−GF τF ωm

GF

# .

(4.14)

Then, the round-trip signal transfer function M is given by M = B·A 1 = 2 2 2 (−x2 + x2 + x2 )] (1 + τF ωm ) [2Io2 + 2C 2 ωm 2r o 2i " # −Io − Cωm x2i 3Cωm (−xo + x2r ) · . Cωm (xo + x2r ) 3(−Io + Cωm x2i )

"

GF

GF τF ωm

−GF τF ωm

GF

#

(4.15)

By combining (4.6) and (4.8) with the feedback control equations derived in the previous chapter, i.e., (3.32) and (3.34), we arrive at the same simplifying step by which all the second harmonic components become zero with the assumption of xo = VPFC,ref . Thus, (4.15) becomes 1 M= 2 2 2 x2 ) 2(1 + τF ωm )(Io2 + C 2 ωm o

"

2 −GF (Io + CτF ωm xo ) −3GF ωm (Io τF + Cxo )

GF ωm (Io τF + Cxo )

2 3GF (−Io + CτF ωm xo ) (4.16)

# .

The two eigenvalues of M are λ1 =

3GF h i; p 2 (1 − 3τ 2 ω 2 ) − 8CI τ ω 2 x + C 2 ω 2 x2 (τ 2 ω 2 − 3) 2 x + 2 −2Io + 2CτF ωm I o o F m o o m o F m F m (4.17)

3GF i. λ2 = − h p 2 (1 − 3τ 2 ω 2 ) − 8CI τ ω 2 x + C 2 ω 2 x2 (τ 2 ω 2 − 3) 2 x + 2 2Io − 2CτF ωm I o o F m o o m o F m F m (4.18) The magnitude of the appropriate eigenvalue represents the magnitude of the overall loop gain |Ty1 |. By substituting the typical circuit parameters shown in Table 4.1, λ1 yields a value of around 0.488 and λ2 yields a value of around 1. Therefore, λ2 is the eigenvalue of interest and thus, 3GF i. |Ty1 | = − h p 2 (1 − 3τ 2 ω 2 ) − 8CI τ ω 2 x + C 2 ω 2 x2 (τ 2 ω 2 − 3) 2 x + 2 −2Io + 2CτF ωm I o o F m o o m o F m F m (4.19)

4.3 Stability Boundaries

85

Table 4.1: Circuit parameters used in simulation Parameters of PFC stage

Values

Rectified line voltage Vin,rms

70 Vrms, 50 Hz

PFC stage reference output voltage VPFC,ref

240 V

Switching frequency fsw1

100 kHz

Inductance L

1 mH


66 µF

Nominal voltage feedback gain GF

12 A

Nominal feedback time constant τF

8.6 ms

Nominal loading current Io

0.2 A

For stable operation, |Ty1 | > 1. Therefore, the stability criteria of the PFC boost converter terminated with constant current sink is given by h xo >

GF

q 2 − 2τF ωm + −3 + τF2 ωm

8Io (1 GF

+

2 ) τF2 ωm

−

4Io2 (1 G2F

+

2 )2 τF2 ωm

2 ) 2ωm C(1 + τF2 ωm

i . (4.20)

4.3 Stability Boundaries The stability criteria are visualized as stability boundaries plotted in various perspectives of the parameter space, which are shown in Fig. 4.2. Comparing the figures with Fig. 3.6 in the previous chapter, the boundaries have similar shapes as those of the twostage PFC power supply. The similarity reflects that the parameters and the way they affect the stability condition are similar, irrespective of the type of load termination. In general, the boost PFC converter becomes more stable with the following changes of parameters: 1. Increasing the output capacitor. 2. Reducing the dc gain of the voltage error amplifier’s compensation. 3. Increasing the time constant of the voltage error amplifier’s compensation, which is equivalent to moving the pole to a lower frequency.


86

However, a detailed comparison also reveals that the boundaries of the constantcurrent-sink terminated converter have slightly shifted downward. The resulting larger stable regions reflect that the constant-current-sink terminated system is more stable than the two-stage PFC power supply under the same output power.

450

450

400

400

STABLE 350

τF = 6.4 ms

350

C = 66 µF

VPFC [V]

VPFC [V]

STABLE

C = 56 µF

300

C = 83 µF 250

300

τF = 8.6 ms

250

τF = 10.8 ms

200

200

UNSTABLE

UNSTABLE

150

150

100

100 9

10

11

12

13

14

15

50

16

60

70

80

GF [A]

90

100

110

120

C [µF]

(a)

(b)

450

280

400

260

STABLE

300

GF = 12 A

250

Io = 0.2 A

240 VPFC [V]

VPFC [V]

STABLE

GF = 14 A

350

GF = 10 A

200

Io = 0.4 A

220

Io = 0.6 A

200 180

UNSTABLE UNSTABLE

150

160

100

140 6

7

8

9 τF [ms]

(c)

10

11

12

6

7

8

9

10 τF [ms]

11

12

13

14

(d)

Figure 4.2: Stability boundaries of the constant-current-sink terminated model plotted in various parameter planes. (a) GF –VPFC plane with τF = 8.6 ms; (b) C–VPFC plane with GF = 12 A; (c), (d) τF –VPFC plane with C = 66 µF. For (a), (b) and (c), Io = 0.2 A.

4.3 Stability Boundaries

87

Next, the stability boundaries of the constant-current-sink terminated system are compared with those of the constant-power-sink terminated system over a range of output power. The boundaries are plotted in Fig. 4.3 with y-axis begin the output voltage and x-axis being the equivalent loading current. The results once again show that the converter with current sink termination results in larger stable region. Moreover, the current sink terminated system can be easily stabilized by increasing the loading current. The results suggest that the use of constant current sink termination in the testing process may be over-optimistic.

320

STABLE

280

Constant current sink terminated Constant power sink terminated

GF = 14 A

300

C = 58 µF

280

240 GF = 12 A

240 220

C = 68 µF

220

VPFC [V]

260

VPFC [V]


STABLE 260

GF = 10 A

200 C = 82 µF

180

200

160

180

UNSTABLE

UNSTABLE

140

160 140

120 0

0.1

0.2

0.3

0.4

0.5

0.6

0.7

0.8

0

0.1

Equivalent loading current Io [A]

0.2

0.3

0.4

0.5

0.6

0.7

0.8


(a)

(b) 260


STABLE 240 τF = 8 ms

VPFC [V]

220 200

τF = 10 ms

180

τF = 12 ms

160

UNSTABLE

140 120 0

0.1

0.2

0.3

0.4

0.5

0.6

0.7

0.8


(c)

Figure 4.3: Stability boundaries of the constant-current-sink terminated model and the constant-power-sink terminated model. (a) C = 66 µF, τF = 8.6 ms; (b) GF = 12 A, τF = 8.6 ms; (c) GF = 12 A, C = 66 µF.


88

4.4 Simulation Results The stability boundaries derived in Section 4.3 are verified by simulation using WinSpice. The averaged model of the PFC converter terminated with constant current sink is constructed. The converter model is simulated under various parameter changes and the stability boundaries are recorded. The simulation results are plotted along with the analytical results to facilitate comparison. Fig. 4.4 shows the stability boundaries plotted in output voltage against various parameters. The simulation results match with the analytical results.

360

340 340

320

STABLE 320

C = 55.35 µF

280 VPFC [V]

300

VPFC [V]

STABLE

300

280

C = 66 µF

260

260

τF = 6.4 ms

240

τF = 8.6 ms

220

240

UNSTABLE

180

Analytical results Simulation data

200 10

11

12

13


160

180 9

UNSTABLE

200

220

14

50

15

55

60

65

GF [A]

70

75

80

85

90

13

14

C [µF]

(a)

(b) 280

340

STABLE

320

STABLE

300 280 260 240 220

GF = 12 A

200

UNSTABLE

Io = 0.2 A

240

GF = 14 A

VPFC [V]

VPFC [V]

260

Io = 0.4 A

220

UNSTABLE

200

180

180


160


160 6

7

8

9

10 τF [ms]

11

12

13

(c)

14

6

7

8

9

10 τF [ms]

11

12

(d)

Figure 4.4: Simulation results of stability boundaries between the constant-currentsink terminated model and the complete two-stage system. (a) GF –VPFC plane with τF = 8.6 ms; (b) C–VPFC plane with GF = 12 A; (c), (d) τF –VPFC plane with C = 66 µF. For (a), (b) and (c), Io = 0.2 A.


89

Then, the converter is simulated over a range of loading current with different combinations of parameters. The resulting stability boundaries are plotted in Fig. 4.5 and compared with those of the constant-power-sink terminated model. Moreover, both sets of simulation data are plotted along with the analytical results to verify the theoretical analysis. From the figures, the simulation results match well with the analytical results. The results verified that the converter with constant current sink termination has a larger stable region and can be easily stabilized by increasing the loading current.

300


STABLE

280

STABLE

340

Forward converter terminated 320

260

VPFC [V]

VPFC [V]

300 240 220

Constant current sink terminated

280 Constant current sink terminated

260 200

UNSTABLE

240

UNSTABLE Analytical results Simulation data

180


220

160

200 0

0.1

0.2

0.3

0.4

0.5

0.6

0.7

0.8

0

0.1


0.2

0.3

0.4

0.5

0.6

0.7

0.8


(a)

(b) 300

STABLE

280

Forward converter terminated

260

VPFC [V]

240 220 Constant current sink terminated

200 180

UNSTABLE


160 140 0

0.1

0.2

0.3

0.4

0.5

0.6

0.7

0.8


(c)

Figure 4.5: Simulation results of stability boundaries of the constant-current-sink terminated model and the constant-power-sink terminated model. (a) C = 66 µF, τF = 8.6 ms; (b) GF = 12 A, τF = 8.6 ms; (c) GF = 12 A, C = 66 µF.

90


4.5 Further Comparison A further comparison of stability boundaries is made here with the PFC converter terminated with resistive load [96]. For ease of comparison, the stability criterion of the three converters are re-stated as follows. For PFC converter with constant power sink termination, ³ ´ p 2 GF 2τF ωm + −3 + τF2 ωm xo > . 2 ) 2ωm C(1 + τF2 ωm For PFC converter with constant current sink termination, h q 2 − 8Io (1 + τ 2 ω 2 ) − GF 2τF ωm + −3 + τF2 ωm F m GF xo > 2 2 2ωm C(1 + τF ωm )

(4.21)

4Io2 (1 G2F

2 )2 + τF2 ωm

i . (4.22)

For PFC converter with resistive load termination, q i h 1 2 2 2 2 2 2 2 2 2 GF R ωm CRτF − 2 + 1 − 4ωm CRτF − 3ωm τF + 4 ωm C R (ωm τF − 3) xo > . 2 C 2 R2 )(1 + ω 2 τ 2 ) (4 + ωm m F (4.23) The stability boundaries of the three systems are plotted in Fig. 4.6 over a range of equivalent output power. Through comparing the boundaries, we can conclude that the use of constant power sink termination results in the smallest stable region, under which the PFC converter is mostly prone to oscillation and cannot be stabilized by increasing the output power. In contrast, the use of resistive termination results in the largest stable region, under which the converter can be easily stabilized by a relatively small increase in the output power. Also, the boundary resulting from the constant current sink termination lies mid-way between the other two systems, indicating that the constant-current-sink terminated system is more stable than the constant-power-sink terminated system, but is more prone to oscillation than the resistive-load terminated system. Further, the converter can be stabilized by relatively large increase in the output power. The results show that comparing to the resistive load terminated system, the stability information given by the constant-current-sink terminated system is closer to that of the actual two-stage PFC power supply.

4.5 Further Comparison

91

300

Output voltage [V]

280

STABLE (a)

260

(b) 240

(c) 220

UNSTABLE 200

180 20

40

60 80 Output power [W]

100

120

Figure 4.6: Comparison of stability boundaries among converters with different types of load terminations: (a) constant power sink termination; (b) constant current sink termination; (c) pure resistive load. C = 66 µF, τF = 8.6 ms; GF = 12 A. On the other hand, a detailed comparison either between the boundaries (a) and (b) in Fig. 4.6 or between the inequalities (4.21) and (4.22) reveals that the stability criterion of the constant-current-sink terminated converter converges to that of the constant-power-sink terminated system with Io → 0. This observation suggests that the use of smaller loading current gives a model which is closer to the actual two-stage system. However, the condition of zero load current is impractical because the PFC converter cannot operate properly without any loading current. Even though the converter can work properly under a very small loading current, cautions should be taken in choosing the minimum value of load current, because large error may incur due to the possible occurrence of DCM under the light load condition, which violates the basic assumption of our theoretical derivation.

92


4.6 Conclusion In this chapter, the line frequency instability in the boost PFC converter terminated with constant current sink is examined. Based on the similar approach used in the previous chapter, the closed-form loop gain of the line frequency component has been derived and the stability condition has been visualized graphically in terms of design-oriented stability boundaries. Stable regions and unstable regions are identified and comparisons are made between the constant-current-sink terminated system and the two-stage PFC power supply. The results show that the constant-current-sink terminated system has a larger stable region than the constant-power-sink terminated converter. Also, the constant-current-sink terminated system can be “stabilized” by increasing its power consumption. The stability boundaries have been verified by simulation. In summary, if the resistive-load terminated converter is also included for comparison, the constant-power-sink terminated converter gives the most consistent stability results when compared with the actual two-stage PFC power supply. Both the constantcurrent-sink terminated converter and the resistive-load terminated converter give overoptimistic results on the system stability. But the results given by the constant-currentsink terminated system are generally closer to those given by the two-stage system, and the difference between the two systems reduces with smaller loading current. Based on these results, engineers may need to rethink the type of load termination to be used for design and testing for ensuring the consistency of converter performance between testing and practical operation.

Chapter 5 The Feedback Linearization Approach for the Derivation of Robust Current Loop Control 5.1 Introduction In general, the design of the control system focuses on the specifications of stability and system performance. In Chapters 3 and 4, we have covered the stability analysis of the two-stage boost PFC power supply and the boost PFC pre-regulator with different kinds of load terminations. In this chapter, we move forward to a control design methodology that aims at performance improvement. In this chapter and Chapter 6, we introduce a generalized approach for the generation of robust control rules for the boost PFC converter based on feedback linearization. In Chapter 2, we have shown that a typical PFC control is in a multi-loop structure, where the outer voltage loop is connected to the inner current loop through a multiplier function, as depicted in Fig. 5.1. The approach to be introduced is a unified approach that can be applied to both the inner current loop and the outer voltage loop. However, as an application-based introduction, we limit ourselves to the basic idea of feedback linearization and the discussion of the current loop control in this chapter, as highlighted in Fig. 5.1. The technique will be extended to the voltage loop in Chapter 6.

93

94

5. The Feedback Linearization Approach for Current Loop Control

vo vi

i

L

L vgs

current loop control

D

i

D

C

SW

i

|sin t|

ref

I

multiplier

ref

R

voltage loop control

Figure 5.1: Boost PFC converter with the control based on the multi-loop control structure. The inner current loop is highlighted to indicate the use of the proposed derivation approach.

5.1.1 Control objectives of PFC converters The usual form of a PFC pre-regulator is a boost converter [120] controlled by a fast control loop, also known as inner current loop, such that the input current follows the same sinusoidal waveform as the input voltage [8]. The PFC pre-regulator is often terminated with a storage capacitor which interfaces with a downstream converter to provide a tightly regulated output voltage to the eventual load. The PFC pre-regulator is thus required to maintain a regulated averaged output voltage across its terminating storage capacitor. Therefore, the objectives of the control circuit for the PFC preregulator are two-fold. First, a near unity power factor should be maintained at the input side via an inner current loop. Second, a constant average voltage should be maintained across the output storage capacitor via an output regulation loop. The first objective means that the input current should be sinusoidal and in phase with the supply voltage, resulting in a squared sinusoidal power input function, as shown in Fig. 5.2, where vi is the rectified line voltage, iref is the reference current, pi is the input power and vo is the output voltage. Clearly, output voltage ripple is inevitable for power balance since the input power is a squared sinusoidal function, and the size of the storage capacitor can be chosen to keep the ripple magnitude to a reasonable level. In practice, the storage capacitor also affects the dynamical response of the output regulation loop, and as a compromise, the output voltage would be regulated at every rectified line cycle. This indicates that the line frequency is the maximum bandwidth allowed in the output regulation loop under the condition of unity power factor [118].

5.1 Introduction

95

v

i

V i

i

t

ref

t

ref

I p

i

P

t

i

v

o

V T

ref

t

(a line period)

Figure 5.2: Ideal waveforms of the boost PFC converter.

5.1.2 Decoupling of the dynamics In order to program the input current to follow the sinusoidal envelope, the input current has to be controlled cycle-by-cycle at the switching frequency. In contrast, the output voltage has to be controlled at a much slower rate due to the reasons mentioned in the previous subsection, so that the reference current is not contaminated by the line frequency ripple in the output voltage. Thus, the bandwidth required by the current control is usually more than a decade higher than that of the voltage control, and they operate in totally different range of time scale, as illustrated in Fig. 5.3. The multi-loop control structure exploits this separation of time scale in the two control loops [65], [73], with the inner-loop being the fast current loop and the outer-loop being the slow voltage loop. Such a wide separation of time scale decouples the dynamics of the inner current loop from that of the outer voltage loop. Based on this concept, the modeling and analysis of the PFC converter can be greatly simplified in the way that when the current loop is analyzed in the time scale of switching frequency, the slow varying output voltage and the output of voltage loop control can be approximated by constants. Likewise, during the analysis of the voltage loop in the time scale of line frequency, ideal current tracking can be assumed.

96


Voltage loop

Current loop

Low frequency model

Averaged model frequency f

dc

(line frequency)

fSW/2

(half switching frequency)

Figure 5.3: Separation of time scale and the modeling approach for the current loop and the voltage loop.

5.1.3 Problems addressed by the derivation approach As regards the inner current loop control, we have reviewed some improvement schemes in the literature in Chapter 1. Most of these improvement schemes are specifically developed to tackle particular undesirable phenomena. Specifically, in the feedforward control schemes, a generalized and systematic derivation procedure is still missing. Moreover, the resulting closed-loop systems become too complex for analysis and formal study of their large-signal behaviors. This necessitates the use of trial-and-error procedures in the design of the control parameters, with the design constraints and the optimal design solution remained unknown. Instead of focusing on particular phenomena in the current loop, we attempt to reduce the current loop’s error dynamics to a simple linear form based on the method of feedback linearization [121]. This approach turns out to be effective in eliminating all the undesirable phenomena incurred by the nonlinearity and the dependency of the current loop dynamics on the input disturbance such as line frequency and input voltage, and thus results in improved current tracking performance and robustness under variations of operating condition. Another issue addressed by this approach is the choice of the control parameters. Based on the feedback linearizaton approach, the error’s dynamical equations give clear pictures of the closed-loop behaviors of the inner current loop, and offer insights into the design of the control parameters. Due to the linear nature of the resulting error dynamics, effective tools from linear control can be fully utilized to analyze the steady-state frequency response and the transient response. The control parameters can be selected according to the frequency response plots of the loop gain to ensure system stability and satisfactory current tracking performance. The performance of the resulting control rules will be evaluated by experiments.

5.2 Feedback Linearizatoin

97

5.2

Feedback Linearizatoin

5.2.1

Basic idea of feedback linearization

Feedback linearization is a generalized approach introduced for designing effective controllers for nonlinear systems [47], [122]. It is also known as the “exact linearization via feedback” [121]. In the context of nonlinear control theory, this method is readily applied to the class of nonlinear systems that can be represented in companion form, or controllability canonical form. The main idea is to transform a nonlinear system into an equivalent linear system via the combined use of feedback signals, so that well-established linear control techniques can be applied. It is completely different from the conventional (Jacobian) linearization in that the feedback linearization is achieved by state transformation and feedback, rather than by linear approximation of the dynamics. Besides removing the nonlinearities of the system dynamics, the method of feedback linearization allows the desired dynamics or behaviors to be imposed on the closed-loop system. Again, we have to emphasize that feedback linearization differs from the usual linearization as normally applied in electrical engineering analyses, in that feedback linearization does not employ a small-signal perturbation process to generate a smallsignal linear model. In the context of nonlinear control theory, feedback linearization is conceived as a nonlinear compensation method which combines with the plant to result in an overall linearized system. To introduce the idea of feedback linearization mathematically, let us consider a class of nonlinear system in the form of x˙ = f (x) + g(x)u

(5.1)

where u is the scalar control input; x is the state vector with n components, given by x = [x1 , x2 , ..., xn ]T , and xi is the state variables with i = 1, 2, ..., n; f , g are infinitely differentiable functions of x. This class of system is unique in the way that no derivative of the input u is present. If the system in (5.1) can be represented in the companion form, also known

98


as the controllability canonical form as follows    x˙ 1 x2     x˙ 2   x3        ...  =  ...     x˙   xn  n−1   x˙ n f (x) + g(x)u

     ,   

(5.2)

the nonlinear system dynamics can be written as (n)

x1 = f (x) + g(x)u

(5.3)

where x(n) represents the nth derivatives of x with respect to time. The nonlinearity of (5.3) can be eliminated if the control input u is chosen to be u = g(x)−1 (v − f (x))

(5.4)

with v being an “equivalent input” to be specified. By substituting (5.4) into (5.3), the dynamics of the closed-loop system is reduced to a simple form (n)

x1 = v.

(5.5)

The dynamics in (5.5) is linear if v is a linear function of x. In typical, v is chosen to be the linear feedback control of x given by v = −k0 x1 − k1 x2 − ... − kn−1 xn−1 = Kx

(5.6)

Control parameters K = [k0 , k1 , ..., kn−1 ] are selected such that K is Hurwitz [122], which is equivalent to have the following characteristic equation sn + kn−1 sn−1 + ... + sk1 + k0 = 0

(5.7)

with all its roots located in the left-half plane. Satisfying this condition ensures that the closed-loop system (5.5) is exponentially stable, which can be written as (n)

(n−1)

x1 + kn−1 x1

(1)

+ ... + k1 x1 + k0 x1 = 0

(5.8)

Stability of the system in (5.8) also means x1 → 0. If x1 represents a tracking error, it leads to exponentially convergent tracking.

5.2 Feedback Linearizatoin

99

Finally, the control rule required to linearize the nonlinear system is u = g(x)−1 (Kx − f (x))

(5.9)

Although the above discussion has only introduced the basic concepts of feedback linearization, it already suffices for the applications of controlling the power converters. More advanced topics like input-output linearization, internal dynamics and zero-dynamics are not covered here as they are beyond the scope of our studies. Interested readers can refer to [121], [47], [122] for details.

5.2.2 Applications of feedback linearization in the control of power converters The use of feedback linearization has solved many practical control problems such as the control of industrial robots, biomedical devices and high performance aircrafts. It has also been successfully applied to the control of power converters and results in improved performance in terms of steady-state error and transient response. A number of its applications in the control of ac-dc converters have been reported in the literature. The application of feedback linearization in ac-dc converters was first reported by Rioual et al. in 1994 [123]. They derived a nonlinear control for three phase PWM rectifiers using the method of feedback linearization. However, the characteristics and the benefits of the derivation method were not been specified. Later, the merits and usefulness of this application were recognized by Lee et al. [124] in his work of developing a fast voltage control strategy for three-phase PWM rectifiers. Another feedback linearization-based control using the d-q synchronous reference frame was introduced by Lee [125] in 2003. Recently, Matas [126] has reported the combined use of feedback linearization and sliding mode control to control a shunt active power filter.

5.2.3 Advantages of feedback linearization The advantages offered by the application of feedback linearization can be summarized as follows. 1. By transforming the nonlinear system into an equivalently linear system, analysis of the closed-loop system’s behaviors and dynamics is greatly simplified and

100


powerful tools of linear control can be utilized to study the system effectively. 2. The linearized dynamics equations give full pictures of the behaviors of the closed-loop system and offer insights into the design of control parameters. 3. Desired dynamics and behaviors can be imposed to the closed-loop system by the initial choices of the state variables and the equivalent input in the form of feedback control. 4. The linearity of the closed-loop dynamics results in traceable system behaviors and consistent performance despite the presence of input disturbances.

5.2.4 Limitations of feedback linearization However, there are also shortcomings and limitations associated with the approach, which are stated as follows [47]. 1. The result is not global and is only valid in a large region of the state space. For example, the control law is not well defined when the zeroing of the feedback state variable leads to a division-by-zero in u. 2. In general, the approach relies on an established system model for the derivation of the control rule. This in turn implies that uncertainties in the model, such as the fluctuation of system parameters and the presence of parasitic components, will lead to error in the control input and consequently the system output. 3. Full state measurement is necessary in implementing the control law. This complicates the implementation because some state inputs, such as the derivatives of the certain state variable, may neither be physically meaningful nor be accessed easily by direct measurement. Despite the above limitations, the usefulness and the advantages of the feedback linearization method in the control of power converters have been recognized in the research literature. Moreover, in these applications, feedback linearization is only applied as a general concept to aid the generation of the control rule. The exact formulation of the resulting control rule varies and depends on the initial choice of state

5.3 Derivation of the Current Loop Control

101

variables and the dynamics imposed to the closed-loop system. In our studies, feedback linearization is applied separately to the inner loop and the outer loop of the boost PFC converter for generating individual control solutions. The generation and design of the current loop control will be discussed in the following sections.

5.3

Derivation of the Current Loop Control

This section demonstrates the derivation of the inner-loop current control rule using the method of feedback linearization. Considering that the current loop control operates in the time scale of switching frequency, we adopt the general averaging over the duty cycle, which provides a simple yet effective model to capture the essential behaviors of the fast current loop dynamics. The averaged model of the inductor current is represented by 1 diL ¯ o ), = (vi − dv dt L

(5.10)

where d¯ = 1 − d with d being the continuous duty cycle. The objective of the control is to track the inductor current along the reference current iref generated by the outer loop. Here we denote the current error by ei where ei = iref − iL .

(5.11) v

o

L v

D

SW

i

C

R

v

gs

i

L

i

L

(

PI

L K i1 + K i 2 ∫ dt i

ref

L

v

)

i

PWM

d dt

1 vo

d

v

o

inner-loop current control

Figure 5.4: Boost PFC converter with the derived inner-loop current control rule.

102


The dynamics of the current error is diref diL diref 1 vo ¯ dei = − = − vi + d. dt dt dt dt L L

(5.12)

Here d¯ is the input of the current error dynamics. In a closed loop system, d¯ is generated by the control circuit using the feedback signals. Based on the method of feedback linearization, the dynamics can be made linear if d¯ is configured as 1 diref diref vi L + ) = (Lvia − L + vi ) d¯ = (via − dt L vo dt vo

(5.13)

with via being an equivalent input. Hence, the resulting error dynamics becomes dei = via . dt

(5.14)

Clearly, a desired dynamical behavior can be imposed to the current error by the choice of via . Here, via can be chosen to be the linear PI function of the current error in order to minimize the steady-state error [127], i.e., Z via = −Ki1 ei − Ki2

ei dt

(5.15)

with Ki1 > 0 and Ki2 > 0. By substituting (5.15) into (5.14), the current error dynamics becomes Z dei + Ki1 ei + Ki2 ei dt = 0. dt

(5.16)

With Ki1 and Ki2 being positive, the current error converges to zero exponentially. By combining (5.15) and (5.13), the general current control is given by · µ ¶¸ Z diref 1 ¯ vi − L − L Ki1 ei + Ki2 ei dt , d= vo dt

(5.17)

which is illustrated in Fig. 5.4. The resulting current control (5.17) can be implemented as an individual current control circuit. Alternatively, it can be applied to the standard PFC controller by adding input voltage feedforward and the corresponding functional circuitries (e.g. summation, inversion) to the controller circuit, resulting in a control rule that covers the functions of the feedforward control schemes proposed previously [65], [66]. Based on the proposed derivation, the properties of the resulting control rule will be further explored in the following sections.

5.4 Frequency Response Analysis

5.4

103

Frequency Response Analysis

In this section, the frequency response of the current error dynamics is investigated. Under the derived current control rule, equation (5.16) gives a complete picture of the steady-state behavior of the closed-loop system, which can be written as Z diref diL = + Ki1 (iref − iL ) + Ki2 (iref − iL )dt. dt dt

(5.18)

Due to the linear nature, (5.18) can be expressed in the s-domain as ¶ µ 1 . siL = siref + (iref − iL ) Ki1 + Ki2 s

(5.19)

The block diagram of (5.19) is depicted in Fig. 5.5 (a), which can be manipulated into a general form as shown in Fig. 5.5 (b). Upon inspection of Fig. 5.5 (b), the round-trip loop gain is

³ Ki2 1 +

sKi1 Ki2

´

. (5.20) s2 The frequency response is determined by (5.20), which contains a double-pole at the Gi =

origin and a mid-frequency zero determined by Ki1 and Ki2 . Equation (5.20) also indicates that the ideal loop gain is independent of the operating condition, leading to robust steady-state performance. To account for the non-ideality in practical converters, an improved transfer function G0 can be formulated by ´ ³ Ki1 Ki2 1 + s K i2 · Hi , G0i = 2 s 1 s

s

i

K i1 + K i 2

i

L

i

ref

1 s

(5.21)

 s + 

K i1 + K i 2

K i1 + K i 2

(a)

i

L

1 s

s + K i1 + K i 2

ref

11  ss

1 s

(b)

Figure 5.5: (a) Block diagram of the current error dynamics under the derived current control rule; (b) block diagram in general form.

104


where Hi is a transfer function to account for the effects of the parasitic components, the additional low-pass filters and the propagation delay of the control signals on the loop gain, i.e., ³ ´ s sL 1 − ωd sLe Hi = ³ ´³ ´³ ´2 ≈ ³ ´³ ´³ ´2 ³ ´. s s s s s s s 1 + ωd r 1 + ωp1 r 1 + ωp1 1 + ωp2 1 + ωp3 1 + ωp2 1 + ωp3 ´ ³ ´ (5.22) ³ −sTd

In (5.22), the delay function e−sTd is approximated by 1 − 1st order Padé approximation with ωd =

2 Td

s ωd

/ 1+

s ωd

using the

and Td being the propagation delay. Vari-

able ωp1 is the pole created by the resistance in series with the inductor, ωp1 =

r L

and

r = rL + Rs + do rdson + (1 − do )rf on , with rL being the parasitic resistance of the inductor, Rs being the sensing resistor, rdson and rf on being the on-time resistance of the MOSFET and the diode respectively. Also, do is the nominal duty cycle, ωp2 and ωp3 are the poles of the additional low-pass filters. Based on (5.21), frequency response of the current loop gain can be computed. Fig. 5.6 shows the computed frequency responses with different combinations of Ki1 and Ki2 . Other parameters are constant and measured from the experimental circuit (see Fig. 5.7) with the following values: ωp1 = 1081 rads−1 , ωp2 = 396000 rads−1 , ωp3 = 106 rads−1 and Td = 1 µs. In Fig. 5.6(a), under a fixed Ki2 , as Ki1 increases, the crossover frequency is slightly increased, and the phase margin is increased by a larger amount. In Fig. 5.6(b), under a fixed Ki1 , as Ki2 increases, the crossover frequency is slightly decreased, and the phase margin is decreased by a larger amount. Hence, Ki1 and Ki2 can be selected according to the desired crossover frequency and phase margin to ensure current loop stability and a satisfactory current tracking performance.


105

100

K

Gain [dB]

80

= 4 x 109

i2

60

K

40

= 12 x 104 K = 6 x 104

i1

20

i1

K

0

= 3 x 104

i1

-20 1 10

2

10

3

10 Frequency [Hz]

10

4

10

5

Phase [deg]

-100

K = 12 x 104 K = 6 x 104 i1

-120

i1

K

-140

= 3 x 104

i1

-160 -180 1 10

2

10

3

10 Frequency [Hz]

10

4

10

5

(a) 100

K

Gain [dB]

60 40 20 0 -20 1 10

= 6 x 104

i1

80

K

= 8 x 109

i2

K

= 4 x 109 K = 2 x 109

i2

i2

10

2

3

10 Frequency [Hz]

10

4

5

10

Phase [deg]

-100

K K K

= 2 x 109

i2

-120

= 4 x 109

i2

-140

= 8 x 109

i2

-160 -180 1 10

10

2

3

10 Frequency [Hz]

10

4

5

10

(b)

Figure 5.6: Computed frequency responses of G0i with various combinations of control parameters: (a) Ki1 is varying with Ki2 fixed at 4 × 109 ; (b) Ki2 is varying with Ki1 fixed at 6 × 104 .


106

5.5 Practical Implementation A laboratory prototype of the boost PFC converter and the derived current loop control circuit are constructed using analog devices. A simplified schematic of the hardware prototype is shown in Fig. 5.7 and the key circuit parameters are shown in Table 5.1. The implementation of the current control rule can be simplified by employing the PWM modulator gain as the dividing function [128]. This can be done by using a ramp with its amplitude proportional to the output voltage. The amplitude is denoted by β3 vo and β3 = 0.01852 in our experimental circuit. Then, considering that the voltage across the sensing resistor Rs is the input, the control voltage feeding into the modulator is a modified version of (5.17) without the dividing function, i.e., · µ ¶¸ Z β3 Rs vi − Lv˙ iref − L Ki1 (viref − Rs iL ) + Ki2 (viref − Rs iL )dt , vic = Rs (5.23) where viref is the reference current profile generated by the multiplier circuit. With the adoption of the derived current loop control rule, stability specifications, such as the phase margin, and desirable performance specifications, such as the input current harmonic distortion, can be achieved by the selection of Ki1 and Ki2 using (5.21)–(5.22). The control parameters Ki1 and Ki2 are associated with the component values by

Rs Riz Rs ; Kv2 = , (5.24) Ril Lβ3 Ril Ciz Lβ3 where Ril , Riz , Ciz are the main components in the compensation network of the curKi1 =

rent amplifier (Fig. 5.7). For comparison purposes, another control circuit implementing the conventional ACM control using UCC3817 is constructed. The control circuit is applied to the same boost power stage in Fig. 5.7. The design of the compensation parameters in the current amplifier follows the conventional design approach [129] with the current loop crossover frequency being 1/10 of the switching frequency at around 10 kHz and a 30◦ phase margin. The simplified schematic is shown in Fig. 5.8. In both systems, same voltage loop control circuit using UCC3817 is adopted. the voltage loop crossover frequency is 1/10 of the nominal line frequency at around 50 Hz to ensure low distortion in the input current. It is worthy to mention that although the compensation of the current amplifier in

5.5 Practical Implementation

107

the ACM control can also be optimized using Bode plots with some sort of stability and performance trade-offs, it will be shown clearly that the derived current loop control outperforms the ACM control under similar stability specifications in the next section.


108

18V 14 13 43 12 7D11 V A10 V 9 8 -18V vi 510 k 1 2vi 0 k 1 V 2 2 LM318 3 4 2M 5 6 7 Multiplier circuit ff

1 2 3 4 5 6 7

500 Hz 110 Vrms 2

0.01 F

C

ip

V

ramp

2N 66 03

VNL2222

Vramp 20 0

10 k

1k 10 0 pF

2N 66 03

v

2 00

O

1N5819 10 k

510 k 10 k

LM318

iref

510 k 10 k

v

io

10 k

v

LM318 Current error amplifier 270 pF 10 k 100 100 nF LM318 v 1k Ref. current differentiator

iL

v

10 k

3vo

10 k

8 V 4.5 V

External Clock

vl

iref

50 k

1 n F

100 pF 10 k

iz

il

20

10 k

270 pF C

iz

16.65 0.9 nF R v k LM318 3.9 k

10 k

LM318 10 k 10 k

gs

Comparator and driver

R

10 k

v

da oL

Outer-loop voltage control circuit

iref

LM318

1 2.74 nF

s

R

R

100 F

SW

iL

18V 14 13 v 43 12 7 11 D A10 9 8 -18V

vo

D C

IRF840 0.25

v

10 k LM318

vgs

R

vic

APT15060B

L

ff

ff

MC34152

1 mH

vi

i

LM318

10 k

10 k

1k Input voltage buffer

Variable ramp generator

Derived inner current loop control

510 k 3vi 10 k

Figure 5.7: Simplified schematic of the boost PFC converter with the derived control rules implemented as individual control circuitries.

0.25

R

mo

R

1N 58 19

18V

10

3

8 3 0 k

ac

2 0 k

ref

v

i

ref

ip

6

R6

V

iz

C 270 pF

2

UCC3817

15

V

iz

5

4

1 0 k

1N5819 560 pF 1 0 0.82 nF k 4 16.5 k .7 F R C 1.8 k

s

3 .9 Rl k

3 .9 k

V

0 . 0 2 .2 1 F F

13 12 ff

1 1 .3 k

9 7 1 11

2 .7 n F

C

v p

1 5 0 1 k 0 k

4 7 C v n Fz 1 2 R 0v kz

v

O

Figure 5.8: Simplified schematic of the control circuit implementing conventional ACM control using UCC3817.

5.6 Experimental Results

5.6

109

Experimental Results

A series of experiments have been conducted to evaluate the performance of derived inner-loop current control. The selected control parameters are: Ki1 = 6 × 104 , Ki2 = 4 × 109 for yielding consistent crossover frequency and phase margin with the ACM control in the current loop gain. First, Bode plots of the current loop gain are measured under the nominal conditions with dc line voltage of 110 V. The results are plotted along with the analytical results in Fig. 5.9. The measured data generally match with the theoretical results. The accuracy of the loop gain transfer function is thus verified. The discrepancies can be attributed to the tolerance of the compensation components and the presence of parasitic components in the power converter, such as the output capacitance of the power MOSFET that has not been accounted for in our derivation. In addition, it is worthy to note that the obtained results correspond to the cases of an ac line just when the line angle is 45◦ , 135◦ , 225◦ and 315◦ , because only in these cases the diode current averaged in a switching period equals the load current, as it occurs when a dc line is used. Then, the derived control is compared with the conventional ACM control in current tracking performance. Under the derived control, the zero-crossing distortion in the input current is eliminated and high power factor is achieved even under the condition of high line frequency and low power. For illustration, Fig. 5.10 shows the current waveforms under the derived control for a line frequency of 800 Hz. Finally, the con-

Table 5.1: Circuit parameters used in the experiments Parameters of PFC stage

Values


110 V

Nominal line frequency f

500 Hz

Reference output voltage Vref

270 V

Switching frequency fsw

100 kHz

Inductance L

1 mH

Sensing resistor Rs

0.25 Ω


100 µF


1.2 kΩ

Scaling factor β3

0.01852

Compensation components Riz , Ciz , Cip

16.65 kΩ, 0.9 nF, 270 pF

110


100

Gain [dB]

Experimental Theoretical 50

0

−50 1 10

2

10

3

10 Frequency [Hz]

4

10

Experimental Theoretical

−100 Phase [deg]

5

10

−120 −140 −160 −180 1 10

2

10

3

10 Frequency [Hz]

4

10

5

10

Figure 5.9: Experimental and theoretical Bode plots of the current loop gain with Ki1 = 6 × 104 , Ki2 = 4 × 109 . verter is tested for input current distortion over a range of line frequency, input voltage and output loading. As a result, the current distortion is relatively low over a range of line frequency from 300 Hz to 800 Hz, input voltage from 80 Vrms to 140 Vrms and output power from 30 W to 120 W. For illustration, Fig. 5.11 shows the resulting waveforms in some selected operating conditions. The power factor is measured and plotted along with that using the ACM control in Fig. 5.12. The measured power factor resulting from the derived control is higher than that from the conventional ACM control in all tested conditions. It is rather consistent over the range of line frequency, as shown in Fig. 5.12(a). Over the range of input voltage and output power, although the measured power factor shows some deviations in Figs. 5.12(b) and (c), the overall derivation is smaller than that under the ACM control. The discrepancies are mainly attributed to the occurrence of discontinuous conduction mode (DCM). Since the control rule is derived based on the assumption of continuous conduction mode (CCM), the occurrence of DCM in extreme line and load conditions invalidates our derivation and incurs control errors. The above results confirm that the derived current control is ca-

5.7 Conclusion

111

Input voltage

Inductor current

Input voltage

vi

iL

(a)

Inductor current

vi

iL

(b)

Figure 5.10: Experimental waveforms resulting from (a) the conventional ACM control and (b) the proposed general current control at f = 800 Hz. Inductor current: [0.5 A/div]; input voltage [100 V/div]. pable of maintaining a relatively high power factor with various operating conditions, and the robustness of the control performance is verified.

5.7 Conclusion In this chapter, we have introduced the method of feedback linearization for the derivation of robust control solutions. Based on this method, a nonlinear current loop control for the boost PFC converter has been derived. Essentially, the derivation approach eliminates the nonlinearity and the dependency of the error dynamics on the input disturbance via the combined use of feedback signals. The resulting nonlinear control rule improves the current loop’s tracking performance with the zero-crossing distortion eliminated and high power factor maintained under all practical conditions, which are the direct results of the linearization of the current loop dynamics. The derived current control rule is readily implemented using analog devices. The control parameters can be designed according to frequency response analysis to ensure current loop stability and satisfactory current tracking performance. The accuracy of our modeling and analysis have been verified by experiments. Moreover, the experimental results have confirmed that the derived current control is capable of achieving low input current distortion and maintaining satisfactory control performance with the variations in line frequency, line voltage and loading conditions.

112


Input voltage

Inductor current

Input voltage

vi

Inductor current

iL

(a)

iL

(b)

Input voltage

Input voltage

vi

Inductor current

iL

(c)

vi

Inductor current

iL

(d)

Input voltage

vi

Inductor current

(e)

vi

Input voltage

iL

vi

Inductor current

iL

(f)

Figure 5.11: Experimental waveforms of inductor current and input voltage under various operating conditions: line frequency of (a) 300 Hz and (b) 800 Hz; input voltage of (c) 80 V and (d) 130 V; output power of (e) 120 W and (f) 50 W. Inductor current: (a)–(d), (f) [0.5 A/div], (c) [1 A/div]. Input voltage: [100 V/div].

5.7 Conclusion

113

1 0.99 Power factor, PF

0.98 0.97 0.96 0.95 0.94 0.93

Derived current control ACM control

0.92 200

300

400

500

600

700

800

900

Line frequency, f [Hz]

(a) 1

Power factor, PF

0.99 0.98 0.97 0.96 Derived current control ACM control

0.95 0.94 70

80

90 100 110 120 130 Input voltage Vi, rms [V]

140

150

(b) 1

Power factor, PF

0.99 0.98 0.97 0.96 Derived current control ACM control

0.95 0.94

20 30 40 50 60 70 80 90 100 110 120 130 Output power, Po [W]

(c)

Figure 5.12: Power factor measured under the variations of (a) line frequency, (b) input voltage and (c) output power.

Chapter 6 The Feedback Linearization Approach for the Derivation of Robust Voltage Loop Control 6.1 Introduction In Chapter 5, we have introduced the method of feedback linearization and succeeded in generating the robust current loop control solution. Through removing the nonlinearity of the current loop’s error dynamics, the approach generates a nonlinear control rule that eliminates the input current distortion and maintains consistent tracking performance under all practical conditions. In this chapter, we extend the approach to the voltage loop control, which is highlighted in Fig. 6.1. We will show that the derivation approach applies equally well to the outer voltage loop, which results in a robust voltage loop control rule with improved and consistent transient response performance under various operating conditions.

6.1.1 Problems of the existing voltage loop control As mentioned in Chapter 5, the objective of the voltage loop control is to maintain a constant average voltage over the rectified line frequency. In order to achieve this objective without contaminating the reference current signal with the output’s line fre114

6.1 Introduction

115

vo vi

i

L

current loop control

L vgs

i

D

|sin t| ref

I

D

C

SW

multiplier

i

ref

R

voltage loop control

Figure 6.1: Boost PFC converter with the control based on the multi-loop control structure. The voltage control loop is highlighted to indicate the adoption of the proposed derivation approach. quency ripple, the voltage loop’s bandwidth is deliberately limited to be lower than the line frequency. Such narrow bandwidth makes the output voltage suffer from poor transient response with relatively large overshoots in the event of sudden load change. In the literature, numerous attempts have been made to improve the output transient response of the PFC converter, which have been discussed in Chapter 1. Similar to the problems of the existing current loop control, most of these voltage loop control schemes were specifically developed to tackle the problem of sluggish transient response. Specifically, for the feedforward control schemes, a systematic derivation procedure is still missing. Moreover, the complexity of their closed-loop models hinders analysis of their large-signal behaviors. The resulting performance cannot be predicted accurately and trial-and-error procedures become necessary in the design of the control parameters, with the design constraints and the optimal design solution remained unknown.

6.1.2 Application of the feedback linearization to the voltage loop control The afore-mentioned problems can be solved by applying the feedback linearization approach to the outer voltage loop. In a likewise manner, by eliminating the undesirable phenomena incurred by the nonlinearity and the dependency of the voltage loop dynamics on the input disturbance, this approach generates a robust control solution

116

6. The Feedback Linearization Approach for Voltage Loop Control

that results in improved and robust transient-response performance. The linearized dynamical equation fully describes the closed-loop behaviors of the voltage loop, based on which the loop gain and the transient response waveform can be predicted accurately. The information facilitates the design of the control parameters such that loop stability can be ensured and at the same time, improved transient response can be achieved. The performance of the resulting voltage loop control rule will be evaluated by experiments.

6.2 Derivation of the Voltage Loop Control This section presents the derivation of the outer-loop voltage control using the feedback linearization approach. Based on the discussion in Chapter 5, low-frequency averaging over the rectified line frequency is adopted for the voltage loop modeling to account for the separation of time scale between the voltage control and the current control. Assume that the converter has a very high efficiency with η ≈ 1. By power balance, the averaged diode current can be represented as iD (t) =

Vi IL sin2 ωt, vo (t)

(6.1)

where iD (t) is the diode current, Vi the peak input voltage, IL the peak inductor current and vo (t) the output voltage. To simplify the derivation, we assume that the output capacitor is large enough to guarantee a small line frequency ripple in the output voltage, and the average of iD (t) over a rectifier line cycle iD =

T 2

is approximated as

IL Vi . 2vo

(6.2)

Here we denote x as the average value of x(t) over a rectified line cycle. The averaged model of the voltage loop is represented by v˙ o (t) =

1 (iD (t) − io (t)) C

(6.3)

where io (t) is the output current. Equation (6.3) is further averaged over the rectified line cycle to become 1 dvo = dt C

µ

¶ Vi IL − io . 2vo

(6.4)

6.2 Derivation of the Voltage Loop Control

117

Under the assumption of an ideal current loop, IL = Iref with Iref being the peak reference current, which can be regarded as the control input of the voltage loop, i.e., µ ¶ 1 Vi Iref dvo = − io . (6.5) dt C 2vo Similarly, the voltage control can be regarded as a tracking control problem in the resolution of the rectified line frequency. Here we denote the voltage error by ev = Vref − vo ,

(6.6)

where Vref is the constant reference voltage. The dynamics of the voltage error is

µ ¶ dVref dvo 1 Vi Iref dev = − = io − . (6.7) dt dt dt C 2vo The reference signal Iref is the amplitude of the reference current, which is the control output generated by the outer-loop. Based on the feedback linearization, the error dynamics (6.7) can be made linear if Iref is chosen as 2vo (io − Cvva ) Iref = (6.8) Vi with vva being an equivalent input. Thus, the resulting error dynamics is simplified to dev = vva . (6.9) dt Similar to the current loop derivation, vva is chosen to be a linear PI function for minimizing the steady-state error in the output voltage, i.e., Z vva = −Kv1 ev − Kv2 ev dt

(6.10)

with Kv1 > 0 and Kv2 > 0. By substituting (6.10) into (6.9), the voltage error dynamics becomes With Kv1 and Kv2

Z dev + Kv1 ev + Kv2 ev dt = 0. (6.11) dt being positive, the voltage error converges to zero exponentially.

Finally, combining (6.10) and (6.8) gives the resulting voltage control rule: · µ ¶¸ Z 2vo io − C Kv1 ev + Kv2 ev dt . (6.12) Iref = Vi Again, equation (6.12) can be implemented as an individual voltage controller. Alternatively, the resulting control can be implemented by adding the load-current feedforward and the corresponding functions (e.g. summation, inversion) in standard controller circuits, which become similar to some previously proposed load-current feedforward schemes [78].

118


6.3 Sample-and-Hold Function The direct implementation of the resulting control has a drawback that the input current can be distorted by the line frequency ripple in the feedfowarded load-current signal and feedbacked output voltage signal. This problem can be solved by applying the sample-and-hold (S/H) function to the control output signal such that the control output is sampled at every zero-crossing of the line voltage. This approach offers several advantages. First, unity power factor is ensured even in the presence of the line frequency ripple in the feedforward and feedback signals. Second, according to the Nyquist’s sampling theorem [130], the maximum bandwidth of the voltage loop is automatically limited to the line frequency. This ensures the validity of our basic assumption, which is the decoupling of the current loop and voltage loop dynamics. Third, with the unity power factor already ensured by the S/H function, more flexibility is offered to the design of the control parameters. Finally, maintaining fixed sampling instants enables easy prediction of the transient response waveforms under the derived control rule, which will be shown in the subsequent sections. The drawback of using the S/H function is that it is noise sensitive and the high frequency noise in the incoming signal needs to be filtered to avoid false-triggering. Fig. 6.2 depicts the simplified schematic of the outer-loop voltage control rule with the S/H circuit included. Properties of the derived control will be further explored in the following sections.

vo L

vi

D

SW i

|sin t|

i

L

i ref

S/H

2v o Vi

O

R

v

gs

L

ideal current loop (i =i ) L

ref

ref

I

C

i

(

PI

C K v1 + K v 2 ∫ dt

)

V

ref

outer-loop voltage control

Figure 6.2: Boost PFC converter with the derived outer-loop voltage control rule.


6.4

119

Frequency Response Analysis

In this section, the frequency response of the voltage error dynamics is investigated. The dynamics of the voltage error (6.11) can be written as Z dvref dvo = + Kv1 (vref − vo ) + Kv2 (vref − vo )dt. dt dt

(6.13)

Due to the linear nature, (6.13) is readily expressed in the s-domain as ¶ µ 1 . svo = svref + (vref − vo ) Kv1 + Kv2 s

(6.14)

In a likewise manner, the block diagram of (6.14) is depicted in Fig. 6.3 and the loop gain Gv is obtained as Gv =

´ ³ Kv1 Kv2 1 + s K v2 s2

.

(6.15)

The frequency response is determined by (6.15). Having a similar structure as Gi , Gv also contains a double pole at the origin and a zero determined by Kv1 and Kv2 . Similarly, the robustness of the steady-state performance is reflected by the independence of the loop gain of the operating conditions, which is a straight-forward result of the linearization of the error dynamics. To account for the non-idealities in the practical converter, an improved transfer function G0v can be formulated by ´ ³ Kv1 Kv2 1 + s K v2 · Hv , G0v = 2 s 1 s s

K v1 + K v 2

vo

vref

1 s

  s + K v1 + K v 2 

K v1 + K v 2 vo

vref

(a)

(6.16)

11  ss

1 s

s + K v1 + K v 2

vo

vo

1 s

(b)

Figure 6.3: (a) Block diagram of the voltage error dynamics under the derived voltage control rule; (b) block diagram in general form.


120

where Hv is the transfer function accounting for the effects of the S/H function and the low-pass filter on the loop gain, i.e., Hv = ³

1 ´ , 1 + ωsp4 (1 + sTh )

(6.17)

where ωp4 is the pole frequency of the low-pass filter and Th is the hold-time of the S/H circuit, which approximately equals a half line cycle T2 . Using (6.16), frequency response of the voltage loop gain can be computed. Fig. 6.4 shows the computed frequency response plots with different combinations of Kv1 and Kv2 . Measured from the experimental circuit (see Fig. 6.7), ωp4 ≈ 3 x 103 rads−1 and Th ≈ 1 ms. In Fig. 6.4(a), under a fixed Kv2 , as Kv1 increases, the crossover frequency is slightly increased, and the phase margin is increased with a larger amount. In Fig. 6.4(b), under a fixed Ki1 , as Ki2 increases, the crossover frequency is slightly increased, but the phase margin is decreased drastically. Hence, Kv1 and Kv2 can be selected according to the desired crossover frequency and phase margin to ensure voltage loop stability and satisfactory regulation performance. It is worthy to note that since the S/H function samples the control output signal at the rectified line frequency, the hold time Th and the resulting frequency response plots vary with the operating line frequency. Such variation can be minimized by a conservative choice of Kv1 and Kv2 . For a cautious design, Kv1 and Kv2 should be designed based on the frequency response corresponding to the lowest operating frequency.


121

Gain [dB]

100

KV2 = 4.5 x 104

KV1 = 760 KV1 = 380 KV1 = 190

50

0

10

0

10

1

2

10

10

3

Frequency [Hz]

Phase [deg]

-100

-150

KV1

KV1

= 760 = 380

KV1 = 190

-200

-250 0 10

10

1

2

10

10

3

Frequency [Hz]

(a)

Gain [dB]

100

KV1 = 380

KV2 = 9 x 104 KV2 = 4.5 x 104 KV2 = 2.25 x 104

50

0

10

0

10

1

2

10

10

3

Frequency [Hz]

Phase [deg]

-100

-150

KV2 = 2.25 x 104

KV2 = 4.5 x 104

-200

-250 0 10

KV2 = 9 x 104 10

1

2

10

10

3

Frequency [Hz]

(b)

Figure 6.4: Computed frequency responses of Gv with various combinations of control parameters: (a) Kv1 is varying with Kv2 fixed at 4.5 × 104 ; (b) Kv2 is varying with Kv1 fixed at 380.


122

6.5 Transient Response In addition to the steady-state performance and the system stability, output transient response can be predicted based on the mathematical derivation in Section 6.2. Differentiating the voltage error’s dynamics (6.11) gives dev d2 ev + Kv1 + Kv2 ev = 0, 2 dt dt

(6.18)

which is a homogeneous second-order differential equation governing the transient response of the voltage error. Solving (6.18) gives ev (t) = −

b1 (t) + b2 (t) √ , 2 D

(6.19)

where 2 D = Kv1 − 4Kv2 ;

√ (−Kv1 ev (0) + Dev (0) − 2e˙ v (0)); b1 (t) = e √ √ b2 (t) = e0.5(−Kv1 + D)t (Kv1 ev (0) + Dev (0) + 2e˙ v (0)). √ 0.5(−Kv1 − D)t

(6.20) (6.21) (6.22)

Under the derived voltage control rule, the initial conditions ev (0) and e˙ v (0) can be obtained from the steady-state condition with the instant of the load change being known. Using (6.19), transient response waveforms of the error voltage can be traced. For illustration, Fig. 6.5 shows the transient response waveforms computed from (6.19) with different combinations of Kv1 and Kv2 . Referring to Fig. 6.5(a), with Kv2 fixed, increasing Kv1 results in increased damping of the error voltage waveform. However, excessively large Kv1 results in over-damped response with prolonged settling time, while an excessively small Kv1 results in oscillatory response with prolonged settling time. Likewise, with Kv1 fixed in Fig. 6.5(b), increasing Kv2 results in increased damping of the error waveform with longer settling time, whereas decreasing Kv2 results in less damping with shorter settling time. Hence, the control parameters Kv1 and Kv2 can be adjusted according to the desired transient response waveforms, in conjunction with the frequency response for stability and performance trade-offs. Although our study focuses on high line frequency applications for illustrating the current distortion issue, the derived control rules can also be applied to mains line frequency of 50 or 60 Hz. In this case, no mandatory change is required for the design of the current loop. As for the voltage loop, since the sampling frequency of the S/H

6.5 Transient Response

123

circuit is lowered to 100 or 120 Hz, the corresponding pole or phase drop will move down to around 50 or 60 Hz. In order to ensure stability, the control parameters need to be adjusted using the Bode plots to allow sufficient phase margin.

voltage error (in percentage of V ref ) [%]

1

KV2 = 4.5 x 104

0.8

KV1 = 640 KV1 = 510 KV1 = 380

0.6 0.4 0.2 0 -0.2 -0.4

KV1 = 250 KV1 = 200

-0.6 -0.8

0

0.01

0.02

0.03

0.04

0.05

0.06

time [s]

(a) voltage error (in percentage of V ref ) [%]

1

KV1 = 380

0.8

KV2 = 1 x 104

0.6

KV2 = 2.5 x 104 KV2 = 4.5 x 104

0.4 0.2 0

KV2 = 6 x 104

-0.2

KV2 = 8 x 104

-0.4 -0.6 -0.8

0

0.01

0.02

0.03

0.04

0.05

0.06

time [s]

(b)

Figure 6.5: Transient response of the error voltage with various combinations of control parameters: (a) Kv1 is varying with Kv2 fixed at 4.5 × 104 ; (b) Kv2 is varying with Kv1 fixed at 380.

124

6. The Feedback Linearization Approach for Voltage Loop Control vo

L

vi

D v

SW

V |sin t|

i

i

i

PWM signal

L

(

PI

ref

|sin t|

L I

ref

S/H

d dt

)

R i

o

PWM

L

L K i1 + K i 2 ∫ dt i

C

gs

v

vi

v

o

ram p

inner-loop current control

(

2Vref

PI

C K v1 + K v 2 ∫ dt

Vi

)

outer-loop voltage control

V

ref

Figure 6.6: Boost PFC converter with complete control scheme.

6.6 Practical Implementation Including the inner-loop current control derived in the previous chapter, the complete robust control scheme of the boost PFC converter is depicted in Fig. 6.6. A laboratory prototype of the boost PFC converter and the general control circuit are constructed using analog devices. A simplified schematic of the hardware prototype is shown in Fig. 6.7 and the key circuit parameters are shown in Table 6.1. For implementation of the outer-loop voltage control, the control voltage generated from the control circuit is obtained from (6.12) with proper scaling · µ ¶¸ Z β12 io − C Kv1 ev + Kv2 ev dt , vvc = Vref β2

(6.23)

where β1 is the ratio of Vf f to Vi,rms , and β2 is the scaling factor of the input voltage feeding into the multiplier. In our experimental circuit, β1 = 0.02364 and β2 = 0.02516. vio is the sensed load-current using a small resistor. vo is replaced by Vref for simplified implementation. The control voltage is fed into the S/H circuit with the sampling pulse generated by the zero-crossing detection circuit. The output of the S/H circuit is then fed into the multiplier circuit to produce the reference current for the inner current loop. With the adoption of the derived voltage loop control rule, stability specifications, such as the phase margin, and desirable performance specifications, such as the


125

transient-response overshoot and the recovery time, can be achieved by the selection of Kv1 and Kv2 using (6.16)–(6.17) and (6.19)–(6.22). The control parameters Kv1 and Kv2 can be related to the component values by Kv1 =

β2 Rvz β2 ; Kv2 = , 2 Rvl CVref β1 Rvl Cvz CVref β12

(6.24)

where Rvl , Rvz , Cvz are the main components in the compensation network of the voltage error amplifier (Fig. 6.7). Again, the conventional ACM control circuit employing standard controller UCC3817 (Fig. 5.8) is adopted for comparison. The control circuit is applied to the same boost power stage in Fig. 6.7. The design of the compensation parameters follows the conventional design approach [129] with the voltage loop crossover frequency is 1/10 of the nominal line frequency at around 50 Hz to ensure low distortion in the input current. The resulting phase margin is 45◦ . It is worthy to mention that although the compensation of the voltage amplifier in the ACM control can also be optimized using Bode plots with some sort of stability and performance trade-offs, it will be shown clearly that the derived voltage loop control outperforms the ACM control under similar stability specifications in the next section.


126

18V

V

ff

vi V

14 13 43 12 7D11 A10 9 8

1 2 3 4 5 6 7

V

500 Hz 110 Vrms 2

ff

0.01 F

vgs

18V

2vi 1 2 3 4 5 6 7

LM318 2M

14 13 43 12 7D11 A10 9 8

v

15V

iref

V

20 0

ramp

VNL2222 External Clock

1 nF

20 0

iz

270 pF

270 pF

C

100 pF

iz

R

v

il

10 0 pF

20

10 k

iref

270 pF

LM318

LM318 10 k

iL

LM318

10 k

510 k 10 k

v

10 k

3.9 k

1k

1N5819 10 k

8 V 4.5 V

ref

Outer-loop voltage control circuit

ip

16.65 0.9 nF k LM318

v

50 k

V

Voltage error amplifier

Current error amplifier

10 k 10 k

2N 66 03

70 nF LM318

100 k

C R

LM318

10 k

vz

120 k

100 k

gs

10 k

10 k

io

vp

vz

Comparator and driver

LM318

C 2.74 nF v R C

100 k

io

MC34152

10 k

10 k

10 k 60 k Zero-croosing detection vi LM318 v Sample & hold circuit Loading current sampling amp. v

Inner-loop current control circuit 10 k

2N 66 03

iL

1 3 7 N 86 5 93 1 nF 4 FL 8

510 k

vl

1

LM318

vvc

-15V

LM318

vic

s

0.25

R da oL

R

100 F

SW

10 k

-18V

Multiplier circuit Vramp

v

vo

D C

IRF840 R

10 k

2

APT15060B

L

ff

-18V

510 k

1 mH

vi

100

100 nF

v 1k

iref

Ref. current differentiator

O

3vo 10 k

Variable ramp generator

v

10 k 10 k LM318 1k

Input voltage buffer

i

510 k 3vi 10 k

Figure 6.7: Simplified schematics of the boost PFC converter with the derived control rules implemented as individual control circuitries.

6.7 Experimental Results

127

6.7

Experimental Results

6.7.1

Voltage loop control evaluation

Similar experiments have been conducted to evaluate the performance of outer-loop voltage control. The selected control parameters are: Kv1 = 381 and Kv2 = 4.51×104 for yielding consistent crossover frequency and phase margin with the ACM control in the voltage loop gain. First, Bode plots of the voltage loop gain are measured under the dc line voltage of 110 V. The measured Bode plots are shown along with the analytical results in Fig. 6.8. The measured data agree with the theoretical results and verify the loop gain characteristic. The deviations can be attributed to the components’ tolerance and the round-off error of the S/H function. Second, the derived voltage control is compared with the conventional ACM control in transient-response performance. The output current is stepping from 0.4 A to 0.14 A. Fig. 6.9 shows the resulting waveforms. Under the derived control, the transient response improves with the overshoot amplitude reduced from 5 V to 2.5 V and

100 Exeperimental Theoretical

80 Gain [dB]

60 40 20 0 −20 −40 0 10

1

2

10

3

10

10

Frequency [Hz]

Experimental Theoretical

Phase [deg]

−100 −150 −200 −250 0

10

1

2

10

10

3

10

Frequency [Hz]

Figure 6.8: Experimental and theoretical Bode plots of the voltage loop gain with control parameters Kv1 = 381 and Kv2 = 4.51 × 104 .

128


output voltage vo

output voltage vo

output current io

output current io

(a)

(b)

Figure 6.9: Transient response waveforms under (a) the ACM control and (b) the derived voltage control. Output voltage: (a) [2 V/div], (b) [1 V/div]. Output current for both (a) and (b): [0.2 A/div]. Time scale: [10 ms/div]. the settling time shortened from 25 ms to 20 ms. The result verifies the capability of the derived control of improving the transient-response performance. It should be noted that the above configuration is not optimal for transient response because the crossover frequency of the voltage loop is set at only 50 Hz for consistency with the ACM design. A shorter recovery time can be achieved by increasing the crossover frequency with other combinations of Kv1 and Kv2 , such as the examples in Figs. 6.10(c) and (d), which will be discussed next. Third, the derived voltage control is examined in terms of the transient response waveforms with different combinations of Kv1 and Kv2 . The resulting transient response waveforms match with the predicted waveforms using (6.19). Fig. 6.10 shows some illustrative waveforms with some selected combinations of Kv1 and Kv2 . The results verify the accuracy of the derived error dynamics and the predicted effects of the control parameters. Finally, the converter is tested over a range of input voltage and loading condition for output transient response. It turns out that as the input voltage varies from 80 Vrms to 140 Vrms, the voltage overshoot and the settling time are consistent at around 2.5 V and 20 ms, respectively. For illustration, Figs. 6.11(a) and (b) show the transient waveforms at some selected input voltages. As the loading condition varies, although the voltage overshoot changes with the load step, the settling time remains approximately constant at around 20 ms. Figs. 6.11(c) and (d) show the transient response waveforms at some selected loading conditions. The above results confirm the robustness of the derived voltage control in the variations of line voltage and loading condition.

6.8 Conclusion

129

output voltage vo

output voltage vo

output current io

(a)

(c)

output current io

(b)

output voltage vo

output voltage vo

output current io

output current io

(d)

Figure 6.10: Transient response waveforms with various combinations of Kv1 and Kv2 : (a) Kv1 = 380 and Kv2 = 4.5 × 104 ; (b) Kv1 = 220 and Kv2 = 4.5 × 104 ; (c) Kv1 = 510 and Kv2 = 4.5 × 104 ; (d) Kv1 = 380 and Kv2 = 2.5 × 104 . Output voltage: [1 V/div]. Output current: [0.2 A/div]. Time scale: [10 ms/div].

6.8 Conclusion In this chapter, we have applied the feedback linearization approach in the outer voltage loop and succeeded in generating a robust voltage loop control rule that results in improved transient response with consistent performance under all practical conditions. Similar to the current loop control, the voltage loop control parameters can be designed according to the frequency response analysis to ensure voltage loop stability. Moreover, through the linearized dynamical equation and the use of sample-and-hold function, the transient response waveform of the output voltage can be traced out. By adjusting the control parameters, the transient response waveform can be fine-tuned to meet the desired specifications such as overshoot and recovery time. The accuracy of our modeling and analysis of the closed-loop system has been verified by experiments. Further, the experimental results confirmed that the derived voltage control is capable of achieving improved transient response and maintaining consistent performance

130


output voltage vo

output voltage vo

output current io

output current io

(a)

(b)

output voltage vo

output voltage vo

output current io

output current io

(c)

(d)

Figure 6.11: Transient response waveforms at various operating conditions: line voltage at (a) 140 Vrms and (b) 80 Vrms; stepping load-current of (c) 0.4 A to 0.14 A and (d) 0.2 A to 0.14 A. Output voltage: [1 V/div]. Output current: [0.2 A/div]. Time scale: [10 ms/div].

under the variations in line voltage and loading conditions. Summarizing the studies in this chapter and Chapter 5, a unified approach has been introduced for systematic derivation of robust control rules for the inner current loop and the outer voltage loop of the boost PFC converter. Based on feedback linearization, the unified approach removes the nonlinearity and the dependency of the error dynamics on the input disturbance. A desired dynamics can also be imposed to closed-loop system. This technique leads to nonlinear control rules that improve the converter’s steady-state and transient-response performances, with consistency maintained in various operating conditions. The control parameters can be designed according to the frequency response analysis to ensure closed-loop stability and satisfactory performance. In conjunction to these criteria, we can also adjust the control parameters to yield desired transient response waveforms. The derived control rules are readily implemented using analog devices. They can also be integrated in any PFC controller IC to simplify the implementation. It is hoped that these studies can provide useful guide-

6.8 Conclusion

131

Table 6.1: Circuit parameters used in the experiments Parameters of PFC stage

Values


110 V


500 Hz

Reference output voltage Vref

270 V

Switching frequency fsw

100 kHz

Inductance L

1 mH

Sensing resistor Rs

0.25 Ω


100 µF


1.2 kΩ

Scaling factor β1

0.02364

Scaling factor β2

0.02516

Compensation components Rvz , Cvz , Cvp

120 kΩ, 70 nF, 274 nF

lines to engineers for designing the control for high-performance PFC converters.

Chapter 7 Re-Visit of Robust Current Control From a Sliding Mode Viewpoint 7.1 Introduction In Chapter 5, we have succeeded in generating the robust current control solution for the boost PFC converter using the method of feedback linearization. In this chapter, we re-visit the current control rule from an alternative approach under the framework of sliding mode (SM) control [45], [52]. The reasons for adopting a SM control viewpoint are as follows: 1. SM control theory is well established in the literature [51], [57], and hence provides a solid framework for systematic derivation of robust control rules. 2. The invariance property of SM control can be directly described in terms of the feedforward compensation components, which can be readily deduced from the closed-loop dynamical equation. Thus, the concept of equivalent control can be conveniently applied. 3. The concept of sliding plane in the SM control approach offers a clear picture of the linearized dynamics of the closed-loop system and facilitates the design of the control parameters. However, SM control is hysteresis-based and the switching function cannot be directly applied to the derivation of the PWM control. Nevertheless, by applying the 132

7.2 Sliding Mode Control

133

concept of equivalent control [45] in the SM control theory to the averaged model of the PWM control, a PWM control solution can be generated. Although the generated control cannot be regarded as SM control due to its PWM nature, it inherits from the SM-based approach the advantage of robust performance [52] and yet operates at a fixed switching frequency due to its PWM nature [60]. It also eliminates the undesirable phenomena due to the inherent non-linearities of the current loop dynamics, such as the zero-crossing distortion mentioned previously. The SM-based derivation approach also provides insights into the design and optimization of the controller parameters through the manipulation of the sliding surface equation which is not available in the conventional derivation approach of feedforward control. The stability of the current loop can be assessed by frequency response analysis, which follows the same procedure as in Chapter 5 and is not repeated here. Specific to the SM-based approach, SM operation can be ensured by the existence condition, which imposes additional constraints to the design of the control parameters. As mentioned in Chapters 5 and 6, besides implementating the derived control rule as a dedicated current control circuit, it can also be implemented as add-on feedforward schemes applied to standard PFC controllers. The feedforward implementation schemes using different types of PFC controllers will be discussed in this chapter. The performance of the implementation circuits will be evaluated by simulation.

7.2 Sliding Mode Control 7.2.1 Main idea of sliding mode control In general, sliding mode (SM) control is a class of nonlinear control introduced for the robust control of variable structure systems (VSS). SM control theory has a long development history and its potential applications in power converters have attracted much research attentions, as discussed in Chapter 1. The main idea of SM control is to predefine an ideal manifold for the state trajectory to travel along. This manifold is known as the “sliding surface”. Upon the satisfaction of certain criteria, the state trajectory is directed towards the sliding surface and travels along it towards the origin, which is the equilibrium point where the control error is zero. This series of operation is termed the “sliding mode operation”. During the SM operation, the system dynamics follows the

134

7. Re-Visit of Robust Current Control From a Sliding Mode Viewpoint

sliding surface equation, which is typically designed to be linear and independent of other input disturbances. Therefore the controlled system exhibits constant dynamical behaviors even in the presence of input disturbance, which is known as the “invariance property” of SM control. In the control of power converters, this feature of robustness is reflected by the consistent steady-state and transient-response performances under all practical conditions.

7.2.2 General SM control derivation The general derivation procedure of SM control can be exemplified by the generation of voltage control for a single-switch dc-dc converter [131]. Here we denote the state variables of the converter by x, which is described by    x1 Vo,ref − vo    d   x=  x2  =  R dt (Vo,ref − vo ) (Vo,ref − vo )dt x3

   

(7.1)

where x1 , x2 and x3 denote the voltage error, the dynamics (or the rate of change) of the error and the integral of the error respectively. According to the power stage’s dynamical equations, the dynamics of the system can be written as x˙ = Ax + Bv + D

(7.2)

where A, B and D are matrices with constant real entries. Variable v = u or u¯ (depending on topology), with u begin a scaler control taking discrete value of either 0 or 1 and u¯ being the inverse logic of u. To control the switching converter in a hysteresisbased manner, it is appropriate to adopt the control law 1 u = (1 − sign(S)) 2 which represents

( u=

1, when

S>0

0, when

S 0.

(7.7)

(7.8)

From the inequalities in (7.8), we can extract the necessary conditions for SM operation to exist. If the existence condition is violated, the state trajectory either fails to reach the sliding surface from its initial condition, or leaves the sliding surface half-way and fails to converge to the equilibrium point. In other words, the existence condition imposes additional constraints to the selection of SM coefficients for ensuring SM operation.

7.3 Theoretical Derivation In this section, the control rule for the inner current loop of the boost PFC converter is re-examined under the derivation framework of SM control, which has been covered in the previous section. In our derivation, we assume that there is no interaction between the dynamics of the inner-loop and that of the outer-loop. This assumption holds by virtue of the wide separation of time scales of the two control loops. Specifically, the input current is controlled cycle-by-cycle to track the reference current at the switching frequency, whereas the output voltage is only regulated for its averaged value over the

136


vo(t)

L

v (t) i

SW i (t) L i

vgs

D

R

PWM signal

Current loop controller

(t)

L

C

i

(t)

ref

Figure 7.1: A boost PFC converter with the inner loop current control. line frequency. Thus, the bandwidth of the inner current loop is usually more than a decade higher than that of the outer voltage loop. Therefore, we can assume that the dynamics of the inner current loop is decoupled from that of the outer voltage loop and an ideal rectified sinusoidal reference current is generated by the voltage loop. The simplified circuit diagram of the inner current loop is shown in Fig. 7.1. Based on the SM control derivation framework [52], we take the current error, x1 (t), the integral of the current error, x2 (t), and the double integral of the current error, x3 (t) as the controlled state variables. The double-integral term is included to minimize the steady-state error caused by the finite switching frequency [127]. The state variables are described as x1 (t) = iref (t) − iL (t); x2 (t) =

Z

Z Z x1 (t)dt; x3 (t) =

x1 (t)dtdt,

(7.9)

where iL (t) denotes the instantaneous inductor current and iref (t) represents the reference input current. The state trajectory is defined as a linear combination of the state variables, i.e., S(t) = α1 x1 (t) + α2 x2 (t) + α3 x3 (t)

(7.10)

where α1 , α2 and α3 are the control parameters. They can be regarded as the sliding mode coefficients. Considering that the boost converter is operating in continuous conduction mode (CCM), the power stage dynamics of iL (t) can be described by 1 i˙ L (t) = (vi (t) − u¯vo (t)), L

(7.11)

7.3 Theoretical Derivation

137 v

o

L v

L

i

ref

L

R

PWM signal

i

i

C

gs

SW

i

D

v

PWM

(

PI

L K1 + K2 ∫ dt L

)

vo

v

ramp

v

i

d dt

SM-derived general current controller Figure 7.2: A boost PFC converter with the current loop employing the derived control rule. and the time differentiation of (7.9) gives the dynamic model of the proposed system as x˙ 1 (t) =

1 diref (t) − (vi (t) − u¯vo (t)); x˙ 2 (t) = x1 (t); x˙ 3 (t) = x2 (t), dt L

(7.12)

where u is the switching logic which is either 0 or 1. Variable u¯ = 1 − u is the inverse logic of u, vi (t) denotes the rectified input voltage and vo (t) denotes the output voltage. Based on the SM control theroy, the invariance conditions of SM control ˙ enforce S(t) = 0 and S(t) = 0, which gives ˙ S(t) = α1 x˙ 1 (t) + α2 x˙ 2 (t) + α3 x˙ 3 (t) = 0.

(7.13)

This is the case of ideal SM control with infinite switching frequency. In practical control with finite switching frequency, the trajectory is maintained within a small vicinity of the sliding surface through a series of switching actions. Therefore, the trajectory’s dynamics obeys (7.13) only at particular instants within a switching cycle. The same applies to the PWM control. To derive the PWM control law, we apply the concept of equivalent control, such that the switching logic u¯ is substituted by the continuous signal u¯eq with the boundaries 0 < u¯eq < 1.

(7.14)


138

For PWM control, the instantaneous values of x˙ 1 (t), x˙ 2 (t) and x˙ 3 (t) that obey (7.13) can be regarded as their average values over a switching cycle, which are obtained by taking the average of (7.12), 1 diref − (vi − u¯eq vo ); x˙ 2 = x1 = iref − iL ; x˙ 3 = x2 = x˙ 1 = dt L

Z iref − iL dt. (7.15)

Here we denote x as the average value of x(t) over a switching cycle. It is worthy to note that it is always true that vi (t) = vi , vo (t) = vo and iref (t) = iref because they contain no switching ripple. Thus, the dynamics of the sliding surface (7.13) becomes S˙ = α1 x˙ 1 + α2 x˙ 2 + α3 x˙ 3 = 0.

(7.16)

Equation (7.16) is a second-order homogeneous differential equation. Based on the Routh-Hurwitz criterion, x1 converges to 0 and x1 = 0 is the equilibrium point as long as α1 , α2 and α3 are of the same sign. Applying (7.15) and (7.14) to (7.16) gives α1

α1 diref − (vi − u¯eq vo ) + α2 x1 + α3 x2 = 0. dt L

(7.17)

Solving (7.17) for u¯eq gives 1 u¯eq = vo

µ

Ldiref − + vi − LK1 x1 − LK2 x2 dt

¶ (7.18)

where K1 =

α3 α2 ; K2 = . α1 α1

Equation (7.18) is the resulting current control rule and is depicted in Fig. 7.2. It inherits the invariance property of SM control such that if the duty cycle is configured as (7.18), the current error dynamics will follow (7.16) associated with the sliding surface, which is independent of the input disturbances such as the input voltage and the loading condition. This eliminates all the undesirable phenomena incurred by the nonlinearity and the dependency of the system dynamics on the input disturbance, such as the zero-crossing distortion mentioned previously, and results in designated and consistent control performance under variations of operating condition.

7.4 The Existence Condition

7.4

139

The Existence Condition

7.4.1

Saturation of duty cycle

This section investigates the existence conditions of SM operation. In PFC converters, at the zero-crossing position, SM operation is violated due to the unavailability of the input voltage (input voltage being zero). Assume that the current error is negligible at the zero-crossing position from vi = 0− to vi = 0+ , i.e., iL = iref . During this interval, the equivalent duty cycle can be represented by: u¯eq = −

L diref . vo dt

(7.19)

At vi = 0, u¯eq is undefined due to the discontinuity of diref /dt. Moreover, when vi = 0 − , u¯eq =

L Iref ωm , vo

(7.20)

where Iref is the peak value of iref and ωm is the line frequency in rads−1 . When vi = 0+ , u¯eq = −

L Iref ωm . vo

(7.21)

As u¯eq becomes negative, the duty cycle is saturated. During the saturation of the duty cycle, the inductor current can be described by iL,sat =

Vi (1 − cos ωm t) , ωm L

(7.22)

where Vi is the peak value of vi . When vi > 0, the saturation continues until u¯eq increases from a negative value back to zero. The time interval of the saturation to can be found by setting u¯eq to zero, i.e., 1 u¯eq = vo

µ

diref vi − L − LK1 (iref − iL,sat ) − LK2 dt

Z

¶

to

(iref − iL,sat )dt 0

=0 (7.23)


140 0.02

0.04

0.015

0.03

saturation of duty cycle

0.01 0.005 q e

u

t

] 0.02 A [ iL

o

fe

ir

u eq

-0.02 -5

t

5 Time [µ s]

10

15 x 10

L

o

-0.01

saturation of duty cycle

-0.02 -5

0

discontinuity 0

ref

0

-0.01 -0.015

i

i

d 0.01 n a

0

-0.005

discontinuity

-6

(a)

5 Time [µ s]

10

15 x 10

-6

(b)

Figure 7.3: Calculated waveforms of (a) u¯eq and (b) iL and iref during the saturation period. Expanding (7.23) gives ¸ Vi (1 − cos ωm to ) Vi sin ωm to − LIref ωm cos ωm to − LK1 Iref sin ωm to − ωm L ¸ · 1 Iref Vi (1 − cos ωm to ) + ( sin ωm to − to ) = 0 −LK2 ωm ωm L ωm (7.24) ·

The above equations can be solved numerically for to with different choices of K1 and K2 . For illustration, using K1 = 6 × 104 and K2 = 4 × 109 and the parameters of the suggested implementation circuits (see Fig. 7.7, Fig. 7.8 and Table 7.1), the calculated time interval is to = 5.94 µs, which also represents the initial time when the saturation finishes and the system returns back to the sliding surface. For illustration, Fig. 7.3 shows the waveforms of u¯eq , iL and iref during the saturation period.

7.4.2 Transient response of the current error Under SM operation, we can obtain the transient response of the current error by further differentiating (7.16) with time to give dx1 d2 x1 + K1 + K2 x1 = 0, 2 dt dt

(7.25)

7.4 The Existence Condition

141

which is a second-order differential equation describing the transient response of the current error. Solving (7.25) gives b1 (t) + b2 (t) √ 2 D b˙ 1 (t) + b˙ 2 (t) √ x˙ 1 = 2 D x1 =

(7.26) (7.27)

where D = K12 − 4K2 ; (7.28) h i √ √ (7.29) b1 (t) = (−K1 + D)x1 (to ) − 2x˙ 1 (to ) e0.5(−K1 − D)t ; h i √ √ (7.30) b2 (t) = (K1 + D)x1 (to ) + 2x˙ 1 (to ) e0.5(−K1 + D)t ; i √ √ √ h ; b˙ 1 (t) = −0.5(K1 + D) (−K1 + D)x1 (to ) − 2x˙ 1 (to ) e0.5(−K1 − D)t(7.31) h i √ √ √ b˙ 2 (t) = −0.5(K1 − D) (K1 + D)x1 (to ) + 2x˙ 1 (to ) e0.5(−K1 + D)t . (7.32) The initial conditions can be obtained by substituting to found in the previous subsection into the following equations Vi (1 − cos ωm to ) ≈ 0 ωm L Vi x˙ 1 (to ) = Iref ωm cos ωm to − sin ωm to . L x1 (to ) = Iref sin ωm to −

(7.33) (7.34)

Hence, u¯eq (t) during the transient response can be obtained as u¯eq

µ ¶ µ ¶ diL 1 diref 1 vi − L = vi − L + Lx˙ 1 = vo dt vo dt 1 (Vi sin ωm t − ωm LIref cos ωm t + Lx˙ 1 (t)) , ≈ Vo,ref

(7.35) (7.36)

where Vo,ref is the reference output voltage. The time varying function u¯eq can be used to verify that the trajectory is staying on the sliding surface by ensuring that 0 < u¯eq (t) < 1. In most circumstances, the current error initiated by the transient response is very small compared to the current signal and the resulting duty cycle usually stays within the above constraints. For illustration, Fig. 7.4 shows the waveforms of x˙ 1 and u¯eq just after the saturation of the duty cycle.


142

200

0.6

100

0.5 t

o

0

.

0.4

s]/ -100 [A

. x

1

0.3

q e

u

x1 -200

ueq

0.2

-300

0.1

-400

0

-500

-0.1

0

0.1

0.2 0.3 Time [ms]

0.4

0.5

(a)

to 0

0.1

0.2 0.3 Time [ms]

0.4

0.5

(b)

Figure 7.4: Calculated transient waveforms of (a) x˙ 1 and (b) u¯eq just after the saturation of duty cycle.

7.5 Practical Implementation 7.5.1 Modulation methods The resulting current control rule in (7.18) is readily implemented as a dedicated current control circuitry using discrete components, as demonstrated in Chapter 5. Alternatively, it can be implemented as an add-on feedforward control applied to standard PFC PWM controllers. In general, there are two different modulation methods adopted by PWM controllers, namely the leading edge modulation (LEM) and the trailing edge modulation (TEM). For brevity of presentation, we refer to the controller adopting LEM as the “LEM controller” and to that adopting TEM as the “TEM controller”. The control equations are slightly different between implementations using these two types of controllers. In the following subsections, we will describe the operation of TEM and LEM, and discuss the feedforward implementations of the derived control using TEM controllers and LEM controllers.

7.5.2 Trailing edge modulation Trailing edge modulation (TEM) is the conventional modulation method adopted by general PWM controllers. TEM is characterized by its resulting duty cycle determined


143

by a controlled on-time. Fig. 7.5(a) illustrates the operation of TEM. At the beginning of the switching cycle, the PWM output signal vgs becomes high when the ramping signal vramp starts to rise from zero or a low voltage level, which commences the ontime constantly at the beginning of each switching cycle. As vramp continues to rise and exceeds the control voltage vic , vgs becomes zero, and at that instant, the off-time of the duty cycle begins. In consequence, the higher the vic , the larger the duty cycle. In other words, the duty cycle d is directly proportional to the level of vic . To comply with the logic of the TEM operation, an inverting-input configuration is adopted by the current amplifier, so that a larger negative current error produces a higher voltage at the amplifier’s output, and hence, results in larger duty cycles. TEM has the advantage of simple implementation comparing to LEM. Since the PWM output can be easily disabled by pulling the control signal to ground, it allows simple implementation of protection functions. Moreover, it does not exhibit initial condition problem during startup, which occurs in converters under LEM and will be discussed in the next subsection.

7.5.3

Leading edge modulation

Leading edge modulation (LEM) is a new modulation method and can be found in some modern PFC controllers. It operates in the inverse logic of TEM. LEM is characterized by the resulting duty cycle determined by a controlled off-time. Fig. 7.5(b) illustrates the operation of LEM. At the beginning of the switching cycle, the PWM output signal vgs becomes low when the ramping signal vramp starts to rise from zero or a low voltage level, which commences the off-time constantly at the beginning of each switching cycle. As vramp continues to rise and exceeds the control voltage vic , vgs becomes high, and at that instant, the on-time of the duty cycle begins. In consequence, the lower the vic , the larger the duty cycle. In other words, the inverse-duty cycle 1 − d is directly proportional to the level of vic . To comply with the inverse logic of the LEM operation, the current amplifier needs to adopt a non-inverting-input configuration, so that a larger negative current error produces a lower amplifier’s output, hence results in larger duty cycles. LEM offers several advantages over TEM for PFC applications. First, it can reduce the ripple current flowing into the storage capacitor under proper synchronization with the downstream converter [119], thus less expensive capacitor can be used. Second, it exhibits lower input current distortion under high operating

144


vramp

vic

Vm t

vgs

t dTs

(1-d)T

s

(a) TEM

vramp

vic

Vm t

vgs

t (1-d)Ts

dTs (b) LEM

Figure 7.5: Illustrations of the control signal vic and the PWM output vgs in (a) TEM scheme and (b) LEM scheme. line frequency [64]. Third, the inverse logic improves the noise-immunity of the modulator against high frequency switching noise. However, the inverse logic of LEM also makes it suffer from large inrush current and high output voltage overshoot during initial startup condition, which necessitates the use of extra protection circuitries [132]. It also complicates the implementations of protection functions such as soft-start and duty cycle limit.

7.5.4 Implementation using TEM controllers In order to implement the derived current control rule as feedfoward control scheme applied to the standard PFC controller, the control rule equation needs to be scaled according to the parameters of the controller circuit. Here we adopt a standard TEM


145

controller UC3854 [21] as an illustrating example. The derivation of the control equation for the feedfoward implementation is shown step-by-step as follows. Step 1. The equivalent control using with TEM is defined as ueq = 1 − u¯eq . Using (7.18), ueq is given by 1 ueq = 1 − vo

µ

Ldiref − + vi − LK1 x1 − LK2 x2 dt

¶ (7.37)

Step 2. According to the controller circuit, the current variables iL and iref in (7.37) are replaced by the sensed voltage Rs iL and Ril imo respectively, where imo is the reference current generated by the multiplier and Ril is the resistor the current imo passing through. Step 3. The output voltage vo is approximated by the constant reference output voltage, Vo,ref . Thus, the equivalent control in (7.14) is modified as · LRil dimo 1 0 − + Rs vi − LK1 (Ril imo − Rs iL ) ueq = 1 − Vo,ref Rs dt ¸ Z −LK2 (Ril imo − Rs iL )dt . (7.38) Step 4. The control voltage vic is the control signal fed into TEM modulator. It can be formulated by scaling (7.38) with the amplitude of the ramping function Vm . Vm LRil dimo Vm Vm vi + + LK1 (Ril imo − Rs iL ) Vo,ref Vo,ref Rs dt Vo,ref Rs Z Vm (Ril imo − Rs iL )dt (7.39) +LK2 Vo,ref Rs

vic = Vm −

Step 5. On the other hand, the current amplifier’s output of a TEM controller can be represented by vca = (Ril imo − Rs iL )(1 + Hca ) ≈ (Ril imo − Rs iL )Hca

(7.40)

under the assumption of Hca À 1, where Hca is the transfer function of the current amplifier’s compensation. Transfer function Hca can be expressed in the Laplace domain as Hca =

1 + Riz Ciz s 1 . Ril (Ciz + Cip ) s [1 + Riz (Cip //Ciz )s]

(7.41)

146

7. Re-Visit of Robust Current Control From a Sliding Mode Viewpoint where Riz , Ril , Ciz and Cip are the compensation components shown in Fig. 7.7. Considering in most practical cases, Ciz À Cip and the resulting pole frequency is usually much higher than the zero frequency, Hca can thus be simplified as Hca =

1 Riz + . Ril Ril Ciz s

(7.42)

Step 6. As a result, the control equation for implementing the derived current loop control using the TEM PFC controller is vic = Vm − G1 vi + G2 Ril where G1 =

dimo + vca dt

Vm L Vm ; G2 = . Vo,ref Vo,ref Rs

(7.43)

(7.44)

Step 7. The SM coefficients are associated with the component values by K1 = where β3 =

Rs Riz Rs ; K2 = , Ril Lβ3 Ril Ciz Lβ3

(7.45)

Vm . Vo,ref

The feedforward implementation scheme using the TEM controller is illustrated in Fig. 7.6(a), and the simplified schematic of the implementation circuit adopting the TEM controller UC3854 is shown in Fig. 7.7, with the key parameters listed in Table 7.1.

7.5.5 Implementation using LEM controllers The implementation of the current control rule as add-on feedfoward control schemes using LEM controllers are slightly different from that using TEM controllers. Here we adopt a LEM controller UCC3817 [133] as an illustrating example. Since it is the inverse of the duty cycle that is being modulated in LEM, the inverse equivalent control (7.18) derived in Section 7.3 is readily applied for scaling. The rest of the derivation procedures are shown step-by-step as follows. Step 1. In a likewise manner, variables iL and iref in (7.18) are replaced by Rs iL and Ril imo respectively. Also, vo is approximated by Vo,ref . The inverse equivalent


147 vca

vgs

M W P

Vm

vic

G1

vi

d dt

G2

i

moRil

Vm vo Vref

vramp (a) TEM

vgs

M W P

vca

vic

G1 G2

vi

d dt

i

moRil

Vm vo Vref

vramp (b) LEM

Figure 7.6: Feedforward implementation of the derived current control using (a) TEM controllers and (b) LEM controllers. control in (7.18) becomes u¯0eq

· LRil dimo − + Rs vi − LK1 (Ril imo − Rs iL ) = Vo,ref Rs dt ¸ Z −LK2 (Ril imo − Rs iL )dt 1

(7.46)

Step 2. The control voltage vic fed into the LEM modulator is formulated by scaling (7.46) with Vm , which gives vic =

Vm LRil dimo Vm Vm vi − − LK1 (Ril imo − Rs iL ) Vo,ref Vo,ref Rs dt Vo,ref Rs Z Vm (Ril imo − Rs iL )dt. (7.47) −LK2 Vo,ref Rs

Step 3. On the other hand, the output of the current amplifier in the LEM controller can be represented by vca = (Rs iL − Ril imo )Hca ,

(7.48)


148

where Hca is the transfer function of the current amplifier’s compensation, which has the same expression as that in the TEM controller given in (7.41) with Riz , Ril , Ciz and Cip being the compensation components shown in Fig. 7.8. Step 4. As a result, the control rule equation for implementing the derived current loop control using the LEM PFC controller is vic = G1 vi − G2 Ril

dimo + vca , dt

(7.49)

The feedforward implementation scheme using the LEM controller is illustrated in Fig. 7.6(b), and the simplified schematic of the implementation circuit adopting the LEM controller UCC3817 is shown in Fig. 7.8, with the key parameters listed in Table 7.1. Table 7.1: Nominal conditions and circuit parameters in the simulation Parameters of PFC stage

Values


110 V


500 Hz

Reference output voltage Vo,ref

270 V

Switching frequency fs

100 kHz

Inductance L

1 mH


100 µF


1.2 kΩ


149

L

18V 1 2 3 4 5 6 7

Vff

vi

14 13 43 12 7D11 A10 9 8

500 Hz 110 Vrms Vff2

0.01 F

vi 18V

1 0 k

Vff2

14 13 43 12 7D11 A10 9 8

1 2 3 4 5 6 7

LM318

2M vea

Rmo

viref

0.25 3 .9 R k

3 .9 k

47 k

0.1 F

MC34152

LM318

Riz

8

2 2 .5 k

2 2 k

Vff

1 F

4 .7 F

2

10

7 6 0 p F

14

2 .7 n F

9 7

13 12

1 F

1 5 k

Vref vea

7 0 n F

1 2 0 k

1 11

1 0 k

5 1 0 k

V Standard PFC controller circuit v cc

O

vgs

-V

10 k

m

270 pF 100

100 nF

viref

LM318

50 1k 100p nF

1k Ref. current differentiator 10 k 10 k v LM318 ca

vO

10 k

5 1 0 k

10 k

1 0 k

10 k

External Clock

3

UC3854A

Vm

1 n F

560 pF

1 0 k

Ciz

4

10 k Summing amp. 200 200

VNL2222

IRF840

k 2 .1

R

100 F

Cip 270 pF

5 15 6

10 k 10 k 10 k 10 k

10 k

C

SW

0.9 nF 16.7 k

il

Comparator and driver LM318

APT15060B

vca

cc

620 k

vo

1.8 k

18V V

vi

-18V4 7 0 Ref. current generator k

vramp vic

vgs

Rs

-18V

510 k

D

1 mH

LM318 8 V 4.5 V

50 k Variable ramp generator

1k Current amp. output buffer 100 LM318

Input voltage buffer

vi

5 1 0 k 1 0 k

Figure 7.7: Simplifed schematic for the feedforward implementation of the derived control using the TEM PFC controller UC3854.


150

L 1 mH

500 Hz 110 Vrms

0.01 F

vi

R

V

0.25 3 .9 Ril k

18V

V v

1 2 3 4 5 6 7

ff

ff

ff

R

2

1 2 3 4 5 6 7

LM318 2M

v

ea

Ref. current generator

v

ramp

v

ic

LM318

-18V

1 0 k

10

V

MC34152

6 20 k

LM318

10 k 10 k 10 k

3 0 k

v

i

10 k

2 .2 F

V0 .0 1 F

13 12 ff

7

1 1 .3 k

v

1 2 0 k

1 11

1 0 k

ea

7 0 nF

5 10 k

v

O

270 pF 100

100 nF

v

LM318

50 1k 100p nF

v5 10 k

1O 0 k

10 k

1 0 k

LM318

8 V 4.5 V External 50 k Clock Variable ramp generator

9

ref

gs

10 k

1 n F

2

V

2. 7 nF

Standard PFC controller circuit

10 k Summing amp. 200 200

VNL2222

4. 7 F

iz

270 pF 3

8

6

Comparator and driver 10 k

560 pF

1 0 k

ca

UCC3817

ref

v

C

iz

5

4

iref

v

0.9 nF 16.7 k

15

v

k 2. 1

R

100 F

IRF840 1.8 k

ip

14 13 43 12 7 11 D A10 9 8

C

SW

s

R C

18V

1 0 k

2

mo

3 .9 k

vo

APT15060B

vgs

18V

-18V

510 k

i

V

14 13 43 12 7 11 D A10 9 8

D

iref

1k Ref. current differentiator 10 k vca 10 k LM318 1k Current amp. output buffer 10 k

5 10 k

1k

1 0 k

v

10 k

LM318 Input voltage buffer

i

Figure 7.8: Simplifed schematic for the feedforward implementation of the derived control using the LEM PFC controller UCC3817.


7.6

151

Simulation Results

Based on the afore-mentioned schematics shown in Figs. 7.7 and 7.8, WinSPICE simulation models of the two implementation circuits are constructed. Figs. 7.9 and 7.10 show some selected waveforms of the two models under the nominal condition stated in Table 7.1. The averaged output voltages of both models are regulated at 270 V and both the inductor currents follow the rectified sinusoidal profile of the input voltage. This shows that both the converter models operate properly under the feedforward implementation schemes.

1.2

280



1 0.8 0.6 0.4 0.2

275

270

265

0 -0.2

260 20

20.5

21

21.5

22

20

20.5

Time [ms]

21

21.5

22

Time [ms]

(a) iL

(b) vo

Figure 7.9: Simulated waveforms of (a) inductor current and (b) output voltage of the converter model with feedforward implementation using the TEM controller. 1.2

280



1 0.8 0.6 0.4 0.2

275

270

265

0 -0.2

260 20

20.5

21

Time [ms]

(a) iL

21.5

22

20

20.5

21

21.5

22

Time [ms]

(b) vo

Figure 7.10: Simulated waveforms of (a) inductor current and (b) output voltage of the converter model with feedforward implementation using the LEM controller.

152


Next, the converter models under the feedforward schemes are compared with that under the original ACM control implemented by the same controller IC in terms of input current distortion. The simulated inductor current under the feedforward implementation using the controller UC3854 is depicted along with that under the original ACM control in Fig. 7.11. Also, the comparison between models using the controller UCC3817 is shown in Fig. 7.12. Upon comparison of the inductor current waveforms, improved zero-crossing distortion can be observed in both models with feedforward implementation under the conditions of high line frequency, high input voltage and low output power. Further, considering the two conventional ACM control models, it is noticed that the one using the LEM controller generally results in less-distorted input current than that using the TEM controller. This verifies the advantage of reduced current distortion offered by LEM in simple ACM control. However, with the application of the feedforward schemes, the effect of modulation method on current distortion is insignificant and similar inductor current waveforms are produced by the two models. These results have confirmed the capability of the derived control rule and the effectiveness of the implementation schemes, which are shown to be independent of the modulation method adopted.

153

1.2

1.2

1

1




0.8 0.6 0.4 0.2 0

0.8 0.6 0.4 0.2 0

-0.2

-0.2 20

20.25

20.5

20.75

21

21.25

20

20.25

Time [ms]

21

21.25

(b)

1

1

0.8

0.8



20.75

Time [ms]

(a)

0.6

0.4

0.2

0

0.6

0.4

0.2

0

-0.2

-0.2 20

20.5

21

21.5

22

20

20.5

Time [ms]

21

21.5

22

21.5

22

Time [ms]

(c)

(d)

1

1

0.8

0.8



20.5

0.6

0.4

0.2

0

0.6

0.4

0.2

0

-0.2

-0.2 20

20.5

21

21.5

22

Time [ms]

(e)

20

20.5

21

Time [ms]

(f)

Figure 7.11: Comparison of the simulated inductor current waveforms between converter models with ACM control (left column) and the feedfoward implementation of the derived control rule (right column) under various operating conditions: (a)(b) line frequency of 800 Hz; (c)(d) input voltage of 130 V; (e)(f) output power of 50 W. Both the models adopt the TEM controller UC3854.


1.2

1.2

1

1



154

0.8 0.6 0.4 0.2 0

0.8 0.6 0.4 0.2 0

-0.2

-0.2 20

20.25

20.5

20.75

21

21.25

20

20.25

Time [ms]

21

21.25

(b)

1

1

0.8

0.8



20.75

Time [ms]

(a)

0.6

0.4

0.2

0

0.6

0.4

0.2

0

-0.2

-0.2 20

20.5

21

21.5

22

20

20.5

Time [ms]

21

21.5

22

21.5

22

Time [ms]

(c)

(d)

1

1

0.8

0.8



20.5

0.6

0.4

0.2

0

0.6

0.4

0.2

0

-0.2

-0.2 20

20.5

21

21.5

22

Time [ms]

(e)

20

20.5

21

Time [ms]

(f)

Figure 7.12: Comparison of simulated inductor current waveforms between converter models with ACM control (left column) and the feedfoward implementation of the derived control rule (right column) under various operating conditions: (a)(b) line frequency of 800 Hz; (c)(d) input voltage of 130 V; (e)(f) output power of 50 W. Both the models adopt the LEM controller UCC3817.

7.7 Discussion

155

Further, the current tracking performances of the two converter models with feedforward implementation are evaluated over a range of operating conditions. Figs. 7.13 and 7.14 show the simulated inductor current waveforms under extreme conditions of operating line frequency, input voltage and output power. The low current distortion shown in the simulated waveforms indicates that both converter models achieve consistent current tracking performance with various operating conditions. The results have verified the robustness of the derived current control implemented by the feedforward control schemes using TEM and LEM PFC controllers.

7.7 Discussion Our re-examination of the current control rule implies that the SM-based derivation approach can just be one of the many possible approaches to arrive at the same robust control rule. However, we believe that it is worthwhile and important to consider a proper exposition of the control derivation under the SM framework, for the reasons mentioned in Section 7.1. Further, it is intuitive to compare the SM-based approach with other derivation approaches. A comparison between the SM-based derivation approach and the feedback linearization approach introduced in Chapters 5 and 6 reveals that the two approaches share the following common characteristics: 1. The sliding surface equation is similar to the linearized dynamical equation, both providing full pictures of the behaviors of the closed-loop system. 2. Robust control solutions can be generated by mathematically manipulating the sliding surface equation or the linearized dynamical equation. 3. The nonlinearity and the dependence of the closed-loop dynamics on input disturbances are removed by the use of the derived control rule, which results in robust control performance. These characteristics point out that a SM control-derived system can be regarded as a closed-loop system with its dynamics linearized. Its robustness is the straightforward result of the linearized dynamics and is independent of the modulation method adopted. This is reflected by the association of sliding mode control with feedback linearization in the literature [134], [135], [126].

156


7.8 Conclusion In this chapter, we have re-visited the robust current control rule for the boost PFC converter under the framework of sliding mode control. By manipulating the sliding surface equation, the stability and performance of the system can be assessed, and based on that the control parameters can be designed in conjunction with the existence condition. The derived control is readily implemented as add-on feedforward control schemes using either the TEM PFC controller or the LEM PFC controller. The performances of the implementation circuits using these two types of PFC controllers have been evaluated by simulation. The simulation results have confirmed that the derived current control, in the form of add-on feedforward implementation, is capable of eliminating input current distortion and maintaining consistent performance under various operating conditions. Further, the current tracking performance is shown to be independent of the modulation method adopted. Hence, the capability of the derived control and the effectiveness of the implementation schemes are verified.

157

1.2

1.2

1

1



7.8 Conclusion

0.8 0.6 0.4 0.2 0

0.8 0.6 0.4 0.2 0

-0.2

-0.2 20

20.5

21

21.5

22

22.5

23

23.5

20

20.25

Time [ms]

20.75

21

21.25

Time [ms]

(a)

(b)

1.4

1

1.2

0.8

1



20.5

0.8 0.6 0.4 0.2

0.6

0.4

0.2

0

0 -0.2

-0.2 20

20.5

21

21.5

22

20

20.5

Time [ms]

21

21.5

22

21.5

22

Time [ms]

(c)

(d)

2

1

0.8



1.5

1

0.5

0.6

0.4

0.2

0 0 -0.2 20

20.5

21

Time [ms]

(e)

21.5

22

20

20.5

21

Time [ms]

(f)

Figure 7.13: Simulated inductor current of the converter model with feedforward implementation of the derived control using the TEM controller UC3854 under various operating conditions: line frequency of (a) 300 Hz and (b) 800 Hz; input voltage of (c) 80 V and (d) 130 V; output power of (e) 120 W and (f) 50 W.


1.2

1.2

1

1



158

0.8 0.6 0.4 0.2 0

0.8 0.6 0.4 0.2 0

-0.2

-0.2 20

20.5

21

21.5

22

22.5

23

23.5

20

20.25

Time [ms]

20.75

21

21.25

Time [ms]

(a)

(b)

1.4

1

1.2

0.8

1



20.5

0.8 0.6 0.4 0.2

0.6

0.4

0.2

0

0 -0.2

-0.2 20

20.5

21

21.5

22

20

20.5

Time [ms]

21

21.5

22

21.5

22

Time [ms]

(c)

(d)

2

1

0.8



1.5

1

0.5

0.6

0.4

0.2

0 0 -0.2 20

20.5

21

Time [ms]

(e)

21.5

22

20

20.5

21

Time [ms]

(f)

Figure 7.14: Simulated inductor current of the converter model with feedforward implementation of the derived control using the LEM controller UCC3817 under various operating conditions: line frequency of (a) 300 Hz and (b) 800 Hz; input voltage of (c) 80 V and (d) 130 V; output power of (e) 120 W and (f) 50 W.

Chapter 8 Conclusion This chapter summarizes the tasks that have been completed in this project. Also, possible extensions and potential areas for future research will be given. Finally, this thesis will be concluded with a summary of its contributions.

8.1 Work Accomplished Fig. 8.1 shows an overview of the work completed in this project. Summaries of the specific completed tasks are given in the following subsections.

8.1.1 Investigation of line-frequency instability in boost PFC converters The low-frequency instability in the boost PFC power supply has been studied in the light of sustained oscillation at the line frequency. By modeling the downstream dc-dc converter as a constant power sink, the analysis of the two-stage PFC power supply is simplified. Using this simplified model, the closed-form loop gain has been derived using the double averaging approach. Stability information has been captured in terms of a closed-loop stability condition, which has been visualized graphically in terms of stability boundaries in various parameter spaces. Stable regions and unstable regions have been identified and compared with those given by the resistor terminated model. Both the analytical and experimental results have shown that the two-stage PFC power 159

8. Conclusion

160

Design of Control for Boost PFC converters Performance improvement

Low-frequency stability constant current sink terminated Stability analysis Stability criterion and boundaries Comparison Stability boundaries with Rload termination

inner current loop

Outer voltage loop

Robust control derivation

Robust control derivation

Two-stage PFC power supplies Modeling with CPS Stability analysis Stability criterion and boundaries Design guideline

SM-based approach

Feedback linearization

Frequency response

Frequency response

Loop gain

Loop gain

existence condition Using LEM controller

Feedback linearization Transient response

Frequency response Loop gain

Transient waveforms

Analog implementation Custom-controller implementation

Using TEM controller

Figure 8.1: An overview of the completed research work.

supply has a more restricted stability region and is more prone to line-frequency instability. Furthermore, the resistor terminated PFC converter can be easily “stabilized” by increasing its power consumption, whereas the stability of the two-stage PFC power supply is independent of the output power. Further, the analysis has been extended to the boost PFC converter terminated with constant current sink, which is commonly adopted in design and testing processes. Following a similar approach, the loop gain and the stability conditions of the constant-current-sink terminated system have been derived. The stability conditions have been visualized as stability boundaries and compared with those given by the two-stage power supply. Both the analytical and simulation results have shown

8.1 Work Accomplished

161

that the constant-current-sink terminated system generally has a relatively larger stable region and can be “stabilized” by increasing its power consumption. If the resistive load terminated converter is also included for comparison, the constant-power-sink terminated converter gives the most consistent stability results when compared with the actual two-stage PFC power supply. The results given by the constant-current-sink terminated converter and the resistive load terminated converter are both over-optimistic. But the results given by the constant-current-sink terminated system is generally closer to that given by the two-stage system, and the difference between the two systems reduces with smaller output power.

8.1.2

Introduction of a unified approach to derive robust control for boost PFC converters

Apart from the line-frequency stability, the multi-loop control of the boost PFC converter has been examined in order to improve the converter’s performance in terms of input current tracking and output transient response. A unified approach for systematic derivation of robust control rules for the inner current loop and the outer voltage loop has been introduced. Using the method of feedback linearization, the approach eliminates the nonlinearity and the dependency of the error dynamics on the input disturbance. It leads to nonlinear control rules under which improved steady-state and transient response performances have been achieved. Moreover, as a result of the linearized dynamics, consistent performances have been maintained under the variations of operation condition. The control parameters can be designed according to frequency response analysis to ensure system stability and satisfactory steady-state performance. They can be further adjusted for the desired transient response waveforms. The derived control rules have been implemented using analog devices in a usual form of PWM control circuitry. The accuracy of the modeling of the closed-loop system and the capability of the derived control have been verified by experiments.

8. Conclusion

162

8.1.3 Re-examination of robust control from a sliding mode viewpoint As an alternative to the method of feedback linearization, we have re-examined the robust current control rule under the framework of sliding mode control. The stability and performance of the system have been assessed through manipulating the sliding surface equation, and based on that the control parameters have been designed in conjunction with the existence condition. The derived control rule has been implemented as add-on feedforward control applied to standard PFC controllers. The feedforward implementation circuits using the TEM controller and the LEM controller have been evaluated by simulation. The simulation results verified the effectiveness of the implementation schemes and the capability of the derived control in achieving low input current distortion as well as in maintaining consistent performance under various operating conditions.

8.2 Future Research Based on the knowledge and experience built up through the research project, some extensions and potential areas of further study are suggested. Following up the studies of line-frequency instability, some attempts can be made to further improve and simplify the double averaging method. Although the double averaging method has succeeded in capturing the stability information of the boost PFC converters, the mathematical manipulation is complex and tedious. Moreover, the current approach has some limitations imposed by the presence of square root in the resulting loop gain equation. Under certain extreme conditions, such as heavy loading condition, complex loop gain results and the stability of the converter cannot be determined. It remains unknown whether the resulting complex loop gain has specific indication, or it is simply a mathematical error incurred during the manipulation process. Apart from the adoption of ACM control, the study of line frequency instability can also be extended to converters using other control methods, such as the borderline control. Borderline control is commonly adopted in PFC converters for low-power applications. As a preliminary study, we have observed similar instability phenomenon

8.3 Contributions of the Thesis

163

through simulation. An in-depth analytical study can be pursued in the future, such that analytical stability criteria can be obtained, which can further enhance our understanding of the effects of various control methods on the stability condition and facilitate design processes of low-power PFC applications. In the research of robust control derivation, we have used the method of feedback linearization to impose a desired linear dynamics to the closed loop system. This inspires the idea that a desirable nonlinear dynamics can also be imposed to the closedloop system using a similar approach, which may lead to the creation of adaptive control rules that can automatically adjust the control parameters corresponding to the changes in operating conditions and other input disturbances. Furthermore, the feedback linearization approach and the SM-based appraoch are general approaches for the derivation of robust control solutions and their applications are not limited to boost PFC converters. In fact, the approaches can be extended to any converter topologies with the open-loop dynamics being known. A potential application is the generation of robust control for more complex converter topologies which are too complicated to be designed and analyzed using conventional approaches, such ´ converter and resonant converters. as the Cuk

8.3 Contributions of the Thesis As mentioned in the beginning of the thesis, the control of power converters is designed to address two major specifications, which are stability and performance. In this thesis, through the studies of the line-frequency instability and the generation of robust control solutions presented in the previous chapters, comprehensive guidelines are provided for designing the control of the boost PFC converter for meeting these two requirements. Specifically, the contributions of the thesis are as follows: 1. The study of the line-frequency instability has addressed the issue of inconsistent results of stability condition in the two-stage PFC power supply. A simple yet effective modeling solution has been introduced, which gives accurate results about the stability of the two-stage system. 2. The presented analysis and results have enhanced the understanding about the instability phenomenon. Stability criteria have been derived not only for the two-

8. Conclusion

164

stage system, but also for the PFC boost pre-regulator terminated with constant current sink. The criteria are visualized as stability boundaries, which depict the stability conditions of the converter under the effects of variation of different parameters and facilitate comparison among converters with different kinds of load termination. The stability boundaries also serve as guidelines for performance trade-offs for stability improvement. 3. This thesis has introduced the unified approach to generate robust control solutions for boost PFC converters using feedback linearization. The resulting controls lead to improved steady state and transient response performance. The robustness of the derived control is reflected by the consistent performance maintained under various operating conditions. 4. Also, this thesis has presented the design of the control parameters based on frequency response analysis and transient response waveforms, which addresses the basic requirement of stability and performance specifications. The introduced methodologies enable engineers to generate and design nonlinear robust control solutions systematically instead of relying on spontaneous ad-hoc approaches and trial-and-error methods. 5. Though the re-examination of the current control rule from the sliding mode viewpoint, the thesis has presented an exposition of the generation and design of robust control from diverse perspectives. The comparison between the SMbased approach and the feedback linearization approach has also led to clear understanding about the relationship between the two approaches. 6. This thesis has detailed different analog implementations of the derived control solutions. Implementation calculations, circuit schematics, simulation and experimental results have been presented, which serve as useful references for practicing engineers to readily apply the derivation approaches and the resulting control solutions. Overall, this thesis has made contributions to the systematic design of control solutions for boost PFC converters by introducing improved derivation and design methodologies, and providing practical guidelines and useful reference to facilitate the design process. The presented techniques are readily applied to the construction of high-

8.3 Contributions of the Thesis

165

performance PFC converters that achieve outstanding and robust performance with guaranteed stability.

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Modeling and Design of Power-Factor-Correction

Modeling and Design of Power-Factor-Correction

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