Monolithic Integration of Si3N4 Microring Filters With Bulk CMOS IC ...

IEEE PHOTONICS TECHNOLOGY LETTERS, VOL. 27, NO. 14, JULY 15, 2015

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Monolithic Integration of Si3N4 Microring Filters With Bulk CMOS IC Through Post-Backend Process Zan Zhang, Beiju Huang, Xu Zhang, Zanyun Zhang, Chuantong Cheng, Xurui Mao, Sijie Liu, and Hongda Chen, Member, IEEE

Abstract— An experimental demonstration of backend monolithic integration of Si3 N4 microring filter with bulk complementary metal–oxide–semiconductor (CMOS) integrated circuit (IC) is accomplished using CMOS postbackend process. Si3 N4 photonic layer is integrated on the top surface of CMOS IC die which is manufactured in commercial CMOS foundry. The Si3 N4 microring filters in photonic layer are fabricated using CMOS postbackend process with only two additional lithography steps. The filters can be thermally tuned by microheaters integrated in CMOS circuits, which are controlled by transmission gates. A measured optical transmission spectrum and a dynamic characteristic of the integrated filter are provided. Index Terms— Integrated optoelectronics, CMOS technology, silicon photonics, silicon nitride.

I. I NTRODUCTION S DATA rate increases, electrical interconnects suffer from serious problems such as high crosstalk, increased signal latency and attenuation. Optical interconnects based on silicon photonics have been suggested as a prospective solution [1]. The inherent feature of compatible with CMOS platform is a significant advantage of silicon photonics, which provides potentially low-cost solution for optical interconnects through volume production [2]. In the past few years, numerous high performance building blocks have been reported such as high speed modulator, Ge optical detector, optical switch and router, Mux/ Demux [3]–[6]. Performance of these reported blocks have already reached the requirement in bandwidth and power consumption of on-chip optical interconnects [7]. As silicon photonic devices keep developing, the method of integrating silicon photonic devices within state-of-art microelectronic manufacturing platform becomes the main issue for optoelectronic convergence. Silicon based monolithic integrated optoelectronic circuits for on-chip optical interconnects

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Manuscript received March 9, 2015; revised April 9, 2015; accepted May 3, 2015. Date of publication May 5, 2015; date of current version June 24, 2015. This work was supported in part by the National HighTech Research and Development Program of China (863 Program) under Grant 2013AA013602, Grant 2013AA031903, and Grant 2013AA032204, in part by the National Natural Science Foundation of China under Grant 61036002, Grant 61178051, Grant 61321063, and Grant 61335010, and in part by the National Basic Research Program of China under Grant 2011CB933203 and Grant 2011CBA00608. The authors are with the State Key Laboratory of Integrated Optoelectronics, Institute of Semiconductors, Chinese Academy of Sciences, Beijing 100083, China (e-mail: [email protected]; [email protected]; [email protected]; [email protected]; chengchuantong@semi. ac.cn; [email protected]; [email protected]; [email protected]). Color versions of one or more of the figures in this letter are available online at http://ieeexplore.ieee.org. Digital Object Identifier 10.1109/LPT.2015.2429677

have been demonstrated using commercial standard CMOS technology [8]. But, without modification of the technology, performance of the circuits hardly fulfill the requirement in bandwidth and power consumption. So, two main approaches have been proposed to achieve monolithic optoelectronic integration. Both of them need some modification or adding extra process into standard CMOS technology. The first approach is to integrate silicon photonic devices within the CMOS frontend steps. Several impressive works have been reported [4], [9], [10]. To obtain sufficient optical isolation and ensure low propagation loss of the waveguide, modified SOI wafer with thicker BOX is required to manufacture silicon photonic devices, which results in higher thermal impedance and leads to performance degradation of ICs. What’s more, the much bigger footprints of photonic devices occupy valuable transistor real estate leading to higher product cost. The second approach is called backend integration which introduces new layers in CMOS backend steps to manufacture photonic devices [11]–[14]. Although the additional process steps will potentially increase the cost, there is no modification in critical CMOS frontend steps and the process temperature in backend approach is under 450 °C, which will bring no influence to CMOS ICs. More importantly, with the inherent multi-layer characteristic, 3-D integration of photonics and electronics could be achieved through backend approach, leading to high integration density and low cost [13]. In this letter, based on the backend integration method, we present an experimental demonstration of backend monolithic integration of Si3 N4 microring filters on bulk CMOS IC die. No modifications are introduced into the critical frontend steps. The filters can be thermally tuned by integrated micro-heaters controlled by circuits in CMOS IC die which is manufactured in commercial foundry. To the best of our knowledge, this is the first experimental demonstration of monolithic integration of Si3 N4 microring filter with bulk CMOS integrated circuits utilizing post-backend process. II. C ONFIGURATION AND FABRICATION A. Chip Configuration The 3-D schematic of proposed backend monolithically integrated Si3 N4 filter is shown in Fig. 1(a). The backend of CMOS is composed of multiple layers of metal and dielectric to connect electric devices manufactured in frontend. We add a Si3 N4 photonic layer on the top surface of CMOS ICs by means of post-backend fabrication process. The proposed chip

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IEEE PHOTONICS TECHNOLOGY LETTERS, VOL. 27, NO. 14, JULY 15, 2015

Fig. 1. (a) Structure and (b) schematic diagram of the proposed backend monolithic integrated Si3 N4 filter.

is composed of CMOS ICs, deposited SiO2 layer, and Si3 N4 photonic layer. The IC die manufactured in commercial CMOS foundry acts as substrate of the whole chip. The SiO2 layer above IC die here provides sufficient optical isolation, and the thickness is typically on the order of few microns. The photonic layer contains Si3 N4 microring filters with additional dielectric layer on top protecting the devices. Micro-heaters are integrated in the IC die and connecting with control circuits consist of transmission gates, as depicted in Fig. 1(b). The micro-heaters are composed of parallel connected poly-silicon resistors with a total resistance of 160 . The monolithic integrated microring filters can be thermally tuned by applying a control signal on the transmission gates to adjust the current flow through poly-silicon resistors. B. Fabrication Flow Since the Si3 N4 photonic layer is directly fabricated on top surface of CMOS backend, the fabrication process of photonic layer needs to satisfy a strict thermal limit to avoid performance degradation of CMOS ICs [14]. This is mainly because that Al metallization degrades at a temperature as low as 450 °C [15]. Therefore, the temperature of CMOS postbackend process have to be controlled strictly below 450 °C. Fortunately, The process steps used in CMOS backend such as plasma-enhanced chemical vapor deposition (PECVD), photolithography, inductively coupled plasma (ICP) etch and chemical mechanical polishing (CMP) satisfy this strict thermal limit, and of course maintain fully compatible with standard CMOS technology. Compared to amorphous Silicon and poly-silicon which could also be deposited by PECVD technology under low temperature, Si3 N4 waveguide is able to achieve much lower propagation loss [16]. Moreover, Si3 N4 is the material used in passivation layer in CMOS backend, which results in fewer modifications of standard CMOS technology. The process flow of our backend monolithically integrated Si3 N4 microring filter is illustrated in Fig. 2. Firstly, the isolation SiO2 layer is deposited on the top surface of CMOS IC die, followed by planarization of the SiO2 layer using CMP. The isolation layer need to be sufficient thick to preventing light coupling into Si substrate. Then, Si3 N4 is deposited and waveguide structures including microring resonators and focusing grating couplers are patterned through electron beam lithography (EBL) and ICP to form photonic layer. EBL is used here to pattern waveguide devices because we are lack of access to deep UV lithography technology. But actually,

Fig. 2. Process flow of backend monolithically integrated Si3 N4 microring filter using post-backend integration method.

Fig. 3. Microscope photo of the CSMC commercial 1 μm CMOS IC die (a) before and (b) after photonic layer fabrication, the micro-heater and control circuit are marked with blue dash line, the microring filter is marked with red dash line.

state-of-the-art commercial CMOS technology is fully capable to deal with linewidth as small as 300 nm. After patterning waveguide devices, upper SiO2 cladding is deposited and bonding pad windows are defined by one more photolithography step and ICP etch. All the dielectric layers are deposited through PECVD with process temperature of 300 °C. The photonic devices fabricated by this CMOS post-backend process require just two additional lithography steps, which keeps the cost low. III. E XPERIMENT R ESULT In our demonstrated chip, the CMOS IC die was manufactured in the CSMC commercial 1-μm CMOS line. Microheaters and control circuits in the IC die were used to adjust optical characteristic of Si3 N4 microring filters. Microscope photos of the IC die before and after photonic layer fabrication are showed in Figure 3. Heaters and control circuits are depicted in dash line in Fig. 3(a). Above the circuits, Si3N4 microring filters and focusing grating couplers depicted in dash line can be clearly seen in Fig. 3(b) with CMOS circuits slightly defocussed. Cross-section of the chip was observed by SEM as shown in Fig. 4. Si3 N4 waveguide and metal interconnects of the CMOS ICs beneath photonic layer are clearly shown in the SEM images. Top metal and metal interconnects are shown in white dash line. Si3 N4 Photonic layer is shown in black dash line. Measured thickness of

ZHANG et al.: MONOLITHIC INTEGRATION OF Si3 N4 MICRORING FILTERS WITH BULK CMOS IC

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Fig. 4. SEM images of the cross-section of CMOS IC die with deposited SiO2 and Si3 N4 , the top metal and metal interconnects are clearly showed in the images.

Fig. 6. Normalized response spectra of the Si3 N4 microring filter with different voltage applied on Vdd pin.

Fig. 5. Measured coupling efficiency of focusing grating coupler before and after thermal tuning.

Si3 N4 layer are 409.8 nm and thickness of dielectric between photonic layer and top metal of CMOS IC die is 8.73 μm. The demonstrated filter is composed of a single microring resonator with double-side-coupled waveguides as shown in Fig. 3(b). Radius of the microring is 30 μm and crosssection of the waveguides is 400 nm ×1 μm which ensures single mode transmission in Si3 N4 waveguide. Focusing grating couplers with a fully etched configuration act as optical I/O to couple optical signal into and out of the chip. The measured coupling efficiency is -8 dB near 1545 nm as depicted in black line in Fig. 5. We measured the static characteristics of the filter by using an amplified spontaneous emission (ASE) broadband source. Optical power was fed into the chip by a polarization maintained (PM) single mode fiber with cleaved facet. At the output end, light was coupled into a PM single mode fiber which was connected to an optical spectrum analyzer (OSA). The normalized optical spectrum is shown as black line in Fig. 6, the extinction ratio of demonstrated filter is 8.2 dB and the −3 dB bandwidth is about 0.18 nm resulting in a loaded quality factor of ∼8600. By connecting control pin to high level (5 V) and changing the static voltage applied to the poly-resistor, we obtained the normalized transmission spectra response of the filter under different voltages, as depicted in Fig. 6. With a 5 V voltage applied on the Vdd pin, the resonant wavelength shifted more than 0.5 nm and total power consumption was about 113.1 mW as a result of low-tuning-efficiency caused by thick dielectric layer between Si3 N4 photonic layer and micro-heaters. As can be

Fig. 7. (a) Control signal and (b) time response of the backend monolithically integrated Si3 N4 microring filter.

seen in Fig. 6, the insertion loss of the filter is gradually increasing with the applied voltage increasing from 0 V to 5 V. As the refractive index change was quite small, the intrinsic coupling efficiency of the grating coupler should not be degraded significantly. So the increased insertion loss was caused by the expansion of the chip in the heating process [17]. After readjustment, the measured coupling curve was slightly red-shifted as shown in red line in Fig. 5. The dynamic response was characterized by using a tunable laser, a signal generator, an optical receiver and an oscilloscope. Signal light of 1552.53 nm was coupled into the filter through input grating coupler and the output light is coupled to a single mode fiber and then detected by optical receiver. We applied a square-wave voltage of 200 Hz with Vlow = 0 V, Vhigh = 5 V and a 50% duty cycle (as depicted in Fig. 7(a)) to the transmission gate to control the current flowing through micro-heater. The waveform of the output of optical receiver was displayed on the oscilloscope shown in Fig. 7(b). The result shows that the backend monolithically integrated

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IEEE PHOTONICS TECHNOLOGY LETTERS, VOL. 27, NO. 14, JULY 15, 2015

TABLE I C OMPARISONS OF D IFFERENT M ETHODS

ACKNOWLEDGMENT The authors would like to thank Dr. Zhang Lihui from Tsinghua-Foxconn Nanotechnology Research Center and Chang Chun from Institute of Semiconductors, CAS, for fabrication support. They would also like to thank anonymous reviewers for their helpful suggestions. R EFERENCES

microring filter well responses to the 200-Hz thermally tuning signal. The 10-90% rise and 90-10% fall time are 0.85 ms and 0.92 ms, respectively. As the rise and fall time of input signal is on the order of 10s of nanoseconds, the slow tuning speed is mainly caused by the rather thick dielectric layer between Si3 N4 photonic layer and poly-silicon resistors. Table I gives the comparison between our result and other published works on microring devices. Most of them shows better performance, but these works lack of the ability to integrate with CMOS IC monolithically. Although frontend monolithic integration of electronics and photonics is achieved in [4], the modified SOI CMOS technology is still required which may lead to high cost. Comparing to other works, we accomplished monolithic integration of photonic devices with ICs using CMOS post-backend process which brought no influence to ICs. Further improvement can be done to increasing tuning efficiency by reducing the thickness of dielectric layer between heaters and Si3 N4 photonic devices, or using metals in CMOS backend as heaters which are much closer to Si3 N4 photonic layer. IV. C ONCLUSION In conclusion, we have experimentally demonstrated backend monolithic integration of Si3 N4 microring filter with bulk silicon CMOS ICs using CMOS post-backend process. Only two additional lithography steps are required to fabricate optical filters on the top surface of IC die manufactured in commercial CMOS line. While no modification is made to the critical CMOS frontend process, the control circuit and microheater integrated in the IC die work well to achieve thermal tuning of the filter. Static and dynamic responses of the filter are characterized, and measured results shows the filter well response to the thermal tuning signal. The experiment result indicates that the CMOS post-backend integration approach has the potential to promote optoelectronic convergence.

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