The MERASA2 project is focused on the development of a multi-core ... and interconnects of embedded multi-core architectures, there is a need for timing ...
Multi-Core Architectures for Hard Real-Time Applications Mike Gerdes, Julian Wolf, Ji Zhang, Sascha Uhrig, Theo Ungerer1 ∗
Systems and Networking, University of Augsburg, Eichleitnerstr. 30, D-86159 Augsburg, Germany
ABSTRACT The MERASA2 project is focused on the development of a multi-core processor for hard real-time embedded systems. Hand in hand with the investigation of analyzable high-performance features and interconnects of embedded multi-core architectures, there is a need for timing analysis techniques and tools to guarantee the analyzability and predictability of the features provided by the processor. Main Objectives at University of Augsburg within the MERASA project are the definition and exploration of appropriate hardware architecture for a MERASA single-core and multicore processor. Under the scope of hard real-time execution a SystemC simulator is implemented and later transformed to VHDL for an FPGA board. The second basic part is the development of an adequate System Software as an abstraction layer between application software and embedded hardware to provides basic functions of a real-time operating system. KEYWORDS :
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Multi-Core; Hard Real-Time; WCET; SystemC Simulator; FPGA
Introduction
The overall objective of the MERASA project is to achieve a breakthrough in techniques for embedded multi-core processors, hard real-time support in system software for multicores, and WCET (worst case execution time) analysis tools, which will enable combining the requirements for high-performance, with time-predictable execution of single or multiple threads on a multi-core processor. As a result, we will achieve the societal benefits of increased safety and improved control of emissions into the environment in the areas of automotive, avionic and construction-machinery. Moreover, the main objectives of MERASA are to investigate the impact of using multicore processors on static and measurement-based WCET analysability, developing of WCET 1
E-mail: {gerdes, wolf, zhang, uhrig, ungerer}@informatik.uni-augsburg.de Multi-Core Execution of Hard Real-Time Applications Supporting Analysability, funded by the EU within the 7th Research Framework Program 2
Data Pipeline Address Pipeline
Schedule (1st Scheduling Layer)
Instruction Windows
Instruction Fetch
Thread Manager (2nd Scheduling Layer)
Figure 1: MERASA single-core. analysis techniques and tools, providing appropriate system-level software for the multicore MERASA processor and to verify the reached progress by pilot studies of industrial partners. Besides University of Augsburg, the other MERASA project partners are the Barcelona Supercomputing Center especially focused on definition and exploration of hardware architecture. Furthermore the Université Paul Sabatier in Toulouse for WCET tools and analysability together with Rapita Systems Ltd. Moreover, pilot studies are done by project partner Honeywell international s.r.o.
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Project work at University of Augsburg
At University of Augsburg the main objectives in the MERASA project will be the implementation of a MERASA single-core and later a MERASA multi-core as SystemC simulator and transformation to VHDL for an FPGA board under the scope of hard real-time execution as well as the develeopment of an appropriate System Software. In the following subsections, we will describe some of our main work in the MERASA project until the actual state of the project (first 8 months).
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Hardware design
At this point of project the MERASA single-core processor is implemented as a SystemC simulator. Fig. 1 shows a MERASA single-core based on the simultaneous multithreaded CarCore [KMUU06]. The MERASA single-core fetches 64-bit words which may contain serveral 16-bit as well as 32-bit long instructions. These may also overlap between those fetched 64-bit words. When dispatching the instructions to the instruction windows, the select step dispatches the instructions to the different slots, filling the pipelines and also decides, which instruction needs to be fetched for the next cycle. The MERASA core uses two different pipelines, an address pipeline and a data pipeline, which allows parallel execution under certain premises. If this parallel execution is not possible, the pipelines are filled with instructions of different threads. For hard real-time execution it is important to have a
Figure 2: Architecture of the MERASA system-level software. priority-based scheduling, so we can assure the execution of hard real-time threads ahead of other soft real-time or non real-time threads. Thus, if no hard real-time thread needs to be executed, or is waiting for a memory access, we can use the stall time to dispatch other non hard real-time threads. The MERASA processor will support measurement based WCET analysis tools. Application software can be instrumented via WCET analysis tools by manually or automatically adding instrumentation points to the C source code. Thus, the executable code can be run on the MERASA processor and whenever an instrumentation point is reached during testing, trace information is recorded in the form of an instrumentation point identifier and a timestamp. This trace information will be written to a file for later analysis.
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System Software
The MERASA system-level software [KW08] represents an abstraction layer between application software and embedded hardware. It provides basic functions of a real-time operating system to be a fundament for application software running on the MERASA processor. The challenge in this software field is to guarantee an isolation of memory and I/O resource accesses of various hard real-time threads running on different cores to avoid mutual and possibly unpredictable interferences between hard real-time threads. The intent of this isolation is also to enable an effective WCET analysis of application code. The resulting system software should execute hard real-time threads in parallel on different cores of a multicore MERASA processor or within different thread slots of simultaneously multithreaded MERASA cores. These hard real-time threads will potentially run in concert with additional non real-time threads of mixed application workload. Figure 2 shows the architecture which consists of three main parts: The Thread Manager provides an interface to the hardware-based real-time capable thread scheduling unit of the MERASA core processor and mechanisms for thread synchronisation. The Dynamic Memory Management minimizes interferences of different threads by providing a flexible two-layered memory management with memory pre-allocation. Finally, the Resource Management enables the use of peripheral device drivers.
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State of the Project and Future Work
The MERASA project is scheduled for three years until Nov. 2010. Until then, the main objectives of University of Augsburg will be the implementation of the MERASA single-core on an FPGA board, the extension to a multi-core simulator (including the results of design space exploration at Barcelona Supercomputing Center) and implementing it on an FPGA board, as well as an appropiate System Software for the multi-core MERASA processor. The developed core architectures should be analysable in the terms of WCET and therefore scheduling and thread management, inter-core communication and memory architecture will be an important research part in the next months. Until now, a first version of a low level MERASA simulator has been developed and is currently tranformed to VHDL code on an Altera Stratix II. The first version of working System Software is delivered to all project partner and made public through our project website3 . The research focus of our different doctoral theses goes beyond the project work. Based on MERASA, one objective is the investigation of new multi- and many-core architectures. Another thesis explores and ascertains a sophisticated hardware debugging interface. In a third PhD project in concert with the development of the MERASA System Software, safety and security aspects are taken into consideration – especially to fulfill hard real-time requirements in automotive and avionic environments.
References [KMUU06] Florian Kluge, Jörg Mische, Sascha Uhrig, and Theo Ungerer. CAR-SoC - Towards an Autonomic SoC node. ACACES 2006 Poster Abstracts, 2006. [KW08]
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Florian Kluge and Julian Wolf. Basic system-level software for a single-core merasa processor. http://www.informatik.uni-augsburg. de/lehrstuehle/sik/publikationen/reports/2008_06_klu/. Technical Report 2008-06, University of Augsburg, Department of Computer Science, Augsburg, Germany, April 2008.
http://www.merasa.org
