Multiple Independent Gate Field Effect Transistor (MIGFET) – Multi-Fin RF Mixer Architecture, Three Independent Gates (MIGFET-T) Operation and Temperature Characteristics L. Mathew, Yang Du , S. Kalpat , M. Sadd, M. Zavala, T. Stephens, R. Mora, R. Rai,S. Becker, C. Parker , D. Sing, R. Shimer, J. Sanez, A.VY Thean, L. Prabhu , M.Moosa,, B.-Y. Nguyen, J. Mogab.G.O. Workman,A. Vandooren,Z. Shi M.M. Chowdhury2, W. Zhang2,J.G. Fossum2 2 University. Of Florida, FL32611-6130, USA APRDL Freescale Semiconductor Inc. 3501 Ed Bluestein Blvd.MD: K10 Austin TX-78721, U.S.A: (
[email protected], phone: 512 933 2385)-USA
Abstract MIGFET devices have multiple gates to independently control the channel region. This allows for new device architectures and applications. This paper deals with three novel aspects discussed the first time I) Multi-fin MIGFET device with two independent gates capable of high current drives has been fabricated and demonstrated as a RF Mixer II) For the first time a MOSFET with three independent gates has been fabricated. These devices can be used in single transistor memories III) MIGFET has been used to characterize temperature effects on double gate devices in single electrode and independent gate modes. The three aspects discussed in the paper will have significant impact on future applications of these devices. The MIGFET can be integrated with double gate devices enabling novel analog circuits to scale with multi-gated digital CMOS in future digital CMOS transceiver (Single Chip Radio). The third independent gate in the MIGFET-T device enables novel memory architectures. Temperature characterization reveals the double gate Vt can be shifted both by temperature and by the second gate bias. This data enables compact modeling of temperature effects on independent gate devices to evaluate circuits that take advantage of this characteristic of the MIGFET. Introduction Double gate devices offer excellent short channel control and have been proposed to replace the planar MOSFETs [1]. Recently CMOS independent double gate devices have been demonstrated [2]. MIGFET has been demonstrated to be single-fin GG input Mixer [2] but these mixers have lower current compared to multiple transistor planar CMOS mixers. The current in finfet devices can be increased using multiple fins and a common source drain regions (Figure 3). This is not effective for multiple independent gate devices. Adding a contact between each fin would increase the size of the layout substantially or reduce process tolerance. To be useful as a practical CMOS mixer, a new architecture has been proposed and demonstrated (Figure 4). This multi-fin option is required to make practical mixers that can switch high current to drive the load across the drain of the mixer. The MIGFET mixer with multi-fin option has been demonstrated for the first time. A second Novel device architecture demonstrated is MIGFET with three independent gates (MIGFET-T). In this device there are three independent gate electrodes, the MIGFET has been demonstrated as a single transistor memory element [3]. In such devices the body of the MIGFET can be biased using a common third gate provided by the MIGFET-T. MIGFET is an excellent device to study temperature effects for double gate devices, since each gate can be separately or jointly biased. Temperature effects have be characterized for double gate and independent gate modes of operation. Multi-Fin MIGFET Architecture, fabrication and Characteristics SOI Silicon wafers of 100 nm silicon over insulator and 50 nm nitride were patterned into thin silicon channel regions of approximately 40 nm (Body thickness) and 150 nm heights. A 20Å of gate oxide was thermally grown on these fins. Poly-silicon Gates were patterned on such tall silicon/nitride fins. The gates are formed on either side of multiple source/drain structures using a novel mask-less self-aligned process flow. Multiple gate regions are formed on either side of this thin silicon fin (Figure 4). Spacers are formed around the gate regions to protect the silicon fins from being silicided. Cobalt silicide was formed on the source, drain and gate regions. As seen in Fig 2. The silicides are also formed on the independent gate regions near the fins by effectively taking advantage of the tall nitride over the fins. Previously, silicon regions with recess under nitride were used to prevent shorts during solicitation [2]. In this flow the silicon was not recessed and the cobalt silicide was formed such that it did not short with the silicon channel regions. The multiple 80 nm isolated gates formed on each side of the fins have been tied together in separate contact regions. A copper backend process was used to make contact to the two gates, source and drain. The Id-Vg characteristics Fig 5 of the MIGFET reveal the gates have been isolated using the new process and the device provides excellent SS and Vt modulation using the second gate.
MIGFET-Mixer: Electrical Measurement and Device Simulation The MIGFET has been proposed to be used as a single transistor mixer [2]. The significant advantage of MIGFET mixer compared to planar CMOS based mixers is the superior signal matching achieved with self aligned gates across a common fully depleted un-doped channel. In this paper, multi-fin MIGFET mixer architecture has been demonstrated. A 50 kHz sinusoidal RF input signal and 40 kHz LO input signal was applied to each of the independent gates. A variable load resistor was used between the drain and supply of the MIGFET. The mixed output is obtained across the load resistor that is chosen so that the input and output impedances are matched. UFDG simulation [5] of MIGFET mixer shows the mixer can be used in different modes by varying the DC offset of LO input. Biasing the DC offset such that the LO is centered near the Vt, we obtain mixed output without clipping. Centering the LO input above and below the Vt, top and bottom clipped mixed output is obtained (Fig 6). The MIGFET mixer device showed excellent mixing characteristics (Fig. 7) using square wave LO input and sinusoidal RF input. The effect of varying RF amplitude and offset was investigated to optimize mixer gain and reduce noise (Fig 8, 9). The mixer output frequency spectrum showed mixed components of RF± LO obtained at 10 kHz and 90 kHz respectively. At higher RF powers additional harmonics were obtained. An ideal RF mixer will use the MIGFET mixer in a balanced topology (Fig 10). MIGFET-T (MIGFET with Three Independent Gates) Novel MIGFET with three independent gates has been demonstrated. The third gate of the MIGFET is at the bottom of the channel region, the thick starting buried oxide was used as the gate dielectric and silicon substrate as the electrode. Since a third gate is now biased independently VG1 and VG2 have been plotted in separate axis and the response for each VG2 plotted in a 3D plot. At VG2 = 0.2, VG1 and VG3 were biased to get Id-Vg linear and saturation (Fig. 11) as seen the third gate now modulates the short channel characteristics. The linear short channel control (Fig. 12) is modulated much more than saturation (Fig. 13) using the third gate. The MIGFET-T has been demonstrated to function as a single transistor memory [4]. Retention characteristics of MIGFET-T based memory cell is shown in Fig 14. MIGFET-Temperature characteristics The MIGFET has modulated by the gates only on the sidewalls and not from the top surface. Thus it is an excellent device to characterize individually the effect of the second gate and with the gates tied together. The MIGFET sub-threshold characteristics for temperatures from -40oC to 185oC demonstrate the sub-threshold change in Vt and SS as other SOI devices, even though the Vt and SS changes with temperature the second gate has considerable influence on these same characteristics . This data suggests that the second gate can be used to compensate for the changes in temperature by an appropriate bias on the second gate of the MIGFET. Conclusion Multi-fin MIGFET devices on the tallest reported 150 nm topography have been fabricated for the first time. The independent gates have been effectively silicided without use of overhang spacers. Multi-fin MIGFET architecture devices fabricated has been demonstrated to be an effective CMOS signal mixer. A five terminal device MIGFET-T has been demonstrated for the first time. All three gates have been used to modulate the thin silicon fin channels. The temperature characteristics of MIGFET devices have been studied. All these experiments provide a step closer to making double gate architectures feasible in both analog and digital applications. Reference [1].D. Hisamoto et al IEDM 1998 p 1032, 1998 [2] L. Mathew et al SOI Conf. 2004 [3] Gen Pei, IEEE TRANS. ON ELECTRON DEVICES, VOL. 51, NO. 12, DEC. 2004 [4]S. Okhonin et al VLSI 2005 (Submitted) [5] J.G. Fossum et al SSE Vol. 48, pp 919, June 20
GATE 2 40nm Channel
Multiple GATE 2 Source
Source
Drain
S
GATE 1
GATE 1 Fig. 1a SEM view of MIGFET Gates Isolated without CMP
D
S
D
S
D
Drain
GATE 2
Multiple GATE 1
Fig. 2. 40nm Fins straddled by independent gates
Fig.3. FinFET with common silicon source/drain region
Fig.4. Multifin-MIGFET with multiple gates on either side
Vds=1.2 Vdd R
Vds=0.1
Vo
(small signal sinusoid)
(large signal square wave)
VG2 -.5 to .5
Fig.5. Id-Vg characteristics of FinFET with common silicon source/drain region
Fig. 6 a) UFDG circuit simulation of MIGFET-Mixer shows the envelope on both sides. b) Effect of LO bias below Vt shows clipped output, output clipping is achieved just by changing DC offset using a single transistor 0
Fig.11 MIGFETT for VG2 = -0.2
LO Input
-10
RF Sine Input: 50khz Mixed Output for various LO/RF Bias
RMS Voltage (dB)
-20 -30
Mixed Output
-40 -50 -60 -70
Noise
-80 -90
LO Pulse Input: 40khz
-100
VG2= -0.2,0,0.2
0.5
0.7
0.9
1.1
1.3
RFInput Vpp(V)
Fig.12. MIGFET-T Linear , high 3rd gate modulation
Fig.8. Effect of RF input amplitude on the mixed signal output and noise
Fig. 7 . Oscilloscope trace in time domain showing mixed output waves with sinusoidal RO at 50kHz and square pulse LO at 40kHz for varying RF amplitude
-20
LO=50kHz RF=40kHz RF-LO=10kHz
LO input
-30
RMS Voltage (dB)
More Harmonics at Higher Power for the RF input
-40 -50 -60
Mixed output
-70 -80 -90
RF+LO=90kHz
Noise
-100 -600
-400
-200
0
200
400
600
RF Input DC voltage offset (mV) Fig 9. Effect of DC offset in RF input on the mixed signal output and noise
Fig. 10. Spectrum analyzer trace showing the effect of RF signal amplitude and DC offset on the mixed signal output.
Vds=1.2 T=-40,0,27,85,105
Vds=1.2
Vds=0.1
Vds=0.1
VG2 -.5 to .5 DoubleGate Mode
T=-40C Fig. 15 MIGFET Temp. Charc. with gates Tied,Vt, SS,gm, changes
Fig.13. MIGFET-T Saturation, lower 3rd gate modulation
VG2 -.5 to .5
Independent Gate Mode
T=85C
Fig.16 a,b,c. Independent mode temp. changes VtAnd SS. Second gate can move Vt in both direction. The Gate Tied has better gain than -40C
.Fig 14. Retention Z-RAM memory cell on MIGFET-T at T=300K [4]
