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ABSTRACT: A program controlled timing arrangement for service circuit registers in a real-time processing system is dis closed. Sixty timing lists and a modulo-60 counter for indexing the lists are provided. At l-second intervals the registers on the list presently indexed by the counter are examined for timeout and the counter is incremented. A register requiring timing is placed on a list in accordance with the required time interval and the calculated value of the counter at the termina tion of this interval. Facilities are also provided for interrupt
ing and reinitiating timing without loss of unelapsed time.
HCTL‘" I
ADDRESS OF FIRST REGISTER ——————————————————— ——
+2)“
+2x2-
FOR INTERVAL o TIMING LIST
ADDRESS OF LAST REGISTER ADDRESS OF FIRST REGISTER