IEEE ELECTRON DEVICE LETTERS, VOL. 26, NO. 11, NOVEMBER 2005
799
Parasitic Reset in the Programming Transient of PCMs D. Ielmini, Member, IEEE, D. Mantegazza, A. L. Lacaita, Senior Member, IEEE, A. Pirovano, and F. Pellizzer
Abstract—We studied the programming dynamics in phase change memory cells. It is shown that programming in stand-alone cells is strongly affected by the parasitic capacitance in the measurement setup, leading to a current overshoot after threshold switching of the amorphous chalcogenide. This results in a parasitic melting and quenching of the active material, affecting the current distribution during program and the final phase distribution in the active material. The relevance of this artefact for real-device operation is discussed with reference to the value of the parasitic capacitance. Index Terms—Phase change memories (PCMs), nonvolatile memories, threshold switching, chalcogenide materials.
I. INTRODUCTION
A
MONG the recently proposed nanoscaled devices for nonvolatile storage, the phase change memory (PCM) presents many attracting features, such as a large cycling endurance [1], [2], a fast program and access time and an extended scalability [3]. Memory programming consists of a current-induced reversible phase change in a chalcogenide layer: while the high-resistive, amorphous state is obtained by melting and fast cooling of the material in an active region, the low-resistive, crystalline phase is formed by high-temperature annealing of the amorphous volume. As the phase transition represents the core of the device operation, understanding the detailed phase distribution as a function of the programming conditions is an essential task in the development of scaled and competitive PCMs. Previous experimental studies demonstrated that the set operation, namely the current-induced crystallization of the amorphous material to reach the low-resistive state, results in a stacked distribution of amorphous and crystalline phase [4], [5]. However, numerical simulations of the PCM programming based on an electrothermal model indicated that threshold switching occurs along localized current paths, leading to crystalline filaments in the set state [6]. To resolve this controversy, we investigate the programming transient, focusing on
Fig. 1. Schematical view of the standard setup for electrical characterization of stand-alone PCM cells. The parasitic capacitance C at the contact node is also shown.
the effects of electronic switching and the role of the parasitic capacitances in the experimental setup. II. SWITCHING TRANSIENT Fig. 1 shows the experimental setup which is typically used for PCM electrical measurements [1], [2], [4], [5], [7]. A standalone cell with about 2000 nm contact area and a 90-nm-thick chalcogenide layer was connected to a pulse generator with a k in this work). An elecseries (load) resistance ( at the node B on top trometer is used to probe the voltage of the memory cell, thus allowing for the extraction of the cur, where rent in the load resistor as is the applied voltage. However, as indicated in the figure, the of node B cannot be neglected, as it parasitic capacitance transient [8]–[10]. The current significantly impacts the flowing in the PCM can be obtained by analyzing the electrical network as (1)
Manuscript received July 26, 2005. The review of this letter was arranged by Editor S. Chung. D. Ielmini and D. Mantegazza are with the Dipartimento di Elettronica e Informazione and Italian Universities Nano-electronics Team (IU.NET), Politecnico di Milano, Milano 20133, Italy (e-mail:
[email protected]) A. L. Lacaita is with the Dipartimento di Elettronica e Informazione and Italian Universities Nano-electronics Team (IU.NET), Politecnico di Milano, Milano 20133, Italy and also with IFN-CNR, Sezione Politecnico di Milano, Milano 20133, Italy. A. Pirovano and F. Pellizzer are with STMicroelectronics, Advanced R&D, NVMTD-FTM, Agrate Brianza 20141, Italy. Digital Object Identifier 10.1109/LED.2005.857719
where a parasitic capacitance pF was estimated in our in response to a setup from the analysis of the waveform of step-like change of . This capacitance is due to various contributions, including the contact tip for measurement, the contact . pad on the wafer and the active probe used for sensing To study the PCM current during the switching transient, we first prepared a PCM in the high-resistance reset state by applying a reset pulse of 1 mA for 50 ns. A high resistance of
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Fig. 2. (a) Measured voltage V as a function of time, in response to an applied squared voltage pulse with amplitude V = 1:3 V and width T = 1 s. (b) Corresponding current I calculated by (1), showing the current overshoot in correspondence of the threshold switching at t = 300 ns.
1.5 M was then measured on the cell. Then we applied a programming square pulse of amplitude V and width 1 s. Fig. 2 shows the measured and calculated during the is first close to the approgramming pulse. The measured plied , consistently with the high resistance of the amorphous chalcogenide in the OFF-state. After about 300 ns from the start suddenly drops to about 0.55 V, revealing the of the pulse, change of chalcogenide resistance due to threshold switching. Note the relatively long delay prior to switching, which is a con[11]. The current , sequence of the relatively small applied calculated according to (1), displays a large current overshoot of about 1.25 mA in the transition from high to low resistance of the active material. The overshoot was previously reported in discharge through the PCM [8]–[10], and is the result of the abruptly drops down. as characteristics, comparing the tranFig. 3 shows the – sient behavior of Fig. 2 to the steady state curve. The latter was obtained applying a sequence of 200-ns pulses with variable , sampling shortly before the end of the pulse and ne[2]. glecting the capacitive term while applying (1) to obtain The sample was prepared in the high-resistance state by a reset pulse. The transient characteristic in Fig. 2 pulse prior to any shows that the device is initially biased in the high-resistance OFF-state, then the current suddenly raises to the ON-state curve in correspondence of the switching time, while the voltage remains almost constant due to the large parasitic capacitance. The ON-state stationary condition is then reached, and as the voltage pulse is turned off the current vanishes along the high-resistive characteristic. It is worth noting that the switching current overshoot exceeds the reset current of 1 mA, which was initially applied to program the memory in the high-resistance state. Also, the current overshoot width is approximately given by the electrical RC constant of the PCM in the ON-state, which is about 8 ns. The overshoot width is thus comparable to the estimated thermal time ns, where and are the constant equivalent thermal resistance and heat capacitance in the PCM, respectively. Thus the parasitic current and time are sufficient to
IEEE ELECTRON DEVICE LETTERS, VOL. 26, NO. 11, NOVEMBER 2005
Fig. 3. Steady state and transient I–V characteristics of the PCM device. The transient curve is obtained plotting I –V values from Fig. 2.
Fig. 4. Schematic of different phase-change behaviors, showing the distribution of current paths in the reset cell (left) and the phase distribution at the end of the program pulse (right). We consider both the case of a stand-alone cell with (a) relatively high C and (b) the integrated cell described in the text.
provide melting in the active material, causing the formation of a new amorphous phase within (and possibly outside) the original one. Therefore, the current overshoot during switching leads to a parasitic reset, inherent to the switching process in presence of a large parasitic capacitance. III. IMPACT ON PROGRAMMING From the point of view of the electrical properties, the whole volume of newly formed amorphous phase is in a low-resistance, ON-state, and current flows uniformly in the programmable volume as shown in Fig. 4(a). The temperature profile resulting from Joule heating reflects the distribution of current density. Thus temperature rapidly decreases approaching the upper contact, due to both the spreading of current and the boundary conditions at the top metal contact [6]. The rate of phase transition is thus highest close to the bottom contact and constant within the contact cross section, with no filament effects. This results in a hemispherical volume of crystalline phase within an amorphous shell, consistently with the observed series distribution of phases in partially set states [4], [5]. We again recall that this type of phase change is a consequence of the parasitic reset, and is therefore a unique feature of programming stand-alone PCM cells previously prepared in
IELMINI et al.: PARASITIC RESET IN PROGRAMMING TRANSIENT OF PCMs
the high-resistive state and in presence of a high parasitic capacitance. In a PCM array, the cell resistor has a top connection to the bitline and a bottom connection to an integrated select-MOSFET [12], providing two distinct parasitic capaci– pF (bitline capacitance) and tances fF (drain capacitance of the selector MOSFET). To evaluate the impact of this capacitance, we note that the capacitive term in , where ns is (1) can be neglected if the switching time needed to complete the chalcogenide transition from the OFF- to the ON-state [10]. Assuming an ohmic resistance of the selector below 1 k , the bottom and top RC time constants are ps and ns, respectively smaller and larger than . Thus the bottom capacitance readily charges up within the switching time accommodating the chalcogenide snap-back, while the PCM current is limited by the saturated MOSFET characteristics and features no parasitic overshoot. As a result, the amorphous chalcogenide will switch on along hot filaments where the electric field is maximum, as schematically shown in Fig. 4(b). The localized current will thus result in a parallel-type phase distribution [6]. Finally, it is worth pointing out that the detailed transient of the current flowing in the stand-alone cell should be carefully taken into account when evaluating the programming performance of different cell designs. In fact, the effective programming current may be substantially underestimated by the measured steady state current after the switching transient. Therefore, the parasitic current overshoot may well explain abnormally low programming currents which have been recently reported for nonconventional cell structures [13]. IV. CONCLUSION We have shown that the parasitic reset in the programming transient of analytical PCM cells leads to a uniform current density in the amorphous chalcogenide and to a stacked distribution of crystalline and amorphous phases. The parasitic reset has thus to be taken into account while evaluating the set current for PCM performance comparison. Finally, we show that no parasitic reset occurs when the cell is connected to a select transistor, as in the integrated memory array, due to the small parasitic capacitance and to the current-limiting MOSFET characteristic.
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ACKNOWLEDGMENT The authors would like to thank A. Redaelli (Politecnico di Milano) and R. Bez (STMicroelectronics) for fruitful discussions. REFERENCES [1] S. Lai, “Current status of the phase change memory and its future,” in IEDM Tech. Dig., 2003, pp. 255–258. [2] A. Pirovano, A. Redaelli, F. Pellizzer, F. Ottogalli, M. Tosi, D. Ielmini, A. L. Lacaita, and R. Bez, “Reliability study of phase-change nonvolatile memories,” IEEE Trans. Device Mater. Reliab., no. 3, pp. 422–427, Mar. 2004. [3] A. Pirovano, A. L. Lacaita, A. Benvenuti, F. Pellizzer, S. Hudgens, and R. Bez, “Scaling analysis of phase-change memory technology,” in IEDM Tech. Dig., 2003, pp. 699–702. [4] D. Ielmini, A. L. Lacaita, A. Pirovano, F. Pellizzer, and R. Bez, “Analysis of phase distribution in phase-change nonvolatile memories,” IEEE Electron Device Lett., vol. 25, no. 8, pp. 507–509, Aug. 2004. [5] A. Itri, D. Ielmini, A. L. Lacaita, A. Pirovano, F. Pellizzer, and R. Bez, “Analysis of phase-transformation dynamics and estimation of amorphous-chalcogenide fraction in phase-change memories,” in Proc. IRPS, 2004, pp. 209–215. [6] A. L. Lacaita, A. Redaelli, D. Ielmini, F. Pellizzer, A. Pirovano, A. Benvenuti, and R. Bez, “Electrothermal and phase-change dynamics in chalcogenide-based memories,” in IEDM Tech. Dig., 2004, pp. 911–914. [7] A. Redaelli, A. Pirovano, F. Pellizzer, A. L. Lacaita, D. Ielmini, and R. Bez, “Electronic switching effect and phase-change transition in chalcogenide materials,” IEEE Electron Device Lett., vol. 25, no. 9, pp. 684–686, Sep. 2004. [8] M. P. Shaw and I. J. Gastman, “Circuit controlled current instabilities in “S-shaped” negative differential conductivity elements,” Appl. Phys. Lett., vol. 19, pp. 243–245, 1971. [9] J. Kotz and M. P. Shaw, “A thermophonic investigation of threshold and memory switching phenomena in thick amorphous chalcogenide films,” J. Appl. Phys., vol. 55, pp. 427–439, 1984. [10] D. Adler, M. S. Shur, M. Silver, and S. R. Ovshinsky, “Threshold switching in chalcogenide-glass thin films,” J. Appl. Phys., vol. 51, pp. 3289–3309, 1980. [11] S. R. Ovshinsky, “Reversible electrical switching phenomena in disorder structures,” Phys. Rev. Lett., vol. 21, pp. 1450–1453, 1968. [12] F. Pellizzer, A. Pirovano, F. Ottogalli, M. Magistretti, M. Scaravaggi, P. Zuliani, M. Tosi, A. Benvenuti, P. Besana, S. Cadeo, T. Marangon, R. Morandi, R. Piva, A. Spandre, R. Zonca, A. Modelli, E. Varesi, T. Lowrey, A. Lacaita, G. Casagrande, P. Cappelletti, and R. Bez, “Novel trench phase-change memory cell for embedded and stand-alone nonvolatile memory applications,” in Symp. VLSI Tech. Dig., 2004, pp. 18–19. [13] P. H. Bolivar, F. Merget, D.-H. Kim, B. Hadam, and H. Kurz, “Lateral design for phase change random access memory cells with low-current consumption,” in Proc. Eur. Symp. Phase-Change and Ovonic Science, 2004.
