Placement Benchmarks for 3-D VLSI - Springer Link

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schedule would have to bc drastically shortcncd. Givcn the high quality of the partitioncr, and thc fundanlcntal sound- ness of thc partitioning placcmcnt tcchniquc ...
Placement Benchmarks for 3-D VLSI Stcfn.ll TholIlilS Obcnaus Scho 01 01 Cornpll,te1' Scienc McGill Uni'Ver'sity

T cd I1. S)!;ymanski Comm'unications Resear'ch L abvratory AIcMaster' Uni'Ve1'sity

Abstract

\Ve pro vide a general defutition of the 3-D wireleugth placemen problem, This definition facilitate; comparison of 3-D placement algürithms, "\Virelength re;ults llbing partztioning placement are induded fur the A and ISPD98 standard benchmark circuit suites, FW1:her, a wire1ength comparbon betWef:'1l 2- and 3-D placemerts is made, and it is shüwn that 1al'ger' circuits require 50%-60'K 1es::; wire1engthvhen utilising the thircl dimensiou,

Keywords: 3-D, Benchmarks, Pla

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