Pulse-Width-Modulating Biosignal ADC for Rapid ASIC Design and IP Core Reuse Robert Rieger and Shi-Hao Ou National Sun Yat-Sen University in design and evaluation. Albeit small limitations in Editor’s notes: power efficiency must be This paper presents an integrated analog-to-digital converter (ADC) accepted compared to a based on pulse-width modulation (PWM) employing a clocked comparafully optimized design, this tor. The converter parameter resolution, sample rate, input range, and approach enables the resupply voltage are adjustable and make the design useful for implantable use and adoption of the or wearable multiple biopotential recording (ExG). —Shuenn-Yuh Lee, National Cheng Kung University circuit block which is significant for rapid prototyping, teaching, and research h THE ANALOG-TO-DIGITAL CONVERTER (ADC) is where several generations of designers (students) an essential component in modern integrated and researchers may advance with minimum overelectronic systems incorporating analog as well as head in design and evaluation time. A choice of different converter architectures is digital signal processing stages. An important area of application is in biomedical acquisition and available for the target range of application. This processing systems for health monitoring or as includes the cyclic, successive-approximation (SAR), part of a prosthetic device [1]–[3]. The targeted oversampling, and voltage–time–voltage integratdigital resolution for this kind of application is ing converter. A comparison of these approaches 8–10 b, and the maximum conversion speed fs is is provided in Table 1 and a more detailed overabout 20 kHz, sufficient for a wide range of biopo- view is available in [5]. The proposed integrated tentials [4]. The rapid advance of technology and circuit ADC core is based on a single-ramp pulsewidening application market require the research width modulator (PWM) and counter circuit. and realization of novel systems at a fast pace. In This ADC yields the advantage of being naturally this article, we propose the use of a slope integrat- dividable into subcircuits. These blocks can be ing ADC with specific attention to its usability in designed and tested individually, thus lessening different application environments and simplicity the complexity of these tasks. Moreover, all intermediate signals are linear and also the signal Color versions of one or more of the figures in this paper are available flow is linear (no feedback is used in the signal online at http://ieeexplore.ieee.org. path). Figure 1 shows the converter divided into Digital Object Identifier 10.1109/MDAT.2016.2536657 subcircuits where the PWM requires the main deDate of publication: 01 March 2016; date of current version: sign effort as it determines the linearity and noise 17 June 2016. of the converter. The pulse width of the
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Copublished by the IEEE CEDA, IEEE CASS, IEEE SSCS, and TTTC
2168-2356/16 B 2016 IEEE
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Table 1 Comparison of ADC architectures for configurable biosignal application.
modulated signal is measured by a digital counter which may reside on or off chip. In the latter case, the PWM signal is pinned out and connected to the remote counter, e.g., to a microcontroller in the application system. More than one copy of the PWM block may be placed in the design to provide multiple data channels. In
principle, pairs of channels can be combined to yield differential (DM) or common-mode (CM) configurations. A DM/CM channel combine logic block is optionally added for this purpose. The CM channel is useful to obtain information about coupled interference to drive a right-leg circuit [6], or to operate the channels in doubledifferential mode [7]. Initial measured results for one specific configuration of the circuit were previously presented by the authors in [8]. The current article explores the configuration options for the circuit modules to make them useful as reuse core and it provides the analysis revealing the circuit limitations. The focus lies on the ease of design and circuit synthesis. Straightforward performance prediction and modular design enable the use for different ExG applications. Table 2 gives examples of ADC performance targets for the acquisition of a range of (preamplified) biopotentials. The target specifications for the prototype converter are provided in Table 3 and further detail is presented in the Circuit design section. The Measured results section reports on measured results obtained from fabricated samples of the ADC tested on the bench in different settings. Moreover, biomedical application examples are provided where the ADC is used to first convert the electromyogram (EMG), and then the electrocardiogram (ECG) as part of a galvanic isolation patient front-end. It shows that the PWM output can conveniently be transmitted through a digital isolator.
Circuit design
Figure 1. ADC is divided into functional circuit modules which can be designed and verified individually for high circuit reuse and low design complexity.
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Voltage-time-converter design The PWM core cell employs a switched capacitor approach. In the first phase, a capacitor C samples the input voltage via a switch. It is followed by a conversion phase during which the capacitor is discharged by a constant current I toward a final voltage Vref and the width of the output pulse is modulated according to the capacitor discharge time. Dual-slope integrators are often used, providing the advantage that gain errors due to die-to-die variation of C and I cancel [9]. However, it results in longer conversion time for a given discharge current. In our range of applications, offset and gain variation are not critical so that a single-slope approach is chosen to achieve faster conversion with
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small power consumption. However, when operating two converters in DM/CM configuration, gain variation does matter and then this simple approach trades off with a requirement for gain trimming by adjusting I or C either in an initial setup phase or continuously using feedback [7], which is not implemented on the chip presented here. The nominal capacitor discharge time Tc is given by Tc ¼ ðVin Vref Þ
C ¼ ðVin Vref Þ APWM I
Table 2 Typical application requirements.
(1) Table 3 Parameter specification for this
where APWM is the transfer gain of the circuit and implementation. so the conversion speed is limited by the choice of C , I , and the conversion range. To double the conversion throughput, a time-interleaved structure is proposed as shown in Figure 2. Two input capacitors C1 and C2 are charged by the input voltage ) and during alternating sample phases ( and discharged by the same current source during the conversion phases. The output voltage of the discharging capacitor is fed to a comparator which compares it to the constant reference Vref which is here chosen as 0.25 V. The end of the conversion cycle is reached when the capacitor voltage reaches the reference level as determined by 10-b mode, the standard deviation of the INL is the comparator. The discharging current source 0.07 LSB over the 1-V input range. Since the capacitor must be discharged within is realized by a pseudocascode metal–oxide– semiconductor (MOS) transistor [10] consisting of less than one sampling period, the maximum value M3 and M4. The dimensions of the current mirror of Tc found from (1) determines the maximum M1 –M4 affect the linearity of this stage. Figure 3 shows the simulated linearity for three different sizes of transistors M1 –M4 . A deviation from the ideal discharge line of less than 1.5 mV is achievable with practical transistor sizes. For a 10-b conversion, this yields about 0.7 least-significant-bit (LSB) integrated nonlinearity (INL). Slightly higher INL is expected for the smaller MOS dimensions used in the current implementation. Furthermore, corner simulations show that the differential nonlinearity (DNL) remains within 0.5 LSB. The variation of linearity due to transistor mismatch is examined Figure 2. Circuit diagram of the PWM input stage with time-interleaved by Monte Carlo simulation. In sampling and discharge. MOS sizes are given in micrometers.
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Figure 3. Simulated deviation from the ideal discharge slope for different sizes of the mirror transistors M1–M4 of Figure 2. The input ranges from 0.5 to 2.5 V.
conversion speed, which for a conversion range Vin max is fs
max G
I C Vin
max
:
(2)
The input range thus scales in inverse proportion to the selected sample frequency. Here, we choose C ¼ 5 pF and I ¼ 50 nA to provide a nominal gain of 100 s/V and to achieve a minimum of 5-kHz sample rate for 1-V input range around a midsupply ground.
The reference level for the comparator and the discharging current for the sampling capacitor are derived from an on-chip bandgap reference. A lowpower self-biased current source was used as shown in Figure 4. A 100-nA current reference is available at the drain of transistor M12 which is used to bias the comparator and which is further divided down to 50 nA to serve as the capacitor discharge current. It is also copied to M14 to generate the 0.25-V reference voltage across M15 . The minimum supply voltage for operation of this cell is 1.25 V. The comparator is realized using a p-channel MOS differential input stage followed by a clocked latch circuit as shown in Figure 5. A clocked circuit provides a fast response time with minimum direct current (dc) consumption. The latch is precharged and both output nodes are tied low when clock g is low. Comparison is made on the positive edge of signal clock g. When input voltage Vcharge is larger than reference level Vref , the output follows the clock. Otherwise, the output remains low. The nominal switching time delay of this circuit is found from simulation as 10 ns while consuming an average of 950-nA supply current. The comparator offset is determined from Monte Carlo transient simulation with a latch frequency of 4 MHz, and so it includes static as well as dynamic offset due to comparator delay when the input signal slope is 100 s/V. The simulation reveals a 519-V systematic offset and 7.2-mV offset standard deviation at the circuit output. Since comparison is made in discrete time intervals, the time resolution, i.e., LSB, of the PWM circuit referred to its input is given by LSBPWM ¼ ðfclock g APWM Þ1
(3)
and so the maximum input amplitude resolution expressed by the number of converter bits N is N ¼ log2 ½Vin max Voff APWM fclock g fclock g log2 fs max
Figure 4. Schematic diagram of the bandgap cell providing a 100-nA reference current and a reference voltage Vref of about 250 mV. Transistor sizes are given in micrometers.
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(4)
where Voff is the sum of the offset voltages of the converter and of the reference voltage Vref . A positive edge-triggered SR latch follows the comparator, also shown in Figure 5, which latches and holds the comparison result during the precharge phase and so provides a smooth output signal. A
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Figure 5. Schematic diagram of the clocked comparator followed by the latch circuit to provide the PWM output. MOS sizes are given in micrometers.
conventional ring oscillator block not described here further is included on-chip to generate the clock signal for the comparator alternatively to using an external clock input. Nominal latch frequency fclock g was chosen as 8 MHz which is sufficient to yield N ¼ 8, leaving a margin to accommodate deviation of gain and offset. Quantizing the PWM output by using a clock introduces quantizer noise. For input signal amplitudes exceeding a few LSB, this noise is for many practical cases well approximated by a white Gaussian distribution over a bandwidth from dc to the Nyquist frequency fs =2 . The root mean square (rms) output noise for a uniform sampler as this is Tn
PWM
ðfclock g
pffiffiffiffiffi 1 12Þ : (5)
Furthermore, thermal noise generated in the sampling p switch gives rise to a kT/C noise component of about 29 Vrms at room temperature which is negligibly small. Also, the discharging current is
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noisy. From simulation, a current noise density of p about 1 pA/ Hz is estimated; it is relatively high as the current is mirrored several times to provide convenient routing from the bandgap to the PWM circuit. This noise current is integrated on the sampling capacitor during the discharge phase and
Figure 6. Logic circuits for DM and CM channel formation (gray areas) which gate the clock for the DM and CM counters. A pair of switches can bypass the first CM flip-flop to provide a selectable increment by two. D-type latches are used for the CM ripple counter and parallel-clocked T-latches are used for the DM counter.
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a latch frequency fclock g is estimated which yields quantizer noise of the same magnitude as Vn . For example, using a mean discharge time TC of 100 s and a 5-kHz sample rate demands about 2-MHz minimum latch frequency.
Figure 7. Chip microphotograph showing two PWM units with bias and support circuits and two 10-b counters. Pads are not shown.
subsequently sampled by the comparator. For the sampled noise voltage density at the comparator input the approximation for sampled integrated noise provided in [11] is adopted to yield in Vn C
sffiffiffiffiffiffi TC fs
(6)
and the equivalent output noise is obtained by multiplication with APWM . By equating (5) and (6),
Figure 8. PWM power consumption measured for different supply voltages and comparator latch frequencies.
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Channel combination and counter design Two copies of the PWM circuit are placed on the application-specific integrated circuit (ASIC) providing a dual-channel output. The channels can also be combined to yield the CM or DM output using the small digital logic shown in Figure 6. Also shown are the counter circuit diagrams. When the CM logic is active, it receives the PWM signals VPWM1 and VPWM2 , respectively, from the two PWM circuits and applies them to an OR-gate. When either VPWM1 or VPWM2 is high, the OR-gate output is high. In this case, the clock to the counter circuit is passed via an AND-gate; otherwise, it is blocked. In addition, a second AND-gate produces a high output when both signals VPWM1 and VPWM2 are high. This instructs the counter to count upwards by two steps on each clock edge instead of one. A pair of switches controlled by signal “Count2” selectively bypasses the first ripple stage to realize the increments by two. In this way, the counter generates the CM output as addition of the PWM channels. Also shown in Figure 6 is the exclusive-OR (XOR) gate which implements single-bit subtraction between the channels for realizing DM output. The DM counter is constructed from parallel clocked toggle flip-flops which increase the count on each clock tick as long as the XOR output is high. The DM sign bit (which indicates which PWM input voltage is larger) is generated separately as shown. The “DMsign” output is updated on the initial rising edge of VPWM1 , which indicates the start of a new conversion cycle. Therefore, the sign output appears delayed by one sample. All latches are built from NAND-type gates and are rising-edge triggered. The worst case DM counting speed simulated in prelayout corner simulation yields 5 ns per tick. The power consumption at 3-V supply is 31 W when counting at 8 MHz and it reduces to 12 W for 2-MHz frequency (which is sufficient for full range coverage in 8-b mode). For the CM counter, the power is 19 and 8 W, respectively. While the counter is not operating, its power is negligible; for example, when converting a signal with
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500 samples/s, the DM counter power simulates about 1 and 3 W in 8- and 10-b modes, respectively. It is hence negligible in practice compared to the power consumed by the PWM stage.
Measured results The proposed circuit blocks were joined on an ASIC in a prototype configuration for testing. Two copies of the PWM units and two counters provide dual data channels. In addition, the bias circuit and clock generator are added as shown in the chip microphotograph of Figure 7. Also included and tested is the digital logic for DM channel combination. CM logic was also added but is not evaluated here as a design glitch in an output driver prevents us from accessing the signal for testing. The layout cells were individually designed and linked by metal interconnects to yield the final layout. The ASIC was fabricated in TSMC 0.35-m complementary MOS (CMOS) technology, the active die area measures 0.46 mm2 , and a single PWM core occupies 0.04 mm2. The measured power consumption of one PWM block and bias circuits operating at the nominal 3-V supply with 8-MHz clock is 41 W. The range of supply voltage which enables operation within the specifications of Table 3 is from 2.25 to 5 V. However, at this clock rate, power consumption exceeds the 100-W target when the supply increases beyond 3.5 V. This limits the practical supply level in a moderate power and speed application. Figure 8 shows measured results of the PWM power consumption for different supply voltages and comparator latch frequencies, all using 2.9-kHz sample rate. Figure 9 is the measured PWM INL and DNL for 10-b mode. The figure includes some noise which is especially visible in the DNL plot. The observed noise increases toward larger input voltages (i.e., larger discharge time TC ) as expected from (6). Still, the DNL remains below 1 LSB, and the INL is slightly larger than 1 LSB. For an 8-b conversion, the INL and DNL thus range about 0.25 LSB. The input range is related to the chosen sample rate via relation (2) which is confirmed by the measured data presented in Figure 10. The measured range is always smaller than the analytical maximum as there is always a time overhead required for starting a new conversion cycle.
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Figure 9. Measured INL and DNL expressed in LSB for 10-b conversion.
The PWM stage is further examined using an oscilloscope to observe latched comparator output voltages VPWM1 and the LSB of the counter. The second PWM cell was switched off. Figure 11a shows the result when the input voltage is 2 V. The amplitude of the counter ripple does not reach full scale due to the loading of the oscilloscope probe (which is not connected in normal operation). Next, both PWM modules are switched on to
Figure 10. Measured relation between input range and sample frequency (dots) compared to the analysis in (2). The measured range remains below the analytical maximum due to the additional time required for starting a new conversion cycle.
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capacitors far away from each other and decreases matching. Second, a long routing path for the discharge current including current mirrors introduces mismatch. Current mismatch levels would require trimming switches in the reference copy mirrors of Figure 4 to enable gain adjustment for DM/CM operation. This is inconvenient in terms of added area overhead as well as the Figure 11. Measurement of the PWM channels. Signal outh0i is the LSB setup time needed for initial of the counter. (a) Single channel with 2-V dc input. (b) Dual channels in trimming. Instead, improving DM configuration with 2- and 0.8-V input, respectively. the current path in a future implementation is expected to manage mismatch observe the DM output as presented in Figure 11b. and also decrease the noise floor of the converter. The sign bit was also tested and operated correctly. Next, the PWM was tested with dynamic singleThe gain error between the interleaved sam- tone inputs and external clock input to the complers was evaluated by examining the time series parator latch. This enables varying the latch rate output data for a full-scale amplitude input and and observing noise and resolution performance. the stages were found well matched with an error First, the sample rate was set to Ts ¼ 338.125 s less than 0.4%. The modulator gain APWM was mea- and the latch clock was 8 MHz. Figure 12 shows sured on 12 PWM cells and yields an average of the result for a sine wave input of 500 Hz and near 103 s/V. The relative gain error between two PWM full-scale amplitude in comparison with a smaller on the same circuit is found to be large, up to amplitude input. In the spectral plots, a Hanning 10%, which is in contrast to the good matching of filter was applied [12]. The output for the large the interleaved samplers. This is explained as a signal is 106 srms , corresponding to 300-s peakconsequence of maintaining individual design to-peak amplitude. The latter was obtained from blocks for the PWM which are then copied to ex- the time domain plot of the recorded output and pand the channel count. First, this places it is close to the theoretical maximum of 338 s set by Ts . The largest harmonic component occurred at 1 kHz with a magnitude of 493 nsrms . p The noise floor density is observed as 4.3 ns/ Hz, p and including distortion it is 12 ns/ Hz. A signalto-noise-and-distortion ratio (SINAD) of 45 dB and SNR of 56 dB are obtained from these data. A SINAD of 48 dB is achieved when the amplitude is reduced by 50%. Lowering the input amplitude further to yield an output peak of 6.255 srms (24 s peak-to-peak) reduces the harmonic components to near the noise floor. The largest harmonic is 20.8 nsrms at 983 Hz. The effective number of bits (ENOB [12]) relates the noise generated by the converter to the ideal noise (5) and is calculated as 7.5 b. Next, the sample speed was increased by setFigure 12. Superimposed spectra for a measurement ting Ts to 45.75 s (fs 21.85 kHz). The test input with full-scale 106-srms amplitude signal and with was selected as 10 kHz with 13.21-srms amplitude 8.5-srms amplitude. Latch frequency fclock g is 8 MHz.
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(38.25 s peak-to-peak, near full-scale) as the spectral plot in Figure 13 shows. The latch clock frequency was increased to 12 MHz to maintain a resolution of 9 b. The SINAD is measured here as 41 dB and the ENOB calculates as 6.6 b. The noise is expected to vary according to (5) as the clock rate is changed. A measurement with different clock frequency settings was performed using Ts ¼ 338.125 s, resulting in the plot presented in Figure 14. It is observed that the noise matches (5) for low latch frequencies but levels out at about 2 MHz. This is where the noise becomes dominated by the circuit thermal noise (6) and reducing quantizing noise does not further lower the overall floor. For benchmarking of ADC, a commonly used figure of merit (FOM) is FOM ¼
power : fS 2ENOB
(7)
For this PWM and including power consumption of the on-chip counters, FOM is 96 pJ/step for the measurement with slow sample rate and 23 pJ/step for fast sampling, both using nominal 3-V supply. For signals that require only very slow sample rates, e.g., the ECG, the power to the ASIC analog circuits can be duty cycled. This is done by switching the analog power off after the pulsewidth measurement has completed and restoring power about 20 s before the next sample which leaves sufficient time to precharge the sampling capacitor and start up the reference circuit. A duty cycle of 10% was achieved in measurement without noticeable degradation in performance. Under these conditions, the FOM scales down accordingly (thus maintaining a constant energy per conversion). As a test of practical application in a biomedical context, Figure 15 shows the PWM output when a prerecorded EMG obtained from [13] is applied to the converter. The converter was set to use 2-MHz latch clock, 2.9-kHz sample rate, and 3-V supply. Visual comparison with the input signal also shown in the figure confirms that the EMG is successfully captured. In the next measurement, the ADC is tested as a component in a galvanically isolated patient front-end. Galvanic isolation devices are used where recording of ExG requires electrical contact with the patient but processing electronics at the system back-end refers to a potentially hazardous main supply
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Figure 13. Spectrum for a maximum amplitude signal near the maximum frequency fs =2. Latch frequency fclock g is 12 MHz.
grounds [4], [14]. Also, power and signal isolation is required in certain implantable systems operating with highly different signal levels, e.g., in a high-voltage stimulator [15]. Here, a single PWM channel is passed through a digital isolator (HCPL-4731, Avago Technologies) and the pulse width is measured at the receiving side. The receiving counter is not locked to the latch frequency and a 2-kHz latch clock setting was used in this experiment. The power was duty cycled with a 40% on time, so that FOM is 38 pJ/step. An
Figure 14. Noise floor measured with fs ¼ 2.9 kHz and variation of fclock g . The minimum noise of about p 4 nsrms / Hz is achieved for fclock g 9 2 MHz. For lower frequencies the measured values match (5).
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AN ADC CORE was designed and tested which uses voltage–time–voltage approach to achieve a modular design and configurability. For a given PWM gain, variation of the counter and comparator clock (while using an appropriate counter length) enables variation of the converter resolution. This trades off with a linear change in power consumption. A nominal clock of 8 MHz was chosen here which is sufficient for 10-b resolution at moderate conversion speed. However, increasing the clock frequency above 2 MHz does not help to reduce the noise floor further as it is limited by circuit noise. Accordingly, the ENOB drops with increasing conversion speed. The design remains useful over Figure 15. Result of the PWM conversion of a the target range as, for example, in an implant for prerecorded EMG. The PWM pulse length is shown on the recording of ENG high resolution and speed is top and the input signal is at the bottom. Here, fclock g required but lower SNR is tolerable (Table 2). is 2 MHz and fs is 2.9 kHz. The evaluated ADC uses a ground-referenced input. To equip each stage with a differential input, the amplified and prerecorded ECG signal is used as sampler in Figure 2 would be modified to use capacthe input to the PWM. Figure 16 shows a screenitor dual-plate sampling where the differential input shot obtained from the measurement interface is applied across both ends of the sampling capaci(Labview, National Instruments). The received tor and only in the discharge phase one end of the pulse width is plotted in the top graph, and the capacitor is connected to VSS. The anticipated result ECG signal supplied to the converter is in the botis an improved CM rejection and hence lower inputtom graph. It demonstrates successful conversion, coupled interference. If well-matched gain stages are transmission, and recovery of the ECG signal sent required, gain trimming must be performed, e.g., by across the isolation barrier. tuning the discharging currents. Table 4 compares the performance of this converter with other recent designs for biomedical application. Clearly, the technology node has a strong impact on power, area, and FOM. Compared with other designs in 0.35- m technology, the achieved performance appears adequate. Overall, the proposed simple converter meets the target for biomedical signal acquisition comparable to the frequently used SAR converter which requires a more complex design procedure and yields fewer options for design parallelization which is especially important for achieving a predictable and Figure 16. Measurement of ECG conversion and transmission. The fast design time in research counter output is shown on top (scaled in units of received pulse width) and education. and the test input signal to the transmitting ASIC is at the bottom.
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Table 4 Comparison with other recent converters for biomedical application.
h References
[1] S. O’Driscoll, K. V. Shenoy, and T. H. Meng, “Adaptive
[7] R. Rieger and S. L. Deng, “Double-differential recording and AGC using microcontrolled variable
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no. 2, pp. 120–129, 2011. [2] M. Khayatzadeh, X. Zhang, J. Tan, W.-S. Liew, and Y. Lian, “A 0.7-V 17.4-W 3-lead wireless ECG SoC,” IEEE Trans. Biomed. Circuits Syst., vol. 7, no. 5, pp. 583–592, 2013. [3] N. Verma et al., “A micro-power EEG acquisition SoC with integrated feature extraction processor for a chronic seizure detection system,” IEEE. J. Solid-State Circuits, vol. 45, no. 4, pp. 804–815, 2010. [4] J. G. Webster, Medical Instrumentation—Application and Design, 3rd ed. New York, NY, USA: Wiley, 1998. [5] D. A. Johns and K. Martin, Analog Integrated Circuit Design. New York, NY, USA: Wiley, 1997. [6] M. A. Haberman and E. M. Spinelli, “A multichannel
[8] S. E. Lin, S. H. Ou, and R. Rieger, “Dual-channel pulse-width-modulation ASIC for isolated bio-signal recording front-end,” in Proc. IEEE Int. Symp. Circuits Syst., 2015, pp. 1246–1249. [9] P. Bruschi, N. Nizza, and M. Piotto, “A current-mode, dual slope, integrated capacitance-to-pulse duration converter,” IEEE J. Solid-State Circuits, vol. 42, no. 9, pp. 1884–1891, 2007. [10] C. Galup-Montoro, M. C. Schneider, and I. J. B. Loss, “Series-parallel association of FETs for high gain and high frequency applications,” IEEE J. Solid-State Circuits, vol. 29, no. 9, pp. 1094–1101, 1994. [11] R. Rieger, “Variable-gain, low-noise amplification for sampling front-ends,” IEEE Trans. Biomed. Circuits
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test methods,” IEEE Design Test, vol. 32, no. 1, pp. 26–35, 2015. [13] R. M. Rangayyan, Biomedical Signal Analysis: A Case-Study Approach. New York, NY, USA: IEEE Press, 2002, p. 267. [14] K. V. T. Piipponen, R. Sepponen, and P. Eskelinen, “A biosignal instrumentation system using capacitive coupling for power and signal isolation,” IEEE Trans. Biomed. Eng., vol. 54, no. 10, pp. 1822–1828, 2007. [15] D. Jiang, D. Cirmirakis, and A. Demosthenous, “A vestibular prosthesis with highly-isolated parallel multichannel stimulation,” IEEE Trans. Biomed.
Circuits and Systems, VLSI Systems and Applications, and Circuits and Systems Education and Outreach. He is also a member of the Taiwan Chip Implementation Center Peer-Review Committee; a Technical Committee Member of the Bureau of Standards, Metrology and Inspection of the Taiwan Ministry of Economic Affairs; and a member of the German Association for Electrical, Electronic and Information Technologies (Verband der Elektrotechnik). He is also an Associate Editor for the IEEE TRANSACTIONS ON BIOMEDICAL CIRCUITS AND SYSTEMS and the IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS— PART I: REGULAR PAPERS.
Circuits Syst., vol. 9, no. 1, pp. 124–137, 2015.
Robert Rieger joined the Department of Electrical Engineering, National Sun Yat-Sen University (NSYSU), Kaohsiung, Taiwan, in 2006, where he is currently a Professor of Electronics Engineering and the Head of the Bionics Integrated Systems Laboratory. His research interests are in the areas of integrated electronics for biomedical application and embedded and digitally assisted low-power analog circuits. Rieger has a PhD in electronic and electrical engineering from University College London (UCL), London, U.K. (2004). He is the Founding Officer and Past Chairman of the IEEE Engineering in Medicine and Biology Society Tainan Chapter. He is a member of the IEEE Technical Committees on Biomedical and Life Science
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Shi-Hao Ou was born in Yunlin, Taiwan, in 1989. He is currently an equipment engineer working on yield improvement and maintenance of the lithography and processing equipment at the Taiwan Semiconductor Manufacturing Company (TSMC), Hsinchu, Taiwan. He is also involved in the planning and evaluation of quality control projects. Ou has an MS from the Bionics Integrated Systems Laboratory, National Sun Yat-Sen University, Kaohsiung, Taiwan (2013).
h Direct questions and comments about this article to Robert Rieger, Electrical Engineering Department, National Sun Yat-Sen University, Kaohsiung, 80424, Taiwan;
[email protected].
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