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This algorithm loops i j times so that every group of each stage of the BN is converted into a CSG. Aij:I is simply the set of all distinct input labels of the current.
Rapid Prototyping Optimization and Implementation based on Conceptual Speci cation Chantana Chantrapornchai Michael Sheliga Edwin H.-M. Sha

Sissades Tongsima

Research report: TR-96-17

Dept. of Computer Science and Engineering University of Notre Dame Notre Dame, IN 46556 Abstract

In this paper, a new framework for system design and implementation which facilitates system prototyping is proposed. The methodology includes a global optimization process which minimizes designers' speci cation and system testing time. The user speci cation is separated into two components: a conceptual speci cation and a parameter speci cation. The conceptual speci cation de nes the system core which is rarely changed during the design process and may be implemented in hardware. The parameter speci cation de nes other parameters that are adjustable during the simulation process. Such a partitioning approach uses both hardware and software capability. Two models, a Behavioral Network, which describes the overall system behavior, and a Conceptual State Graph, which represents the conceptual speci cation, are presented. The methodology presented is able to shorten the development cycle and increase exibility for system designers.



This work was supported by NSF grant MIP 95-01006 and Royal Thai Government Scholarship.

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1 Introduction In the design of application speci c systems, the iterative process of detailing speci cations, designing a possible solution, and testing and verifying the solution is repeatedly performed until the solution meets user requirements [3]. This cycle prolongs the system development time. Furthermore, the system life cycle is likely to be short due to rapid pace of improvements in current technology. Therefore it is likely that the system will be out of date by the time it is ready to be used unless the development time is improved. Rapid prototyping is, therefore, an important method used to shorten the system development time from speci cation to prototype [5, 6]. Embedding all system components into hardware is not a good approach since it lacks exibility when hardware needs to be recon gured. By taking advantage of hardware and software capability, this paper proposes a rapid prototyping framework which yields exibility for testing several design solutions. Considerable research has been conducted on the applications of rapid system prototyping such as the work of Herold et. al. which considered the underwater acoustic modem as a target prototype[8]. For developing digital signal processing (DSP), Kahn and Swartzland proposed a method to prototype heterogeneous DSP system [12]. The design methodology based on architectural synthesis was presented by Kission et. al [13]. Nevertheless, their method considered hierarchical modules in which hardware and software components were not explicitly separated. In prototyping of embedded systems where the hardware/software co-design environment plays important roles [14,18], the need for methodological support in managing the development process and system life-cycle becomes urgent [22]. It is known that verifying such systems is time consuming and complex [1]. Other concerns on designing such systems are the hardware-software trade-o s with the system performance, the timing constraints, and hardware-software integrations such as the work in [7, 9, 16]. In this paper, we adopt the notion of hardware and software co-design and propose a design methodology that abstractly divides the design speci cation into two parts: a conceptual speci cation and a parameter speci cation. The conceptual speci cation contains the speci cation core and is rarely changed during system testing. The parameter speci cation includes speci c details which can be modi ed during the experimental phase. After 2

several iterations of the design process, the parameters that produce the best output with respect to the user requirements are selected and the nal system can be established. Figure 1 summarizes our prototyping methodology. First, a user speci cation describes what system does is obtained [4]. Next, from the given user speci cation, a global high-level system speci cation is calculated and then transformed to a behavioral network (BN). This model presents a global view of system behaviors. A global optimization process may be applied to the BN to minimize the speci cation. Next, the BN is partitioned into conceptual and parameterized components. A model called s conceptual state graph (CSG) is used to represent the conceptual speci cation. This model exhibits system functions without implementation details, such as as timing constraints or gate delays. Hence, such a graph can be mapped into a formal speci cation model such as a nite state machine (FSM). Because the conceptual speci cation is unchanged throughout the testing process, it may be implemented in hardware. Since a nite state machine modeling is well-developed, we use it to simplify hardware conversion and minimization [15]. Parameter speci cation, on the other hand, is handled by software since it describes speci c details of how the system is implemented. These details will likely change during the design iteration cycle, and need to be easily modi able. User Requirement Analysis

Hardware Prototype

Conceptual Specification

H/W Model and Optimization

Parameter Specification

S/W Development and Optimization Modification

High-level Specification

Optimization and Partitioning

Testing Prototype

Final Version Manufacture

Possible Design Solution Design Iteration Cycle

Figure 1: Proposed prototyping process In general, the proposed approach has the following bene ts: 1. rapid speci cation: the conceptual speci cation gives designers the ability to specify the overall concept of the system which is independent to parameter setting details. 2. exible tuning: the parameter speci cation and our system model allow designers 3

to easily adjust the parameters and consider several possible solutions in order to meet user requirements. 3. hardware/software capability: the integration of hardware prototype and exible parameterized software naturally takes advantages of the ideas of hardware/software co-design. 4. shorter development process: partitioning the speci cation into two components allows the possibility of developing hardware and software in parallel. Further, the optimized user speci cation can speedup the testing time and the parameter

exibility can facilitate adjusting a system to meet speci cation goals. We demonstrate the design methodology for fuzzy systems which have been popularly used in many industrial products recently [17]. Software fuzzy systems are exible but fail to provide high-speed result [19]. Although, general-purposed fuzzy hardware can yield a high-speed output, prototyping such hardwares is complex [11,21]. Our example will focus on the design of speci c fuzzy systems which utilizes software and hardware capability. The detail of our method will be discussed in the remainder of this paper which is organized as follows: basic terminology and graph models are presented in Section 2. The prototyping methodology and simulation process are presented in Section 3. Section 4 presents an example of prototyping a fuzzy control system. Finally, Section 5 summarizes the work.

2 System Models and Terminology A user speci cation is represented by conditional statements such as If-Then rules. The variables in the if-part are called input variables while the variables in the then-part are called output variables. For example,

x=1 If x = 2 If x = 3

If

y=5 Then y = 10 Then y = 15

Then

4

The input variable x has possible values 1; 2, and 3 and the output variable y has possible values 5; 10, and 15. In other words, the values 1; 2, and 3 are assigned to x. We de ne Ix as the domain of variable x, also denoted by domain(x). Similarly, Oy = domain(y). For this example, Ix = f1; 2; 3g and Oy = f5; 10; 15g. The set of all input domains is denoted by I , while the set of all output domains is denoted by O. Since this system has only one input domain Ix and one output domain Oy , I = fIxg, while O = fOy g. Such a speci cation can be modeled by a Behavioral Network :

De nition 2.1 A Behavioral Network (BN) is a labeled directed acyclic graph (DAG) G = (V; E; l) where V is a set of vertices, vi 2 V; 1  i  n, representing rules, input domains and output domains, E  V V is a set of dependence edges, ej 2 E; 1  j  m, e e denoted by u ?! v for u; v 2 V , and l is a set of edge labels (x; z) for u ?! v 2 E where x is an input variable of v and z is the value of x.

Figure 2(a) presents a BN corresponding to the above example. The network contains 5 vertices Ix; Oy ; A; B , and C . Ix is an input vertex and Oy is an output vertex, representing the input and output domains, Ix = domain(x) and Oy = domain(y), respectively. The possible values of x are f1; 2; 3g and y are f5; 10; 15g. An edge label represents an input variable and its value for a vertex. Vertex A requires the value of input variable x to be 1 in order for the value of variable y to be 5. We denote the label of edge e by l(e). The set of distinct inlabels of a group of nodes, Gr, in a BN, denoted by l (Gr), is the set of all distinct labels associated with edges ev ;v , where vj 2 Gr. For the above example, if Gr = fA; B; C g, then lin = f(x; 1); (x; 2); (x; 3)g. Similarly lout is the set of all distinct outlabels of a group of nodes in the BN. in

i

Ix

1) (x, (x,2) (x ,3 )

(y,5)

A

(y,10) B

j

(i,3)/(x,10) Oy

S0

) ,15

(y

(i,2)/Φ (i,1)/Φ

C

(a) BN example

S1 (k,2)/(x,10) S2

(k,1)/(x,5)

(b) CSG example

Figure 2: System model examples

5

S3

S4

A behavioral network presents a global view of a system which, in fact, embeds both the conceptual and parameter speci cations.

De nition 2.2 A Conceptual State Graph (CSG) G = (S; I; O; E; !) is a connected directed edge-weighted graph where S is a set of nodes si 2 S; 1  i  p, representing states of the graph, I is the set of inputs, O is the set of outputs including , E  S  S e is a set of edges, denoted by si ?! sj or es ;s , si 2 S; sj 2 S, and ! is a function from E to I  O, representing the set of edge weights, denoted by x=y, where x 2 I and y 2 O. i

j

If, for the edge weight x=y of an edge euv , if y = , then no output is given for the edge from u to v with the input x. As an example, consider the CSG in Figure 2(b). I contains all combinations of values for i and k, that is I = f(i; 1); (i; 2); (i; 3); (k; 1); (k; 2)g. Similarly, O = f(x; 10); (x; 5); g, S = fs0; s1; s2; s3; s4g and E = fes0;s1 ; es0;s2 ; es0;s3 ; es1;s3 ; es2 ;s4 g Edges to states s3 and s4 have output labels (x; 10) and (x; 5); respectively. The output labels for the other edges are . The edge weights are:

!(s0; s1) = fei;2=g !(s0; s2) = fei;1 =g !(s0; s3) = fei;3=(x; 10)g !(s1; s3) = fek;2=(x; 10)g !(s2; s4) = fek;1=(x; 5)g The state s1 implies that the system has received input i = 2 while the system has received input i = 1 for state s2. The CSG model can be transformed to an incompletely speci ed FSM and therefore, transformed to a completely speci ed FSM to which traditional FSM synthesis can be applied[15]. The CSG is similar to an incompletely speci ed FSM, based on the assumption that no unspeci ed next state is encountered. All unspeci ed outputs, , convey \don't care" outputs and the set of nal states are the set of states where outputs are given. While our system works for deterministic inputs, it is also able to handle nondeterministic or fuzzy systems. Since we present the implementation of our prototyping method for fuzzy systems in Section 4, we include basic fuzzy system terminology here. In fuzzy systems a speci cation is described in conditional sentences (also called relations or rules) using If-Then format. A clause in the if-part (antecedent) contains system input variables while a clause in the then-part (consequence) contains system output variables, describing input requirements and output actions, respectively. The 6

of each variable in a rule is called a linguistic variable. For example, the value of a variable of type temperature could be hot. Hence hot is referred to as a linguistic variable. Instead of a continuous or in nite real or integer value, the domain of values of a linguistic variable must be from a set of nite discrete values, such as fcold, warm, hot g . This domain is called the universe of the linguistic variable. value

The following is an example system: R1 : If the temperature is cold Then set the fan speed to low R2 : If the temperature is medium Then set the fan speed to medium R3 : If the temperature is hot Then set the fan speed to high The above rules require temperature inputs. Each of these inputs will be equal to one of the linguistic variables from the temperature universe: cold, medium, and hot. Similarly, each output will be equal to one of the output linguistic variables of the fan speed universe: low, medium, and high. The system contains one stage since the fan speed is a nal output. (A multi-stage system consists of a collection of single-stage systems such that an output of one stage system is an input of another stage). In a deterministic system where the value of the temperature is not linguistic variable, the calculation of the fan speed would be simple. However, in fuzzy systems three special processes known as fuzzi cation, inference, and defuzzi cation, make the calculation of the outputs more complicated. First, the linguistic variables are not given. Instead they must be calculated from input instances. Furthermore, linguistic variables are not boolean valued variables. Rather each input instance is assigned a strength indicating its relative possibility of being categorized into such a linguistic variable by using a membership function. This process is known as fuzzi cation. During fuzzi cation, for an instance, more than one linguistic variable may be assigned a non-zero strength. Second, since the linguistic variable inputs to each rule are not boolean valued, the outputs will not be boolean valued. Calculating the strength of the output linguistic variables using the strength of the input linguistic variables is known as an inference. Third, since more than one output linguistic variable may be non-zero at a time, the nal output of the system is calculated using a process known as defuzzi cation. Let us examine each of these three points in more detail. An instance of a temperature is normally from a continuous range of possible temperatures. For example, 42.35 degrees is an instance of a temperature, while the allowable range of temperature might be 0 to 7

212 degrees. Each instance in the range of temperatures is assigned a real value in the range [0; 1] for each linguistic variable. This assignment de nes a characteristic function, or membership function, denoted by, X (x); 0  X (x)  1 for an instance x and linguistic variable X . The membership function conveys the possibility of x being considered X . For example, the membership function for hot would convey the possibility of 42.35 degrees being considered hot. Figure 3 shows an example of the membership functions cold ; medium, and hot , representing input linguistic variables, cold, medium, and hot from the temperature universe. µ(t)

µcold

µmeduim

1 0.8

µhot

0.2 0

57

Temperature

Figure 3: Membership function The x-axis represents the input instance while the y-axis represents the membership value of the various membership functions. For the temperature instance t and linguistic variable X , a non-zero membership value for X (t) implies that such an instance may possibly be considered X with strength X (t). Consider the input instance 57 degrees, and the linguistic variable cold. cold(57) returns 0:8. Similarly, medium(57) returns 0:2. This conveys that the temperature instance 57 is more likely to be cold than medium. Let us now consider the inference process using the following rule: If temperature one is cold AND temperature two is medium Then set the fan speed to low. Assume that for given input temperatures, linguistic variable cold for temperature one has a strength of 0.4, while the linguistic variable medium for temperature two has a strength of 0.8. What then should be the strength of the output linguistic variable low? The inference process determines this strength. It could, for example, conclude that the strength of the output variable is the average of the strengths of the input variables. The inference process is chosen by the designer and may be any of a wide variety of functions. Once all outputs of the system are calculated, a defuzzi cation function determines the nal system output. For example, a fuzzy system could determine that there is a 0.4 strength for a low fan speed, and a 0.4 strength for a high fan speed (note that these 8

values need not sum to one). Therefore, the defuzzi cation function might conclude that the fan speed should be set to medium, since medium is between high and low.

3 Conceptual speci cation implementation Recall that the system speci cation is partitioned into conceptual and parameterized components. The conceptual speci cation is the system core which is seldom changed and may be be implemented in hardware. In this section, we describe how to transform the user speci cation into a behavioral network (BN) and model the conceptual speci cation using conceptual state graphs (CSGs), so that traditional nite state machine (FSM) synthesis can be applied to prototype it.

3.1 Behavioral Network construction First, we simplify the input speci cation and transform it into a behavioral network using the following steps. Convert the input speci cation into single-output rule format. A speci cation of the form, R : If : : : Then B1 ; : : : ; Bb , has multiple output actions B1 : : : Bb. It can be broke down into a group of speci cations, each with a single output: R1 : If : : : Then B1, : : : , Rb: If : : : Then Bb

step 1

Convert the speci cation into conjunctive form : If X1 and X2 and : : : and Xm Then Y . The disjunctive clauses A and B in the rule: If A OR B Then C is broken down into two disjunctive rules: If A Then C; and If B Then C . Further details of this conversion can be found in [10].

step 2

Construct a behavioral network according to De nition 2.1. V is fRi : 1  i  ng [ fIj : 8Ij 2 I g [ fOk : 8Ok 2 Og, where n is the total number of single output rules, I is the set of all input domains, and O is the set of all output domains. e Edges E are constructed as follows: Ri ?! Rh 2 E if an output of Ri is required by e Rh. Further, Ij ?! Ri 2 E , if Ri requires an input from the domain Ij . Similarly,

step 3

9

e Ri ?! Ok 2 E , if Ri produces an output in domain Ok . Edge labels are de ned for e edge u ?! v 2 E as a tuple (x; z) where x is v's input variable and z is v's value.

Apply a high level optimization to the BN. Since the number of vertices in the BN determines the total design time for each design iteration, an optimization process is applied to minimize the number of vertices in the BN. During the vertex minimization, vertices with certains relations are combined using union and composition operations. A combined vertex will have input and output edges that correspond to the original vertices. Details of this optimization process can be found in [2].

step 4

Organize the BN by applying a topological sort. The BN is ordered by levels (also called stages). The topological order can be brie y described as follows: if vertex i produces an output which is required by vertex j (i ! j ), i has to be in level k and j in level l, where k < l. Furthermore, the vertices which yield values for the same output domain in the BN are placed in the same level in the sorted BN. Note that in each level, there may be several vertices yielding outputs to di erent domains.

step 5

After sorting we group vertices in the BN. The grouping process can be described as follows: for rule vertices with the same topological order, consider their outgoing label (x; z). All vertices which have the same output variable x are assigned to the same CSG. We denote Gr(x; j ) as a group of vertices at level j with input variable x.

step 6

3.2 CSG construction After we partition the BN vertices into levels and groups, all groups, except input and output groups, are converted to a separate CSG. Each CSG represents the conceptual speci cation of that portion of the system. One of the advantages of this scheme is modularity since each CSG can be veri ed and synthesized individually. Multiple CSGs in the same stage also implies parallelism. Algorithms 3.1 and 3.2 present the conversion process.

Algorithm 3.1 ToCSG

Input: a sorted BN G and its groups Gr

10

Output: CSG Aij for each group i in level j Global variables: the array of CSGs A, and a next state index k begin foreach level j in G do foreach group i in the level j do f /* construct CSG Aij */ Aij :I = l (Gr(i; j )) Aij :O = l (Gr(i; j )) [ fg Aij :S = fs0 g /* mark initial state */ Aij :E = fg Aij :! = fg k=1 /* k=non-output next state number */ call Construct with Gr(i; j ); G; s0 in

out

end

g

This algorithm loops i  j times so that every group of each stage of the BN is converted into a CSG. Aij :I is simply the set of all distinct input labels of the current group, and can be calculated before the construction of the rest of the CSG is started. s0 is the initial state of the CSG.

k is the next non-output state number and is initialized to one for each CSG. E and ! are both set to the empty set. After initializing these values, Algorithm 3.1 calls the Construct procedure to construct the appropriate states, edges and weights for each CSG. Before presenting the details of the Construct algorithm, we rst explain the intuition behind it by showing how a single vertex of a BN could be converted to FSM states. Without loss of generality, assume that all system inputs are ready at the same time and each clause in the if-part of each rule is conjuctive. Under these assumptions, an n-inputone-output vertex is equivalent to a sequence of n state nodes each of which requires one input. Thus for each n-input-one-output vertex, v 2 V of the BN, a collection of state nodes that form an n-edge path, with input labels corresponding to the input labels of v, could be constructed. Figure 4(a) presents an n-input vertex A with one output edge and Figure 4(b) shows a path, denoted by s0 p sn , consisting of state nodes fs0; s1 : : : sng in the new CSG. s0 represents the initial state node. s1 represents the state after receiving input (I; 1) and so on. sn denotes the state that detects the last input (I; n) and emits the output (O; 1). 11

(I1

,1) (I2,1)

A

(O,1) S0

(a) a node in a BN

(In,1)/(O,1)

(I2,1)/Φ

(I1,1)/Φ

,1)

(In

S1

S2

Sn

(b) corresponding state nodes in a CSG

Figure 4: BN to CSG If a BN consists of m nodes each with n distinct input labels and each of them has a di erent output label, the total number of edges in the corresponding CSG is equal to mn. In reality, any two nodes in a BN may require the same, non-distinct, input edge label. Therefore, allowing them to share a single edge will reduce the total number of edges in the CSG. The minimized CSG will simplify the conversion to the corresponding hardware prototype. As long as all input labels of a vertex v in the BN are speci ed to as an edge of the appropriate path in the CSG, the input labels can be arranged in any order. The input labels of the BN have to be selected carefully if the total number of edges in CSG are to be minimized. Algorithm 3.2 proposes a greedy heuristic for this problem.

Algorithm 3.2 Construct

Input: a set of vertices N  V , a sorted BN G, a current starting state sc Output: an update the current state graph Aij begin l max = Extract-Max-Input-Label(N; G) /* nd the input edge label with max occurrences */ if l 6= (NULL) then /* partition vertices into two groups P and Q */ /* P = vertices with input edge label lmax */ e p; with a label; l(u ? P = fp : 9 an edge u ?! !e p) = l max ; u; p 2 V g; Q = N ? P foreach p 2 P do if l max is the only input edge for node p in G then output = output(p); sn = soutlabel /* the output label of vertex p */ else output = ; sn = sk ; nonoutput state = true if sn 62 Aij :S then Aij :S = Aij :S [ fsng if esc sn 62 Aij :E then Aij :E = Aij :E [ fesc;sn g Aij :! = Aij :! [ f(l max =output)g /* add weight to edge esc sn */ e p with label l(e) = l max ; u; p 2 V from G delete input edges u ?! if jP j > 0

12

then if nonoutput state then snext = sk ; k = k + 1; call Construct with P; G; snext

end

if jQj > 0 then call Construct with Q; G; sc

The algorithm rst counts the number of occurrences of each edge label. The maximum occurrence edge label l max is selected. The vertices are then partitioned into two groups: P , containing vertices that have an input edge with the label l max and Q, containing vertices without an edge with the label l max. The algorithm next examines every node in P to determine if it has more than one input edge label. The rst time a node with more than one input edge is found, a unique edge from the current state sc to sn is constructed. (Note that when rst called, sc = s0 : Also note that in this algorithm, for simplicity in de ning a unique state index, two kinds of state indices are introduced. All states are indexed by an integer value except the output states where symbolic names are used.) sn in this case is the next non-output state k. In cases where p has only one input edge, sn is set to an output state where output(p) is the output. This state is added to the CSG if it does not already exist, and an edge is added between sc and sn if necessary. Once all nodes in P have been considered, the input edges with l max are deleted. The nonoutput state ag then determines if there was a node with more than one input edge. If so, a new state snext = sk was constructed during the algorithm. In this case, k is incremented and the algorithm is repeated for P with a new initial state, snext . The algorithm is also repeated for Q using the old initial state. These two recursions stop after all input edges of a given set of vertices are considered. The new CSG is equivalent to the given BN due to the following property.

Property 3.1 Given a BN, G = (V; E; l), let Lv be the input label set of a vertex v and \outlabel" be an output label of a vertex v, v 2 V . A unique sequence of weights,

(l1=); (l2=) : : : (ln=outlabel), of a path s0 p soutlabel in the corresponding CSG, formed from the set Lv , exists if and only if v 2 V . The proof of this property is not shown here due to space considerations. Each path s0 p soutlabel with edge label sequence (l1=); : : : ; (ln=outlabel) of the CSG is created for a vertex v 2 BN with input labels fli : 1  i  ng and output label \outlabel". 13

)

(T,H

(P ,L P

(S,L

A (T,H)

)

T

B

(P,H) (P,M)

)

(S,H) H) (S,

S0 S (P,L)/(S,L)

C

S(S,L)

(a) BN

S1

(P,M)/(S,H)

(T,H)/ Φ (P,H)/(S,H) S (S,H)

(b) Corresponding CSG

Figure 5: Applying the Construct Algorithm Consider the example BN in Figure 5(a) and vertices A; B ,and C . The algorithm rst selects label (T; H ) since there are two vertices requiring such an input label. Thus, e s1 is constructed with P = fA; B g while Q = fC g. In Figure 5(b), an edge s0 ?! weights (T; H )=. Since the initial state of the CSG is s0, the transition from s0 to s1 is constructed and shared by vertices A and B in the BN. The edges with input label (T; H ) of both vertices A and B are eliminated from the BN and the next non-output state k is incremented. Now the current initial state of A and B is s1 , conveying that at state s1 , input (T; H ) has been detected. The algorithm recursively constructs transitions from s1 for the vertices A and B which will distinguish between them. The path s0 p s(S;H ) with labels (T; H )= and (P; H )=(S; H ) corresponds to the vertex B in the BN while the path s0 p s(S;L) with labels (T=H )= and (P; L)=(S=L) corresponds to the vertex A. For the vertex C , because there is the only one input and the output state (S; H ) is already e de ned, only the edge s0 ?! s(S=H ) is constructed. From this CSG, the transitions to states s(S;L) and s(S;H ) emit outputs. After obtaining the CSG, the hardware prototype can be implemented using a traditional nite state machine synthesis. Traditional FSM optimizations may be applied to this CSG to reduce hardware before actual implementation.

14

4 A Design Example 4.1 System design ow for fuzzy systems Since one of the goals of using fuzzy systems is to reduce computational complexity while designing systems, fuzzy systems consist of human knowledge described in rule format. First a user speci es his requirements, e.g., the system input/output and system operations. After a system function is speci ed, designers choose membership functions and a defuzzi cation method. The system is then implemented and its performance evaluated. User Requirement

User Requirement Analysis

Analysis

BN modeling Optimization and Partitioning

Select Defuzzification Method

Testing/Modification

Rule Specification

Select Membership Functions

Rule Specification

(CSG)

Select Membership Functions

Conceptual specification

FSM Implementation and

Select Defuzzification Method

Parameter Specification

Optimization

System Implementation Testing

(a) Traditional fuzzy system design ow

S/W Implementation

(b) Prototyping process of fuzzy systems

Figure 6: Design ow The traditional fuzzy system design ow components are shown in Figure 6(a). This design methodology has the disadvantage of changing the physical design of the rule base during each iteration of the design process. Our methodology is shown in Figure 6(b). Based on our methodology, the speci cation is partitioned into two subcomponents. Since the rule base is rarely changed throughout the design process, our methodology makes it part of the hardware implementation of the conceptual speci cation. The adjustable components of the design are the membership functions and the defuzzi cation method which become part of the software implementation of the parameter speci cation. Our prototyping method increases exibility and facilitates the testing process and shortens 15

the development time.

4.2 The behavioral network and conceptual speci cation We now consider designing a temperature control system for the oven found in [20]. The control system has two temperature input variables x1 and x2 and outputs a new temperature u to which the oven temperature should be adjusted. The following is the set of rules.

x1 is low (x1; L) and x2 is low (x2 ; L) If x1 is low (x1 ; L) and x2 is medium (x2 ; M ) If x1 is low (x1 ; L) and x2 is high (x2 ; H ) If x1 is medium (x1 ; M ) and x2 is low (x2 ; L) If x1 is medium (x1 ; M ) and x2 is high (x2 ; H ) If x1 is high (x1 ; H ) and x2 is low (x2 ; L) If x1 is high (x1 ; H ) and x2 is medium (x2 ; M ) If x1 is high (x1 ; H ) and x2 is high (x2 ; H )

1. 2. 3. 4. 5. 6. 7. 8.

u is high (u; H ) Then u is medium (u; M ) Then u is low (u; L) Then u is high (u; H ) Then u is low (u; L) Then u is high (u; H ) Then u is medium (u; M ) Then u is low (u; L)

If

Then

Figure 7(a) presents the BN for this one-stage set of rules where the system inputs are temperatures x1 and x2 and the temperature output is u. Vertices 1 : : : 8 correspond to rules 1 : : : 8. An edge label is a tuple (x; z) while x is either variable x1 or x2 and z is a linguistic variables with respect to domain(x1 ), domain(x2 ), and domain(u). (x1,M) (x1,H)

I x2

(u,H)

H u,

8 (u,L)

(u,M)

2, (x

s3

/(u

s0

,L)

7

(x2

(u,L)

6

(x1,H)/φ

s2

(x2

,H)

/(u

s(u,M)

(x2,H)/

,H)

(u,H)

)

(u,H)

(x1,M,)/φ

(x2,L)

(x2,H) 5

H u,

(u,L)

(x2,L) 4

)/(

(x2,H)

H

(u,M)

3

2,

(u,H)

(x2,M) 2

)

(x

(x2,L) 1

)/(u,M

s(u,H)

)

s1

(x2,H)

L) /(

(x2,M)

(x2,M

)

)/(u,H

(x2,L

(x1,L)/ φ

,H)

Ix1

(x1,L)

s(u,H)

Ou

)

)/(u,M

(x2,M

(a) Behavioral Network

(b) CSG

Figure 7: Behavioral network and CSG 16

In this example, the BN contains linguistic variables, associated with membership functions, which are parts of the parameter speci cation. Figure 7(b) shows the CSG obtained from Algorithm 3.1 for the BN in Figure 7(a). S is fs0; s1; s2; s3; s(u;M ); s(u;L); s(u;H ) g. The transitions to states s(u;M ) ; s(u;L), and s(u;H ) emit output temperature values medium, low, and high respectively.

4.3 Parameter speci cation Since all input and output variables are temperatures, the same membership function for all variables is used. Figure 8(a) de nes this function. The temperature domain is restricted to between 0 and 500 degrees centigrade. Because of the nature of fuzzy rules, an input instance may re more than one rule, depending on the given membership functions. A mapping relation u is de ned for each instance from U to 2jV j where U is an input instance domain and V is a set of linguistic variables in domain U . Given an input instance i, u(i) returns the corresponding linguistic variable(s). Based on the membership functions de ned in Figure 8(a), T relations are de ned for each of the temperature instances. In this example, according to Figure 8(a), T (x1 )(t) 2 ffH g; fLg; fM g; fL; M g; fM; H gg, for input x1 as well as x2 . For input instance, for x1 = 125, T (x1 )(125)P= fL; M g. We use the weighted average method to defuzzify the output values (z = P((zz))z ) [20].

4.4 Simulation framework According to the fuzzy inference process, a special calculation is required to determine the output strength of each rule given the associated input strengths. Let X (xj ) denote a membership function corresponding to the linguistic variable Xij and the current input instance xj for rule i. Let Y (y) be a membership function corresponding to the linguistic variable Yi and output instance y for rule i. Suppose a rule requires m inputs. Given input instance x1 ; : : : ; xm, for each rule i, Equation 1 calculates the strength of the output Yi ij

i

r = minmj=1X (xj ) ij

17

(1)

while Equation 2 determines a modi ed output function 0Y (y) that is used in the defuzzi cation process i

8 <  (y) if Y (y) < r 0Y (y) = : Y r otherwise i

i

i

(2)

If more than one rules give the same output Yi and therefore generates a new function 0Y (y), each 0Y (y) is combined by using the max operation. i

i

00Y (y) = max(0Y (y)) i

i

(3)

For example, in Figure 7(b), let the temperature instance of x1 be 125 and x2 be 50. Let (x1 ;L)(125) = 0:6, (x1;M )(125) = 0:4, and (x2;L) (50) = 1:0. Hence rule 1 is red and the strength r of the new temperature output (u) being high (H ) is r = min(0:6; 1) = 0:6. Rule 4, which yields the same output as rule 1, is also red with the strength r = min(0:4; 1) = 0:4. The combined strength of (u; H ) for rules 1 and 4 computed by Equation 3 is max(0:6; 0:4) = 0:6. The following algorithm presents the inference process that traverses the CSG.

Algorithm 4.1 TraverseCSG

Input: a CSG A, conclusion function F , input values t1 : : : tm according to the CSG A Output: an output value o begin r = in nity; B [(u; i)] = 0:0; 8i 2 fL; M; H g S = f(s0 ; r; 1)g /* initial state s0 2 A:S */ while S is not empty do (cur state ; r; i) = pop(S ) L = T (xi ) (ti )g foreach l 2 T (xi ) (ti ) do r = min(r; (xi ;l) (ti )) if an edge from cur state to l gives output u then B [u] = max(B [u]; r) else s = StateOf (xi ; l) from cur state x = (s; r; i + 1) push(S; x) o = F (B ) end

Let B be the output bu er and and each element B [p] contain a current cut value (strength) for function p. For instance, B [(u; i)] keeps the current strength that output 18

linguistic variable u is i. Stack S contains the current minimum value r computed by Equation 1. Function StateOf returns the next state according to the given input variable (xi; l), where l is a linguistic variable in T (x ) (ti). Function F de nes the defuzzi cation procedure which is the weight average method de ned above. i

Now let us brie y trace the algorithm. In this example, two input instances, t1 and t2 , are required. Let t1 be 80 and t2 be 85. Let (x1;L) (t1) = 0:93, (x1;M )(t1 ) = 0:1, (x2 ;L)(t2) = 0:89 and (x2 ;M )(t2 ) = 0:07. Starting from the initial state s0 , L = T (x1 )(80) = fL; M g. For (x1 ; L), the next state is s1; r = 0:93 while i + 1 = 2. Hence, the tuple (s1; 0:93; 2) is pushed onto S . Similarly, for (x1 ; M ), the tuple (s3; 0:07; 2) is saved to S . During the next iteration, pop(S ) sets cur state = s3 ; r = 0:1; i = 2 where T (x2) (t2 ) = T (x2 ) (85) = fLg. The transition from s3 with the input (x2 ; L) gives an output (u; H ). Now r = min(r; (x2;L)(85)) = min(0:1; 0:89) = 0:1 and, therefore, B [(u; H )] = 0:1 . Next, the algorithm pops (cur state = s1 ; r = 0:93; i = 2). For t2 = 85, T (x2 )(85) = fL; M g. From state s1 with (x2 ; L) as the input, the transition gives output (u; H ) with strength r = min(0:93; 0:89) = 0:89 and the overall B [(u; H )] = max(B [(u; H )]; 0:89) = max(0:1; 0:89) = 0:89. Finally, the transition from state s1 with input (x2 ; M ) yields output (u; M ) with the strength of the output temperature being considered medium equal to min(0:93; 0:07) = 0:07. The graphical result presenting the cuts for the output membership functions M and H is shown in Figure 8(b). µ L

µ 1.0

M

H

µ 1.0

L

M

H

1.0

0.89

0.89

0.07 0

70

210

350

500

(a) Temperature functions

0

70

343

M

H

0.07 210

350

500

(b) a cut for each output

0

70

210

350

500

(c) After defuzzi cation

Figure 8: Membership functions The area bounded by both output membership functions medium and high and their strengths are shown in Figure 8(c). By using the weighted average method to defuzzify, the output temperature u = z = 343 is obtained. This output maybe fed back to the system and the bu ers may be reset to re-run the system. If the system does not work properly, designers may go back and change the membership functions or the defuzzi 19

cation method. initial system input (i1,..in) software simulator Input counter Generator

(combinational circuit)

next_state output

Binary to Decimal

Hardware Prototype

Fuzzification output feedback next_state state_buffer (S) output output_buffer (B)

Defuzzification

State counter Generator reset buffer

system output (o1,..,ok)

Figure 9: Simulation framework Figure 9 presents the integration of each of the design components. The hardware prototype includes the CSGs transformed into FSMs and to combinational circuits. The input counter generator produces proper binary-encoded inputs to the circuit according to each software input variable. Similarly the state counter generator produces proper binary state to the circuit. The binary-to-decimal converter reverses this process. The software simulator includes parameterized components such as membership functions and defuzzi cation methods. It requires state bu er S and output bu er B to collect all possible states and outputs. The reset signal is provided in order to clear the bu ers.

5 Conclusion One of the most important issues in system design is to make the design easy to adjust for system testing and yield rapid implementation. In this paper, we propose the new design methodology which partitions system components into conceptual and parameterized speci cations. The conceptual speci cation de nes the core of system speci cation which is rarely changed and may be implemented as a hardware prototype. Parameterized components are speci ed in software in order to be easily edited for the system tuning. This method actually integrates hardware and software capability, yielding exibility and re-speci cation and shorten prototyping time. A given speci cation is transformed into a behavioral network. This model exhibits global system behavior, where an optimization process can be applied in order to minimize the speci cation, and implies parallelism between system components in the same stage. The conceptual speci cation of each 20

subcomponent is implemented by a conceptual state graph (CSG), which can be easily transformed into hardware prototype by traditional FSM synthesis and test individually.

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[13] P. Kission, H. Ding, and A. A. Jerraya. Accelerating the design process by using architectural synthesis. In Proceedings of the Fifth International Workshop on Rapid System Prototyping, pages 205{212, 1994. [14] G. Koch, U. Kebschull, and W. Rosenstiel. A prototyping environment for hardware/software codesign in COBRA. In Proceedings of the Third International Workshop on Hardware/Software Codesign, pages 10{16, 1994. [15] Z. Kohavi. Switching and Finite Automata Thoery. McGraw-Hill, 1979. [16] B. Lin, S. Vercauteren, and H. D. Man. Embedded architecture co-synthesis and system integration. In Proceedings of the Fourth International Workshop on Hardware/Software Codesign, pages 2{9, 1996. [17] E. H. Mamdani. Advances in linguistic synthesis of fuzzy controllers. InternationalJournalMan Machine Studies, 8:669{678, 1976. [18] S. Mohanty and P. A. Wilsey. Rapid system prototyping, system modeling and analysis in hardware-software codesign environment. In Proceedings of the Sixth International Workshop on Rapid System Prototyping, pages 154{160, 1995. [19] J. Moore and M. A. Manzoul. An interactive fuzzy CAD tool. IEEE Micro , pages 68{74, April 1996. [20] T. J. Ross. Fuzzy Logic with Engineering Applications. McGrawHill, 1 edition, 1995. [21] M. Togai and H. Watanabe. Expert system on a chip: An engine for real-time approximate reasoning. IEEE Expert, Fall 1986. [22] M. Voss, T. B. Ismail, A. A. Jerraya, and K. H. Kapp. Towards a theory for hardware/software codesign. In Proceedings of the Third International Workshop on Hardware/Software Codesign, pages 173{180, 1994.

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