Real-Time Implementation of an Adaptive Noise Canceller based on MicroBlaze Soft Processor Mohammed Bahoura and Hassan Ezzaidi Abstract— In this paper, two architectures based on the MicroBlaze soft processor are implemented on FPGA for realtime adaptive noise cancellation. The first architecture uses the least mean square (LMS) algorithm with 16-bit fixed-point fractional format, while the second one is based on a scaled version of the normalized least mean square (NLMS) algorithm with 16-bit fixed-point integer format. Those architectures were applied to remove, in real-time, the 60 Hz interference from electrocardiogram (ECG) signal with various levels of the reference input.
in some unknown way with the corrupting noise n0k . The reference input is processed with the adaptive filter that iteratively adjusts its impulse response to minimize the mean square error (MSE) between its output and the primary input. A. Least mean square (LMS) The least mean square (LMS) is the most used algorithm to iteratively minimizing this error (MSE). For an N − 1 th order adaptive filter, the LMS algorithm can be expressed as:
I. I NTRODUCTION The Adaptive noise canceller (ANC) [1] is an interesting application of the adaptive filter that has been used in a wide range of signal processing systems. They include power line interference (50/60Hz) elimination from ECG signals, fetal electrocardiogram (ECG) extraction, echo cancellation in long-distance telephone and satellite communications, adaptive noise cancellation for hearing aids, ambient noise reduction from breath sound measurements, etc. The adaptive noise canceller is based on a finite impulse response (FIR) filter whose coefficients are automatically adjusted using a gradient descendant algorithm. The least mean square (LMS) algorithm is commonly used to minimize the coast function (error). In the last decade, several architectures are proposed to implement the LMS-based algorithm on field-programmable gate array (FPGA) using hardware [2], [3], [4] or hardware/software approaches [5]. The normalized version of this algorithm (NLMS) has been proposed to solve the problem of stability related to the scaling of its input. However, its hardware implementation, using a reduced number of bits, become difficult when its input is large. In this paper, we propose a scaled version of the NLMSbased algorithm to implement it easily on hardware. LMS and scaled NLMS-based filters have been implemented on FPGA for real-time noise cancellation. II. A DAPTIVE N OISE C ANCELLATION Figure 1 shows a block diagram of an adaptive noise canceller that consists of two input signals and an adaptive filter. The primary input contains the wanted signal sk plus the uncorrelated noise n0k . The reference input is the noise n1k which is uncorrelated with the signal sk but correlated M. Bahoura is with the Department of Engineering, Universit´e du Qu´ebec a` Rimouski, 300, all´ee des Ursulines, Rimouski, Qc, Canada, G5L3A1.
Mohammed
[email protected] H. Ezzaidi is with the Department of Applied Sciences, Universit´e du Qu´ebec a` Chicoutimi, 555, boul. de l’Universit´e, Chicoutimi, Qc, Canada, G7H 2B1.
[email protected]
yk =
N −1 X
wi,k xk−i = wkT xk
(1)
i=0
ek = dk − yk
(2)
wk+1 = wk + 2µek xk
(3)
where the vector wk = [w0,k , w1,k , . . . , wN −1,k ]T represents the weights of the adaptive filter at time k, xk = [xk , xk−1 , . . . , xk−N +1 ]T are the last N samples of the reference input from time k, and µ is a positive parameter controlling the stability and the convergence speed. B. Normalized least mean square (NLMS) The normalized least mean squares (NLMS) algorithm is a variant of the LMS one that has been proposed to solve the problem of stability related to the scaling of its input. It is defined by: wk+1 = wk + 2
µ ek x k kxk k2
(4)
where kxk k2 = xTk xk is the Euclidian norm of xk . The filter output yk and error ek are defined by (1) and (2), respectively. C. Scaled Normalized Least Mean Square (SNLMS) The scaled normalized least mean square (SNLMS) is obtained by scaling the filter weights wk of the NLMS algorithm by an integer constant A to obtain a new large filter weights hk = Awk . yk = wkT xk = hk+1 = hk + 2A
1 T h xk A k µ ek x k kxk k2
(5) (6)
where the scaling constant A can be a power-of-2 to replace multiplication and division by right and left shifting, respectively. The filter error ek is defined by (2).
Fig. 1.
Adaptive noise canceller block diagram.
III. FPGA I MPLEMENTATION The proposed architecture is implemented on FPGA using the Embedded Development Kit (EDK). This software tool incorporates the Xilinx Platform Studio (XPS) for configuring the hardware portion and the Xilinx Software Development Kit (SDK) for configuring the software one. A. Hardware Implementation The hardware part of the design is created using the Base System Builder (BSB) wizard in XPS. It is build around the MicroBlaze soft processor by combining blocks of code called cores inside a Xilinx FPGA. This approach provides a highly flexible architecture, delivering the exact processing system we need at the lowest system cost possible. The MicroBlaze is a 32-bit Harvard Reduced Instruction Set Computer (RISC) architecture optimized for implementation in Xilinx FPGAs. It uses separate 32-bit instruction and data Local Memory Bus (LMB) to be connected to the high-speed on-chip dual-port BRAM and Processor Local Bus (PLB) to communicate with the on-chip peripherals. As shown in Fig. 2, the proposed architecture is build using the following cores: • Microblaze: This soft processor is the main component of the implemented architecture. • TIMER: This Timer/Counter is a 32-bit timer module that attaches to the PLB bus. It is used to generate an interrupt every 2777.77 us, corresponding to the sampling frequency (360 Hz) of the ECG signal. • INTC: This Interrupt Controller is used to concentrate multiple interrupt inputs from peripheral devices to a single interrupt output to the system processor. In this application, it receives interrupt only from the TIMER. • SPI: The Serial Peripheral Interface (SPI) connects to the PLB bus and provides a serial interface to SPI devices. The SPI protocol is full-duplex synchronous channel that supports four signal interface (transmit, receive, clock and slave-select) between a master and a selected slave. Configured as master, the two first modules (SPI0 and SPI1) are used to read data from the two 12-bit analog-to-digital converters (ADCs) available on the add-on Digilent PMOD-AD1. The third one (SPI2) is used to write the output on one the two 12bit digital-to-analog converters (DACs) available on the PMOD-DA2 peripheral. It can be noted that the PMOD-AD1 has two simultaneous ADC channels, each to convert an analog input signal
Fig. 2. Hardware/software architecture based on MicroBlaze soft processor for adaptive noise cancellation. The WaveForms and the Analog Discovery tools are used to generate and acquire the analog input/output signals.
ranging from 0-3.3 V (or 5 V) to a 12-bit unsigned digital value. However, these two ADC chips have common clock (CLK) line and common active low select-slave (SS). This requires to link the CLK lines of SPI0 and SPI1 by an OR gate and their SS lines by an AND gate. B. Software Implementation The software part of the design is programmed using the SDK tool. The code corresponding to the filtering techniques are written in C language and compiled in order be executed by the MicroBlaze. The processor starts by initializing the on-chip peripherals (SPI0, SPI1, SPI2, INTC and TIMER). To operate at a defined sampling frequency (360 Hz), the processor is periodically interrupted to execute the filtering function related to a given algorithm. The unsigned 12-bit digital data provided by ADC can be interpreted differently. It can be seen as a 16-bit fixed-point fractional (FPF) format ranging from 0 to 0.999755859375; also it can be seen as a 16-bit fixed-point integer (FPI) format ranging from 0 to 4095. The first format (FPF) will be used to implement the LMS-based algorithm. The second one (FPI) will be used to implement the NLMS or SNLMS-based algorithms. 1) LMS-based filtering: As described in the Listing 1, the LMS Filtering function read inputs from the ADCs, applied the LMS-based adaptive canceller and send the output to the DAC. All data are interpreted as signed 16bit fixed point format with the binary point at position 15.
The 32-bit multiplication result is truncated by shifting it 15 bits to the right. 2) SNLMS-based filtering: As described in the Listing 2, the SNLMS Filtering function read inputs from the ADCs, applied the SNLMS-based adaptive canceller and send the output to the DAC. All data are interpreted as signed 16-bit fixed point format with the binary point at position 0. Weights of the filter are scaled/unscaled by shifting them 12 bits to right/left and normalized. 3) NLMS-based filtering: The LMS Filtering function is the same as the last one, except scaling/unscaling.
Listing 1.
C pseudo-code of the LMS-based filtering
void LMS Filtering ( void ) { X i n t 1 6 x [N] , d , y , e , w[N ] ; / / Read i n p u t s from ADC0 and ADC0 ReadBuf1 >18); }; W r i t e B u f = ( X u i n t 1 6 ) ( ( e > >4)+750); / / U n s c a l i n g + o f f s e t W r i t e B u f −−> SPI3 ; / / W r i t e o u t p u t t o DAC0 }
Listing 2.
Fig. 3. Clean electrocardiogram (ECG) signal (top) and its corrupted version (bottom) obtained by adding 60 Hz interference.
Pseudo-C code of the SNLMS-based filtering
v o i d S N L M S F i l t e r i n g ( v o i d ){ X i n t 1 6 x [N] , d , y , e , w[N ] ; X i n t 3 2 norm ; / / Read i n p u t s from ADC0 and ADC0 ReadBuf1 SPI3 ; / / W r i t e o u t p u t t o DAC0 }
IV. E XPERIMENTS AND R ESULTS
Fig. 4. Large-amplitude (2 V) reference input xk and filtered output ek recorded by the 2-channel Scope of the Analog Discovery board for the LMS-based filter (top) and the SNLMS-based one (bottom).
simultaneously generated by the Analog Discovery module using the WaveForms software running on a laptop. Using the custom or player mode with its appropriate sampling frequency, the channels must be synchronized. Fig. 3 presents a clean ECG signal (top) and its corrupted version (bottom) acquired by loop back at the Analog Discovery module.
A. Setup
B. Experimental Results
The implemented architectures are tested in real-time environment using corrupted ECG signal (dk ) and 60 Hz reference noise (xk ). Sampled at 360 Hz and previous stored on the hard disk, their corresponding analog signals are
Figures 4 and 5 represent the filtering results obtained by the LMS-based algorithm (top) and by the SNLMS-based algorithm (bottom) for large-amplitude (2 V) and smallamplitude (0.1 V) reference, respectively. These adaptive
Fig. 5. Small-amplitude (0.1 V) reference input xk and filtered output ek recorded by the 2-channel Scope of the Analog Discovery board for the LMS-based filter (left) and the SNLMS-based (right).
Fig. 6. Timing diagram of SPI control signals transmitted to ADCs of PMOD-AD1 to read dk and xk inputs, and those transmitted to DAC of PMOD-AD2 to write ek for the LMS-based noise cancelation. These signals are obtained by the Logic Analyzer of the Analog Discovery board for read-ADC/filering/write-DAC in bursts (INTC disabled). The time consumption of the LMS-based filtering is estimated to 41 us.
Fig. 7.
Same as Fig.6 but for the SNLMS-based noise cancelation. The time consumption of the SNLMS-based filtering is estimated to 135 us.
filters remove efficiently the additional noise without disturbing the original ECG signal. Figs 6 and 7 show the CLK and SS lines of the ADC and DAC converters obtained by the Logic Analyzer of the Analog Discovery. They allow us to experimentally estimate the time consumed by each algorithm. V. C ONCLUSION The original LMS-based adaptive filter has been successfully implemented on FPGA to remove, in real-time, 60 Hz interference from ECG signal for various levels of this reference. The NLMS-based filter has been implemented but it was not able to remove noise because the filter weights are not sufficiently coded by the chosen fixed-point integer format. A scaled version of the NLMS-based algorithm has been proposed and applied to remove noise in real-time.
R EFERENCES [1] B. Widrow, J. R. G. Jr, and J. M. McCool, “Adaptive Noise Cancelling: Principles and Applications,” Proceedings of the IEEE, vol. 63, no. 12, pp. 1692–1716, 1975. [2] M. Bahoura and H. Ezzaidi, “FPGA-Implementation of Parallel and Sequential Architectures for Adaptive Noise Cancelation,” Circuits, Systems, and Signal Processing, vol. 30, no. 6, pp. 1521–1548, Dec. 2011. [3] Y. Yi, R. Woods, L. K. Ting, and C. F. N. Cowan, “High Speed FPGABased Implementations of Delayed-LMS Filters,” Journal of VLSI Signal Processing Systems for Signal, Image, and Video Technology, vol. 39, no. 1-2, pp. 113–131, 2005. [4] R. Ramos, A. M`anuel-L`azaro, J. Del R´ıo, and G. Olivar, “FPGA-Based Implementation of an Adaptive Canceller for 50/60-Hz Interference in Electrocardiography,” IEEE Trans. Instrum. Meas., vol. 56, no. 6, pp. 2633–2640, 2007. [5] A. Elhossini, S. Areibi, and R. Dony, “An fpga implementation of the lms adaptive filter for audio processing,” in IEEE International Conference on Reconfigurable Computing and FPGA’s, 2006. ReConFig 2006., Sept 2006, pp. 1–8.
