Reconfigurable detector architectures using conventional and on-line arithmetic for mobile communication receivers
Sridhar Rajagopal
Joseph R. Cavallaro
Abstract
This paper presents two different detector architectures that have varying benefits with Signal to Noise Ratio (SNR) at the receiver. Soft decisions (high precision output from the detector) are needed by the decoder for low SNR while hard decisions can be used to attain higher data rates in case of high SNR or voice. A conventional arithmetic detector using carry save adders for soft decisions is first presented that achieves a 2.12 Area-Time (AT) improvement against a base case conventional arithmetic implementation. For hard decision outputs, a truncated on-line arithmetic detector is presented that attains a 3.94 AT improvement against the same implementation for an 8 bit input precision (with quadratic benefits with increasing input precision). A mobile communication receiver can thus reconfigure between these two different proposed architectures to attain 1.62 3.94 higher data rates depending on the SNR. This technique can also be applied to reconfigure the implementation of other receiver algorithms such as the decoder.
Submitted to 36th Asilomar Conference on Signals, Systems and Computers, Nov 2002
Keywords: 1. ASIC and FPGA design 2. DSP algorithms, architectures, hardware, and applications 3. Wireless communication systems and networks
Corresponding author: Department of Electrical and Computer Engineering, Rice University, Houston, TX 77005, phone : (713)-348-2256, fax: (713)-348-6196, email:
[email protected] Department of Electrical and Computer Engineering, Rice University, Houston, TX 77005, email:
[email protected]
I.
Introduction
Designing fast detector architectures to attain 10 100 Mbps data rates in future wireless communication
systems is an important research problem. The decoder in the wireless receiver has a target Bit Error Rate (BER) of
for data and
for voice. For the decoder to work well in low Signal to Noise Ratio (SNR), it needs
high precision detector inputs (soft decisions). For voice, which has greater error tolerance, or to achieve data rates when the SNR is high, low precision outputs (hard decisions) from the detector may be sufficient. Though speed may not seem important for voice, the circuit could then be put in a power down mode to save power. Hence, a reconfigurable architecture such as Chameleon [1] could reconfigure between an optimized detector using conventional arithmetic that provides soft decisions at low SNR and another optimized detector using online arithmetic to provide hard decisions for voice or at high SNR to attain higher data rates. The Viterbi decoder [2] may also similarly reconfigure from using multipliers to calculate Euclidean distances to a lower complexity faster arithmetic structure using XOR gates to calculate Hamming distance for hard decisions inputs from the detector. To explain our concept, we choose a code matched filter detector for Code Division Multiple Access (CDMA) based wireless communication systems with Binary Phase Shift Keying (BPSK). This algorithm is one of the simplest and most popular algorithms used both in the mobile handset as well as in base stations [3] and can also be used as an initial estimate for other advanced detection algorithms [3–5]. Our work is also applicable to other advanced algorithms for detection with higher modulation schemes, as these algorithms can also be reconfigured between conventional and on-line arithmetic versions to provide hard and soft decisions. Figure 1 shows the block diagram of a mobile communication receiver. Let
and
be the channel estimate of the user.
spreading gain or spreading factor). Let "!$#
&%
('
be the received signal
is the length of the spreading code (also known as be the ) bit of the user to be detected. Then, the
system can be formulated as: * ,+
- #/.0 21
(1)
where . is the Additive White Gaussian Noise (AWGN). The single user matched filter detector with hard and soft decision outputs can be shown to be [3]: 3 +
5 4 *
(Soft decisions)
(2)
-
+
67)98;: < 3 ;= 1
(Hard decisions)
(3)
The architecture of the matched filter detector exhibits an inner product structure [6] for computations. The base case conventional arithmetic architecture is shown in Figure 2(a). For soft decisions, we minimize the carry propagation time by making the multiplier produce outputs in carry save form. The carry save outputs of all the multipliers are then combined using a 2*N:2 compressor with a final carry propagate adder (CPA) at the bottom in Figure 2(b). For hard decisions, finding the sign implies extraneous computations in a conventional number
1
Antenna
Hard decision b or soft decision y Detection
r RF Unit
A/D
Decoded information bits
Decoding
A
Demux
Channel Estimation
Figure 1: Block diagram of a mobile communication receiver. The detector produces either single-bit precision outputs (hard decisions) of the detected bits or higher precision outputs (soft decisions). The final decision on the transmitted information is made at the decoder. system as the sign is obtained only at the end due to the Least Significant Digit First (LSDF) nature of computations. On-line arithmetic [7], based on a signed digit number representation, provides Most Significant Digit First (MSDF) computation. Hence, the computations can stop after the first non-zero MSD (sign) is computed and additional computations for successive digits are avoided as in Figure 2(c). The on-line arithmetic modules, being maximally redundant, can accept input in conventional number representations. The need for back conversion to a conventional number system is also not required as the sign of the digit represents the detected bit. Though on-line arithmetic can be used for soft decisions too by using additional MSDs, it has a higher area-time (AT) overhead as compared to a conventional arithmetic system using carry save adders (CSAs) due to the redundancy in the number system. II.
A truncated on-line arithmetic detector
We have presented the basic on-line matched filter detector architecture in [4]. In this work, we truncate the on-line detector to stop the computations immediately after the first digit has been received. However, if the first digit is zero, the detector output could be erroneous as further digits are needed to determine the sign. Hence, the throughput speedup due to the truncation of the first digit is at the expense of increase in error probability as in Figure 3. The error probability
4
for an optimal detector for BPSK [8] is given by
where 5
