Reliability assessment of electrostatically driven MEMS devices

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Reliability assessment of electrostatically driven MEMS devices: based on a pulse-induced charging technique

This article has been downloaded from IOPscience. Please scroll down to see the full text article. 2012 J. Micromech. Microeng. 22 045016 (http://iopscience.iop.org/0960-1317/22/4/045016) View the table of contents for this issue, or go to the journal homepage for more

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IOP PUBLISHING

JOURNAL OF MICROMECHANICS AND MICROENGINEERING

doi:10.1088/0960-1317/22/4/045016

J. Micromech. Microeng. 22 (2012) 045016 (10pp)

Reliability assessment of electrostatically driven MEMS devices: based on a pulse-induced charging technique Jinyu J Ruan 1,2 , David Tr´emouilles 1,2 , Fabio Coccetti 1,2 , Nicolas Nolhier 1,2 , George Papaioannou 1,3 and Robert Plana 1,2 1 2 3

CNRS, LAAS, 7 Avenue du Colonel Roche, F-31077 Toulouse, France Universit´e de Toulouse, UPS, INSA, INP, ISAE, LAAS, F-31077 Toulouse, France Solid State Physics Section, University of Athens, Panepistimiopolis Zografos, Athens 15784, Greece

E-mail: [email protected], [email protected], [email protected], [email protected], [email protected] and [email protected]

Received 15 June 2011, in final form 4 October 2011 Published 19 March 2012 Online at stacks.iop.org/JMM/22/045016 Abstract The charging mechanism of electrostatically driven MEMS devices was investigated. This paper shows experimental results of (i) electrostatic discharge (ESD) experiments, (ii) charging mechanism modelling and (iii) Kelvin probe force microscopy tests. It highlighted dielectric failure signature occurred under ESD events and allowed understanding of the underlying breakdown mechanism. A further study of the charging effect in conditions below the breakdown was carried out. A new approach to explore trapping phenomena that take place in thin dielectric used for electrostatic actuation is reported. Indeed a pulse-induced charging (PIC) test procedure aimed at reliability assessment of electrostatically actuated MEMS devices is presented. Based on this method, a procedure for carrying out stress testing was defined and successfully demonstrated on capacitive MEMS switches. In this case, high-voltage pulses were applied as stimulus and the parameter Vcapamin , which is directly related to the charging of the insulator layer, was monitored. The PIC stress test results were correlated with conventional cycling stress ones. Finally, temperature-dependent measurements, ranging from 300 up to 355 K, were reported in order to validate the thermal-activated behaviour of the test structures. According to an Arrhenius model, the given reference material showed an activation energy of around 0.77 eV. (Some figures may appear in colour only in the online journal)

1. Introduction

understand the effects. The sensitivity of RF switches to electrostatic discharge (ESD) and electrical overstress (EOS) was reported in the early 2000s [8]. Failure analyses showed that due to small gap spacings and the geometry of the structures, strong localized electric fields were created and led to electrical shorts. Since then additional results were published and showed; the stiction mechanism induced by dielectric breakdown in Ohmic switches [9], arcing and charging mechanisms in capacitive switches [10], electrical and mechanical failure mechanisms in capacitive switches [11] and the analytical model of ESD in MEMS [12]. Issues such as surface roughness of the contact area, asperity size, adhesion or cold-welding and geometry and the

In the last decade, RF-MEMS have emerged as a very promising technology in the telecommunication [1], aerospace [2], radar [3] and energy harvesting [4] industries. Besides, they are compatible with current CMOS [5] and GaAs-MMIC [6] technologies for maximum integration levels. However, the dielectric failure rates of the electrostatically driven devices are still a limitation factor to widespread expansion into a wide range of applications [7]. Furthermore, integration scales are getting smaller due to decreasing component size. Hence, these structures will yield electrostatic and/or electromagnetic strains that are necessary to investigate and 0960-1317/12/045016+10$33.00

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© 2012 IOP Publishing Ltd

Printed in the UK & the USA

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(a)

(b)

Figure 1. Block diagram of (a) TLP and (b) HBM setup including capacitance monitoring.

tester. The breakdown and the charging mechanisms were investigated. Furthermore, the pulse-induced charging (PIC) methodology was introduced and the generated ESD-like pulse was described. Finally, the correlation was made between pulse charging condition and conventional stress condition (i.e. cycling). Temperature variation experiments showed the thermal activation of the tested structures and the activation energy of 0.77 eV was determined using an Arrhenius fit.

number of asperities in contact are critical in understanding contact mechanics. Furthermore, in the particular case of shunt switches, one of the main failure mechanisms observed is charge accumulation in dielectric materials. In fact, charge is deposited into and through the dielectric material. Hence, the residual charge in the dielectric may increase or decrease the actuation voltage depending on the polarity of the charge and applied bias. This failure mechanism occurs over time and over a repeated number of cycles. By constant voltage increases, the dielectric will break down and result in catastrophic device failure. Up to now, the conventional lifetime test method is based on pull-out and pull-in cycling. In this procedure, arbitrary voltage waveform profiles were used such as simple square wave or two-step wave. The results of these intensive investigations using the cycling method led to the conclusions that the device lifetime • decreases exponentially with the magnitude of the pull-in voltage [13] and • depends only on the cumulative pull-in time and not on the cycling frequency or duty cycle [14]. In spite of these conclusions, the only method attempted to provide an alternative tool for MEMS lifetime prediction is the use of continuous dc stress [13, 15]. Further in [16], dc stress with temperature acceleration has been shown using MIM capacitors. Unfortunately, these tests are very time consuming, which means that a demonstrator that shows a long lifetime feedback of 10 years cannot be so easily obtained. The purpose of this study is to identify the failure mechanism before dielectric breakdown and determine how much charge is trapped in the dielectric material in order to model the time to failure. This paper deals with ESD and Kelvin probe force microscopy (KPFM) testing and ended up with a novel testing methodology. Two ESD standards were used: the transmission line pulsing (TLP) generator and the human body model (HBM)

2. Experimental and theoretical background 2.1. ESD testing For ESD evaluation of capacitive RF-MEMS, we have used two types of tester (figure 1). The first technique is TLP testing. It is a 50  impedance wafer level system, providing rectangular pulse of 100 ns width with 300 ps rise time. The second tester is HBM ESD qualification simulator from Hanwa Corporation, which provides a 500 ns width doubleexponential pulse signal on a short load (with 10 ns rise time). 2.1.1. TLP generator. • The first technique is TLP testing (figure 1(a)), the one used in this experiment was a 50  impedance wafer level system, providing rectangular pulse of 100 ns width with 300 ps rise time. The TLP pulses were applied between the signal line and the ground when the membrane was in the upstate configuration. To determine the failure signature, successive zaps ranging from 10 to 400 V were applied. It has to be noted that the actuation voltage of these devices is around 30 V. But, from the device mechanical point of view, the TLP is a very fast transient (100 ns) that cannot induce movement of the membrane (switching time 20–30 μs). It was verified using a laser spotlight pointing on the membrane, with a photodetector to read out the reflected ray during the stress. 2

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Table 1. Deposition conditions of the SiN. Deposition Temperature Pressure ˚ Frequency rate (A/min) (◦ C) (mTorr) LF-Si3 N4 50 kHz MF-Si3 N4 50 kHz– 13 MHz HF-Si3 N4 13 MHz

1238 136

200 200

650 900

110

200

1000

the signal line of the device. The results are summarized in figure 3. The slope constituted an index of how sensitive the dielectric material was against disruptive events. The log–log scale of figure 3 indicated a powerlaw dependence of the shift, the parameter Vcapamin on the accumulated stress, and the corresponding expression is as follows: nTLP VTLP (NTLP ) = V0,TLP · NTLP ,

Figure 2. TLP current–voltage curves of two different kinds of capacitive RF-MEMS switches.

(1)

where V0,TLP is the amplitude factor that depends on the material, NTLP is the number of TLP pulses and nTLP is the power-law exponent that corresponds to the slope in the log–log plot and it is related to charge kinetics in the material. The results showed that in contact-less charging, LF material is dominated by the injected charges, while MF material is dominated by dipole orientation and intrinsic mobile charge displacement. A more detailed discussion is made in subsection 2.1.3.

• The TLP-ESD pulses were applied following the stress-tofailure procedure, i.e. the magnitude of the TLP increased step by step until failure occurred. Figure 2 shows a typical failure signature of RF-MEMS capacitive switches. Three different regimes were distinguished: an area where the device is still functional after the stress, followed by soft and hard failure areas. The functional zone indicates the highest TLP magnitude that the component can withstand and that will not affect its behaviour. Soft failures occurred for a voltage around ∼400 V. Soft failure defined a device that is still functional after the ESD stress, according to RF-measurements (it still works as a switch and performs its RF function). Further investigation showed that soft failures originate from electric arc that occurred between the bottom electrode and the upper membrane, due to very high current creating electric arc breakdown channel and resulting in melting of the metal and the dielectric. This kind of electrical breakdown was first observed in 1889 under Paschen’s law [17] and it was theoretically demonstrated by Townsend in 1925 [18]. However, at that time, the gaps were higher than 10 μm. The air gap in capacitive MEMS is often below 5 μm; the original Paschen’s curve is no longer valid. In contrast, the modified Paschen’s curve by Schaffert [19], Dhariwal [20] and Wallash [21] seemed to be a good guide for taking into account ESD sensitivity in MEMS planar geometry designs. Comparing silicon structures with aluminium nitride ones (in figure 2), in this particular case, their difference in the failure signature was dominated by the air gap (considering that it could also depend on surface roughness, asperities, shape and geometry). • In the second part of the experiment, investigations of the charging behaviour were conducted. In order to simplify the analyses, samples were limited to silicon nitride devices, three differently processed PECVD Si3 N4 (LFSiN, MF-SiN and HF-SiN). The deposition conditions of the nitrides are given in table 1. The arbitrary chosen polarity convention was positive pulses applied through

2.1.2. HBM tester. • The equipment used for the investigation of HBM effects was a wafer level HBM tester from Hanwa Corporation, able to monitor voltage and current waveforms during the stress procedure. It was not possible to use the voltage probe in this case for two reasons. On one hand, the capacitor of the probe (8 pF) will affect the measurements ahead of the capacitance of the DUT. On the other hand, the impedance of the DUT is much higher than that of the voltage probe one, leading to an unrealistic leakage current through the probe discharging the HBM tester capacitance. Therefore, the voltage probe was removed and only current waveform measurements I(t ) were performed during the discharge. The HBM bench uses a 100 pF charged capacitance and 1.5 k serial resistance (figure 1(b)), leading to a current transient with 500 ns decay time. The HBM standards define the shape of a human body discharge into a short circuit (the tester behaves like a current generator). In our case, the DUT is equivalent to a capacitor, which means that the tester becomes a voltage generator. It should be underlined that this must happen if a real charged human body touches the device. Actually, depending on the precharged voltage, the device is equivalent to a capacitor or a variable capacitor due to the air gap of the component (i.e. upstate position is an open circuit and downstate position is a capacitor). So, when the 100 V precharged tester is connected to the 3

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Figure 3. The shift of Vcapamin as a function of positive TLP pulses, for structures with LF-SiN, MF-SiN and HF-SiN dielectrics.

(a)

(b)

(c)

Figure 4. Current waveform responses as a function of HBM failure signature.

MEMS, the 100 V voltage was almost entirely applied to the device due to its very small capacitance compared to the HBM one. This voltage remained approximately for ∼10 ms. In fact, the 10 ms discharge time is determined by the HBM system, i.e. there are two relays: one to apply the discharge and another to connect the device to ground; so, it corresponds to the duration in between the activation of the two relays. The pulse is consistently 10 ms long and does not vary with different devices. • In order to detect the breakdown due to HBM, the following experiment was performed; one device receives cumulative HBM stress from 10 V to 1 kV, using variable voltage steps. The results are shown in figure 4. For HBM magnitudes below ∼400 VHBM , a negative current transfer is measured after each stress (figure 4(a)). This current signal corresponded to the signal shorted to ground after the ∼10 ms discharge (it is from the second relay springing back open and not the current path across the device). The current waveforms obtained in the soft failures region (figure 4(b)) clearly show the current flowing through the device during the HBM pulse (occurred in between the two relays). Finally, the hard failures region (figure 4(c)) appears when the magnitude reaches above 1 kVHBM . The current waveform corresponds to a low-impedance device (short circuit). An optical verification after the stress procedure did not show any degradation. Therefore, the failure

analysis (FA) was performed by removing the membrane manually. Indeed, it showed that each spark created physical damage on the dielectric layer. The HBM system applied the discharge for approximately 10 ms and it lasts long enough to bring the membrane in the downstate (the switching times of the device are around 20–30 μs). Unlike the TLP case, the failure mechanism here can probably be assimilated to a ‘tree growth’ defects phenomenon [22], where completed tree-like channels turn out to be local fractures damaging the thin dielectric layer. • For the charging studies, devices with three different silicon nitrides were used: LF-SiN, MF-SiN and HF-SiN. The HBM voltage was swept from 30 to 100 V. In order to avoid any trace left by previous charging phenomenon, each point corresponds to one single discharge on one virgin device. From figure 5, the expression can be written as nHBM VHBM (EHBM ) = V0,HBM · EHBM , (2) where V0,HBM is the amplitude factor that is related to the instantaneous polarization, EHBM is the electric field of the HBM pulse, nHBM is the power-law exponent that is related to the time-dependent polarization (orientation of dipoles and the distribution of free charges, dipolar and space charge polarization). Unlike the TLP generator, the HBM tester applied signals that last longer. They were long enough to actuate 4

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differences. As already mentioned, two dominant charging mechanisms were observed in the contact-less configuration, i.e. the injected charging and the induced charging. In HBM testing, due to the fact that the bridge was actuated during the stress, only charge injection was observed, and consequently, the shift in Vcapamin was ten times larger than the one obtained for TLP testing. From figures 3, 5 and 6, it was deduced that the charging in LF material builds up faster than in the MF material. In fact, both results indicate that LF-SiN was more sensitive to ESDs than MF-SiN and HF-SiN material. The HF-SiN material was less affected by the instantaneous polarization, whereas the time-dependent polarization appeared faster (the slope is steeper). In fact, FTIR assessment has revealed that in MF-SiN the concentration of Si-H bonds is significantly larger than in LF-SiN [24]. We conclude that the behaviour of MF-SiN material may arise from the large concentration of Si–H bonds and possible hydrogen migration. So, it depends on the properties of the different nitrides. Based on published data from the MIM capacitor [25], we can point out that the transient leakage current analysis revealed that LF material is affected by the presence of defects due to high electric-field injection. These defects are related to the presence of N–H bending bonds. The amount of hydrogen is lower in MF-SiN. It was correlated with the dielectric film macroscopic polarization, obtained from TSDC measurements [24], which showed the interaction from dipoles and also from free carriers. HF nitride films have lower leakage current levels but their time constant is higher to release the trapped charges. Another point is that the roughness of dielectric and bridge surfaces gives rise to a non-uniform charge distribution. During an ESD event, competition between the two basic mechanisms, i.e. charge induction and charge injection, will take place and a non-uniform charge distribution similar to the one shown in [26] cannot be ruled out.

Figure 5. The shift of Vcapamin as a function of stress electric field for LF-SiN, MF-SiN and HF-SiN dielectrics.

Figure 6. The shift of Vcapamin as a function of tdown calculated from cycling conditions, for SW3 structures with LF-SiN, MF-SiN and HF-SiN dielectrics.

2.2. KPFM testing

Table 2. Extracted variables from the fittings. V0,TLP

nTLP V0,HBM nHBM V0,c nc

LF-Si3 N4 6 × 10−2 0.19 1.48 MF-Si3 N4 5 × 10−3 0.34 0.39 HF-Si3 N4 8.5 × 10−4 0.48 0.06

1.50 7.39 2.21 4.63 3.61 0.75

Recently, the assessment of dielectric charging and discharging with Kelvin probe microscopy technique has been introduced as a promising method to qualify dielectric surface charge distribution and discharging process [23, 26–28]. It can map electrostatic potential variations on the sample surface. In insulators, data such as fixed charges at the sample surface and within its bulk and including absorption layers may be obtained. Alternatively, this technique has been used here to verify the model of macroscopic polarization given by [29]

0.026 0.060 0.280

the switch, and in this case, the dominant mechanism was clearly charge injection (the signs of the exponents are all positive). In this range of electric field, it can be pointed out that despite the faster charge kinetics of the HF material, the instantaneous polarization is still lower than that of the LF material. Bearing in mind that this amplitude factor is proportional to the amount of trapped charges, these results agreed perfectly with the effect of charging observed, in cycling stress conditions (figure 6) and charging observed at the nanoscale [23].

P = PD + PSC-i − PSC-e

(3)

where P is the total polarization, PD is the dipolar polarization, PSC-i is the intrinsic space charge polarization of intrinsic origin arising from free charge displacement inside the dielectric when an electric field is applied and PSC-e is the space charge polarization of extrinsic origin and comes from the fact that in the downstate, charge injection takes place. A ESD stress was applied to the MEMS device through its signal line and it was optically noted that the bridge was moving clearly. After the stress, the upper membrane was sacrificed and removed, the bottom electrode is grounded

2.1.3. Discussion. A comparison between TLP, HBM ESD stress and cycling methods, using the parameters extracted in table 2, revealed some common features but also important 5

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where C0 is the minimum of capacitance, A is the linear coefficient (sensitive to charging) and B is the quadratic coefficient (related to the curvature of the parabola).

(a)

3.1.2. Analytical modelling. The analytical model of such a methodology can be described as: when charging occurs in an insulating material, the surface potential will have a value that is related to the amount of charges and the shape of their distribution. The C–V can be shifted either to the positive side or to the negative side depending on the dielectric material and the bias polarity. This shift is proportional to the amount of charge collected by the dielectric and hence to the built in surface potential when stresses are applied to the device. The contributions to the total charge Q are made up of fixed charge Q f , mobile charge Qm , trapped charge Q and surface state charge Qs . Within the small voltage span (measurement window) of the partial capacitance measurement, no current flows through the dielectric and any transient current measured in the external circuit will arise from dipolar polarization and space charge polarization of free charges. This way only the impact of ESD stresses will be analysed. Under highelectric-field pulses, we expected two charging mechanisms responsible for the polarizability to take place [30].

(b)

Figure 7. Surface potential distribution of a stressed device: (a) top view of the scanned area and (b) the corresponding measured surface potential.

to the KPFM system. The obtained result is shown in figure 7. It was verified that charge is still detectable after 17 h. From figure 7(b), laterally inhomogeneous charge distribution was observed and it is in line with results shown by Herfst [26] and it showed that space charge polarization of extrinsic origin part of the model (equation (3)) was excited by the stress. Further material characterizations are reported in [23, 28] showing the relation between the charging and the SiN chemical composition, using the KPFM technique. In the near future, it may be possible to bridge on-wafer level testing data to those from material analysis.

• The first one is electronic polarization from fieldinduced charging. The electric field causes translation of symmetrical distribution of the electron clouds of atoms or molecules. • The second one is orientational polarization from charge injection. The electric field causes the reorientation of the dipoles toward the direction of the field. In the first case, we expect a shift of the parameter Vcapamin of the partial C–V towards the opposite polarity compared to the applied pulse, whereas in the second case, the shift should be towards the same polarity as that of the applied pulse.

3. Pulse-induced charge methodology 3.1. Fundamentals

3.2. PIC test bench

3.1.1. Charge-detection principle. In order to monitor the charging before and after the ESD stresses, capacitance characteristics were measured by biasing the device below its pull-in voltage (partial CV). This precaution was necessary in order to avoid dielectric charging generated from the test bench. The shift of the voltage corresponding to the capacitance minimum is closely related to the underlying physical mechanisms, such as the charge kinetics and the amount of trapped charges or residual surface charges. The measurements were made under ambient conditions (i.e. atmospheric pressure, room temperature 25 ◦ C and 30% humidity). To perform these charging tests, the ESD voltage magnitude was limited to 100 V. This value was chosen to be in the safe range (below the electrical breakdown level) in order to avoid permanent damage to the structure. The measured capacitance of the capacitive RF-MEMS switch in the small voltage span as a function of the voltage C(V ) is a parabola. The nonlinear behaviour of the structure as a function of the applied voltage can usually be fitted with the following quadratic expression: C(V ) = C0 (1 + A · V + B · V 2 ),

In this section, a third and different pulse system is introduced and used because signals provided by the conventional pulse generator lead to EOS type of breakdown in this particular electrostatically driven MEMS testing case. Indeed ESD stress failure leads to small degradation that can be easily located and analysed, giving additional information on the failure mechanism, whereas when breakdown occurs during an EOS event, it results in catastrophic failure. There is no way to understand the cause and to locate the failure with such a destructive event. Besides, commercialized ESD test benches do not enable variation of the discharge time (which is needed for charging investigations in MEMS switches). Therefore, to apply ESD-like pulses, the PIC setup shown in figure 8 has been proposed. The programmable high-voltage (HV) source was connected to the in-house PIC circuit board in order to charge a 100 pF capacitor. The PIC circuit board is an circuit that integrates an in-house fabricated HBM system, whose block diagram is the same as shown in figure 1(b). The fact that it was mounted directly on the RF probes reduced the parasitic capacitance of long cables and additional connectors

(4) 6

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Figure 8. Schematic of the PIC setup. Table 3. Types of capacitive RF-MEMS switches. Type

Active area

Dielectrics

Air gap

Deposition method

Thickness

Bottom electrode

Membrane

SW1 SW1 SW2 SW3

200 × 120 200 × 120 138 × 110 96 × 77

AlN SiN LF-SiN/MF-SiN/HF-SiN LF-SiN/MF-SiN/HF-SiN

2.4 μm 2.4 μm 1.9 μm 1.9 μm

Sputtered PECVD PECVD PECVD

300 ηm 300 ηm 250 ∓ 10 ηm 250 ∓ 10 ηm

Ta/Pt/Au/Pt Ta/Pt/Au/Pt Ti/Au/Ti Ti/Au/Ti

Au/Ni/Au Au/Ni/Au Au evaporated/ Au electroplated

that may dissipated the discharged signal. Four relays RL1, RL2, RL3 and RL4 were used to configure the pulse signal and for automation of the CV measurements. The Tektronix AFG320 signal generator was used to control RL2 and RL4 relays (RL2 was on to apply the discharge and RL4 was on for the capacitance measurement). In order to be sure that no residual signal remains in the DUT, RL3 was used to shortcut the DUT. During the discharging, the waveforms were monitored through the Tektronix DPO 4034 oscilloscope. A BOONTON 7200 capacitance meter (1 fF to 2000 pF range) was used to measure the CV characteristics.

4.2. Device description All structures that were tested in this work are listed in table 3. To be easily distinguished, they are identified as SW1, SW2 and SW3. The first device SW1 that was tested is an AlN-based microwave capacitive microswitch (only used for the first TLP experiment due to the number of samples limitation). A design from LAAS was used [31] and was fabricated by Fraunhofer Institute for Silicon Technology (ISIT-FHG) within a multiproject wafer run. From the bottom up, it started with a high resistivity silicon wafer. A 2 μm thick silicon oxide layer was grown on it. The coplanar lines and all other interconnections consist of 3 μm thick electroplated gold Au layer. Then, 300 nm thick sputtered AlN layer was used as a dielectric layer between the signal line and the membrane. The membrane’s thickness is 0.9 μm and the air gap between the movable membrane and the dielectric surface is 2.4 μm in height. Its RF performances and electromechanical parameters were described in [10]. The RF-MEMS technology of SW2 and SW3 was built on a high-resistivity silicon substrate covered by a benzocyclobutene (BCB) layer of 10 μm in thickness. The 1.8 μm thick coplanar waveguide line was made up of Ti/Au multilayer, formed by the liftoff of evaporated gold. The membrane was made up of 2 μm thick electroplated gold. Under the bridge, the signal line was covered by 250±10 nm of high-frequency (HF)-, mixed-frequency (MF)and low-frequency (LF)-PECVD Si3 N4 dielectric layers with a dielectric constant around 6.5. The average roughness of these

4. Results 4.1. Definition Accelerated lifetime test consists of experimental techniques in which a given DUT undergoes a specific stress protocol such as to induce the same failure mechanisms that would appear under regular working conditions, but in a much shorter elapsed time. These techniques are typically based on overstressing the DUT without altering the underlying physics, i.e. introducing new failure mechanisms or masking the sought ones. By this means, the assessment of reliability figures and test are much more robust and quick to accomplish. The availability of acceleration technique is paramount in the case of inline reliability test of MEMS components where the testing time is estimated to impact the overall production costs by more than 50%. 7

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dielectrics are, respectively, 6.2, 5.66 and 2.86 nm. Without the electrostatic force, the mechanical beam’s height over the signal line featured 1.9 μm. The actuation voltage of the switches is around 20–30 V. Their microwave characteristics were reported in [32]. 4.3. Test under the cycling condition Figure 5 showed that one single disruptive pulse caused a voltage shift V , in the same order or event higher than the normal shift induced by cycling (commonly cycling is considered as the conventional testing methodology). Therefore, in this work, the correlation between cycling and HV pulsing accelerated testing triggered further investigation and dedicated attention. Cycling measurements were made to illustrate conventional stress lifetime. The devices were actuated under a positive square signal, with the frequency range from 10 to 100 Hz, a duty factor of 50% and at room temperature of 300 K. It has to be pointed out that cycling measurements are time consuming. The relation between the charging and the time the switch remains in the downstate during cycling was verified to be a power law (figure 6):   tdown,c nc Vc (tc , Nc ) = V0,c · · Ncnc , (5) τc ∗ where V0,c is the cycling amplitude factor that depends on the material, tdown,c is the total downstate time of the cycling calculated from the frequency and the duty cycle, τc is the charging process time constant (also material dependent), Nc is the number of cycles and Nc is the power-law exponent/index.

Figure 9. The shift of Vcapamin as a function of number of pulses at different electric fields for SW3 structures with HF-SiN dielectric.

4.4. Test under the PIC condition Pulse stress measurements were made using the PIC setup (figure 8). The discharge’s duration is around ∼10 ms. This is important to take into account for the RF-MEMS testing, because the mechanical response for this kind of MEMS structure is around 10–20 μs. So, if the electric field is high enough and the pulse lasts larger than the switching time of the switch, the HV pulse can induce displacement of the movable membrane. When the membrane is brought in contact with the dielectric, the high electric field induces a much higher stress than the conventional cycling test. A series of measurements was made for stresses ranging from 40 to 100 V (which is higher than the actuation voltage of the switch ∼20 V and much lower than the breakdown voltage ∼380 V). The outcome showed that the charging has also a powerlaw voltage stress dependence (figure 9). The stress parameters that have been varied in those experiments are the electric field and the number of pulses, which is related to the total time the switch is in the downstate position. Around 40 cumulative stresses were performed at three different electricfield levels and more than 20 virgin devices were used to plot the experimental data of figure 9. With respect to the applied electric field and within the time scale of the charging procedure, the shift of the C(V ) characteristics induced by the pulse stress can be written as    ms tdown,s ns Es ns Vs (ts , Ns , Es ) = V0,s · · Ns · , (6) τs E0

Figure 10. The shift of Vcapamin as a function of the downstate time.

where V0,s is the stress amplitude factor that depends on the material, tdown,s is the total downstate time of the stress, τs is the charging time constant, Ns is the number of pulses, Es is the electric field of the stress, E0 is an equivalent factor and ms and ns are the power-law exponents. 4.5. Correlation: cycling versus PIC For the correlation, only SW3 devices with HF-SiN were used. In order to compare stress and cycling data, the shift of the C(V ) graphs (the parameter V ) was considered as the comparison parameter. The results of cycling and PIC pulse stress tests are summarized in figure 10. The plots of the two experimental ageing methods indicated that the same magnitude of the shift V is achieved in a much shorter time by using the HV pulses. Thus, the PIC setup or any other setup that can provide ESD-like pulse waveform (in contrast with EOS waveform) can be considered as a promising accelerated lifetime test method. In order to make the correlation between the pulse stress method and cycling, it is necessary to examine 8

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the common relation between the calculated resulting shifts Vc and Vs . Taking into account the electric-field intensity during cycling is Ec = 0.8 MV cm−1 , assuming that we apply only one single cycle/pulse under this electric field and that the estimated total duration of the corresponding pulses is for the cycling method 5 ms and for the PIC method ∼10 ms, we obtain Vc = 18 mV and Vs = 26 mV. This extrapolation approach allows us to validate the method since it univocally identifies the same parameter V (within a given and tolerable error) for the two different techniques. The results showed that the models converge to the same V when cycling and pulsing become equivalent. The results presented are consistent with established voltage acceleration mechanisms [16]. Hence, the confidence in using the initial equations (equations (5) and (6)) in order to define the relation between the pulse stress field and the corresponding number of cycles N, the latter performed under the downstate electric field Ec :  α Es N= , Ec where α > 1 (in this case α ∼ 1.5). Finally, those results show that HV impulse ageing stress worked in the case of accelerated testing in capacitive switches and the acceleration factor is shown above. Consequently, it will reduce significantly the testing time with obvious beneficial consequence on the device lifetime estimation.

Figure 11. The Arrhenius model fit of V0,s .

the model (strongly dependent on the thermal properties of the material) and K0 is a constant. Using this model, the activation energy of a specific device can be extracted. In our case, the activation energy was found to be around 0.77 eV in three decay ranges. The Arrhenius model described above shows the relationship between charging rate and temperature for capacitive RF-MEMS switches. In this manner, the charging of a device under normal usage conditions can be estimated from temperature accelerated test data.

4.6. Temperature acceleration Temperature is often used as an acceleration factor to determine the mean time to failure (MTTF) parameter of a structure. Using an Arrhenius relation for this parameter, the operation time of the structure can be accurately calculated. Hence, experiments were completed with investigations on PIC tests carried out under different temperature conditions. The first precaution that has been taken is to know if the failure mechanism remains the same when the temperature varies. This has been validated by observing the independence of the slope (ms of equation (6)) to temperature increase. Since there is no change in the failure mechanism, it allowed us to combine pulse stress with temperature acceleration. Therefore, a series of experiments using more than 70 fresh HF-SiN SW2 devices was performed to cover the temperature range from 300 to 355 K and the data are depicted in figure 11. Indeed, figure 11 shows the V0,s parameter as a function of temperature. In order to extract this V0,s parameter at various temperatures, around seven virgin devices were used to obtain the shift of Vcapamin as a function of the pulse stress electric field, as shown in figure 5 at each temperature. Hence, the V0,s parameter is extracted by using equation (6). The Arrhenius model used for acceleration of temperature-related stress is described by the following expression:   Ea , (7) K = K0 + K1 · exp kB · T where K is the acceleration factor, Ea is the activation energy (eV), kB is Boltzmann’s constant 8.6159 × 10−5 eV K−1 , T is the temperature in Kelvin, K1 is the amplitude coefficient of

5. Conclusion This paper dealt with ESD breakdown and charging analyses. Three different structures with different dielectric materials and two types of ESD tester (TLP and HBM) were used for the experiments. The first results showed the electrical breakdown signature of the tested structures and failure analyses were conducted. It showed that air-gap switches are very sensitive to disruptive discharges that can happen in any non-static free environment. The second part of the results reported the difference in the charging process between LF-SiN, MFSiN and HF-SiN dielectric materials according to ESD. Then, the influence of the process deposition method on the charging behaviour was discussed. The third part introduced a different pulse system. The generated pulse width is long enough to induce displacement of the membrane if the pulse stress magnitude is high enough (higher than the pull-in of the device). Using this method, pulse-induced accelerated stress tests were performed and correlation was made with conventional cycling tests. It showed that HV impulse ageing test must work in the case of accelerated testing in capacitive RF-MEMS switches and the acceleration factor expression was defined. Furthermore, increasing the testing temperature constituted an additional way to multiply this factor. The data showed that testing time can be reduced significantly and thereby reliability statistics may be obtained faster. 9

J. Micromech. Microeng. 22 (2012) 045016

J J Ruan et al

Acknowledgments

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