1/3
RING OSCILLATOR SENSITIVITY TO SPATIAL PROCESS VARIATION Mark Hatzilambrou, Andrew Neureuther, and Costas Spanos Department of Electrical Engineering & Computer Sciences University of California, Berkeley CA 94720 office: (510) 643-6776, home: (510) 635-1882, fax: (510) 642-2739 e-mail:
[email protected]
A test chip has been fabricated with a 6x6 array of ring oscillator (RO) test circuits and linewidth measurement structures to observe and explain spatial performance variation. On-chip counter circuitry allows the measurement and digital readout of frequency to 0.05% accuracy. Strong within wafer position and within die position effects on performance are observed.
1.0
Introduction
Analysis of process variation is undertaken to control or design around that variation in order to produce more manufacturable, and therefore less expensive, products. Thus, it is most important to understand the impact of the components of variation on the performance of the fabricated circuits in order to focus process control and design verification efforts on those high impact components. To date, the efforts to control or account for process variation have concentrated on global temporal and spatial uniformity and consistency. In circuit design, these variations have been accounted for as aggregate, random, mutually correlated parameter distributions. Intra-die variation has been an issue primarily in analog design where matching has been much more important than absolute control. Intra-die variation is increasingly difficult to avoid with large field sizes. Studies have shown a 10% intra-die linewidth variation which has a large deterministic component [1]. This allows the effect to be corrected or accounted for if the benefits exceed the costs. This study demonstrates a method for determining the degree of correlation between intra-die linewidth variations and overall circuit performance.
2.0
Experiment Design
Different circuit design styles are sensitive to different process variations, so it is necessary to decide at the outset the design style of interest. We have chosen to investigate high integration digital logic circuits. For the purpose of this study, it is significant that standard CMOS digital logic circuit performance
can be generalized relatively effectively by ring oscillator (RO) frequency. Although RO frequency is an excellent indicator of overall circuit performance of standard digital CMOS, care must be taken in choosing the stage gate. Variations in interconnect capacitance and resistance, threshold voltage, gate oxide thickness, mobility, and junction depth have all been shown to have significant impact on stage delay, depending on gate configuration. Because our initial purpose was to study the effect of intra-die linewidth variation on RO frequency, the stage gate is designed to make the RO realistically sensitive to linewidth variation. All gates are drawn at minimum length, reflecting actual design practice. The gate is an inverter with a single pull-up and single pull-down device. This non-stacked topology minimizes threshold variation impact. Finally, interconnect is minimized and a fanout of four provides predominantly gate capacitance loading. Alternatively, similar approaches could be taken if the goal were to study interconnect effects and minimize the effects of device parameter variation. Process Test Structures
Scribe Lane with
Abstract
CDTest RO
CDTest RO
CDTest RO
CDTest RO
CDTest RO
CDTest RO
CDTest RO
CDTest RO
CDTest RO
CDTest RO
CDTest RO
CDTest RO
CDTest RO
CDTest RO
CDTest RO
CDTest RO
CDTest RO
CDTest RO
CDTest RO
CDTest RO
CDTest RO
CDTest RO
CDTest RO
CDTest RO
CDTest RO
CDTest RO
CDTest RO
CDTest RO
CDTest RO
CDTest RO
CDTest RO
CDTest RO
CDTest RO
CDTest RO
CDTest RO
CDTest RO
Figure 1 Test chip layout The test chip has been fabricated in the UC Berkeley microfabrication facility using the baseline
2/3
An on-chip counter and multiplexor scheme is designed to allow testing of the chip by available standard autoprobe and DC parametric measurement equipment. As depicted in Figure 2, a set of four RO’s are multiplexed into a single count/shift register. An externally supplied timed pulse allows the pulse count to be stored on-chip and shifted out digitally. This provides better than 0.05% accuracy of frequency measurement.
RO1
...
...
Within Die Position Avg(Freq)
H )
Freq(MHz) 18.5 19
Accompanying the RO’s are linewidth test structures. These structures consist of a Van der Pauw sheet resistance measurement structure along with a 4-point resistor measurement structure to allow for the determination of the drawn gate length in the proximate ring oscillator.
one can see the periodic pattern corresponding to individual dice.
6 4 Y
2 1
3
2
5
4
6
X
Figure 3 Within die position effect on frequency of RO oscillation .
Wafer Position Avg(Freq)
Freq(MHz) 18 19 20
CMOS 2-micron process. The chip floorplan is shown in Figure 1. Ring oscillators are distributed uniformly across the stepper field in a 6x6 array. All poly gates are drawn with a vertical orientation and are separated from other gates to prevent linewidth variations due to lens astigmatism or feature proximity effects.
8 6
RO2 MUX
Count/ Shift Registers
RO3
Y4
Count Out
2 1
Freq. Out
2
3
4
6
5
7
8
X
Figure 4 Within wafer position effect on frequency of RO oscillation
RO4
3.0
Analysis and Results
Measurements of RO frequency and gate linewidth have been analyzed to determine the effects due to their position within the wafer and their position within the die. The within wafer position effect for RO frequency is shown in Figure 3 as the average of all available RO’s, excluding outliers, at a given location on the 6x6 intra-die array. (Eight RO’s failed to operate on any die and therefore are not represented in this figure). Similarly, the wafer map of die averages of within wafer position is shown in Figure 4. Figure 5 shows the raw wafer map of frequencies, in which
Freq(MHz) 16 17 18 19 20 21
Figure 2 Ring oscillator design and frequency measurement strategy
40
30
2 Y 0
10
10
20
30
40
X
Figure 5 Wafer map of ring oscillator frequencies Considering within die position and within wafer position as separate treatments, analysis of variance has been conducted on an additive model for both RO frequency variation and drawn gate CD variation. The results are shown in Table 1 and Table 2, respectively.
3/3
D.F.
Sum of Squares
F Value
Pr(F)
Wafer Effect
47
5.91E13
74.27
0.00
Die Effect
27
2.84E13
62.17
0.00
Residuals
999
1.67E13
20.0
• • •
19.0
Frequency(MHz)
Table 1: ANOVA of Frequency Effects
quency vs. 1/CD. The resulting correlation coefficient is 0.342.
• •
•• •
18.0
Results of the F-test for frequency effects show that both the within wafer position effect and the within die position effect are highly significant. Moreover, the additive model has an R2=0.84, with within wafer position accounting for 57% of the overall variance and within die position accounting for an additional 27%.
The F-test for the drawn gate CD shows that both the die and wafer effects are significant as well. However, the additive model has an overall R 2 =0.29. While the within wafer position accounts for a sizeable 25% of the overall variance, the within die position effect accounts for only 4%. In the face of the 71% residual, the within die effect for the drawn gate CD is insignificant. Analysis of the CD measurement data indicates that the high noise level in the CD data is likely due to difficulty in accurately measuring the sheet resistance from the Van der Pauw structure.
Table 2: ANOVA of CD Effects D.F.
Sum of Squares
F Value
Pr(F)
Wafer Effect
51
4.6127
12.00
0.00
Die Effect
35
0.6649
2.52
2.3E-6
Residuals
1743
13.139
R2=0.29
Because of the relatively high noise level in the spatial CD model, we have attempted to correlate RO frequency with CD by taking within wafer position averages (averages of all points within the die). This averaging choice emphasizes the within wafer effect, which is much more significant than the within die effect. Figure 6 shows the scatter plot and leastsquares fit of within wafer position averages of fre-
• •
•
•
• •• • •• • • • • • • •• • ••• •• •
•
• •• •
•
•
•
• •
•• •
• 0.54
R2=0.84
•
0.55
0.56
0.57
0.58
0.59
1/CD(microns)
Figure 6 Frequency vs. 1/CD for within wafer position averages
4.0
Conclusions
The analysis of the RO frequency dependence on die and wafer position indicates a very strong effect from both causes. This can be the result only of one or more underlying process parameter variations with a similar spatial dependence. The attempt to correlate this spatial variation with the previously observed drawn gate CD variation shows only weak correlation when the more significant within wafer position effect is included. This is due to the fact that the data for CD cannot be well explained by a spatial model. There exists the possibility that the residual observed in the measurement data is due to fabrication noise; it is perhaps more likely that it is due to measurement noise and that the trend observed in the weak correlation has deeper roots. In order to expand upon the conclusions of this experiment, the test chip is being fabricated after a redesign to include a more robust CD measurement structure along with other location specific structures for device parameter extraction. We hope to correlate the observed frequency variation to either CD or other process parameters with spatial dependence.
Acknowledgments This research has been supported by the California State MICRO program under grant #95-113.
References [1] Crid Yu, Tinaung Maung, Costas Spanos, Duane Boning, James Cheung, Hua-Yu Liu, Keh-Jeng Chang, and Dirk Bartelink, “Use of Short-Loop Electrical Measurements for Yield Improvement”, IEEE Trans. Semicond. Manuf., vol. 8, no. 2. May 1995, pp. 150-159.
1/3
RING OSCILLATOR SENSITIVITY TO SPATIAL PROCESS VARIATION Mark Hatzilambrou, Andrew Neureuther, and Costas Spanos Department of Electrical Engineering & Computer Sciences University of California, Berkeley CA 94720 office: (510) 643-6776, home: (510) 635-1882, fax: (510) 642-2739 e-mail:
[email protected]
A test chip has been fabricated with a 6x6 array of ring oscillator (RO) test circuits and linewidth measurement structures to observe and explain spatial performance variation. On-chip counter circuitry allows the measurement and digital readout of frequency to 0.05% accuracy. Strong within wafer position and within die position effects on performance are observed.
1.0
Introduction
Analysis of process variation is undertaken to control or design around that variation in order to produce more manufacturable, and therefore less expensive, products. Thus, it is most important to understand the impact of the components of variation on the performance of the fabricated circuits in order to focus process control and design verification efforts on those high impact components. To date, the efforts to control or account for process variation have concentrated on global temporal and spatial uniformity and consistency. In circuit design, these variations have been accounted for as aggregate, random, mutually correlated parameter distributions. Intra-die variation has been an issue primarily in analog design where matching has been much more important than absolute control. Intra-die variation is increasingly difficult to avoid with large field sizes. Studies have shown a 10% intra-die linewidth variation which has a large deterministic component [1]. This allows the effect to be corrected or accounted for if the benefits exceed the costs. This study demonstrates a method for determining the degree of correlation between intra-die linewidth variations and overall circuit performance.
2.0
Experiment Design
Different circuit design styles are sensitive to different process variations, so it is necessary to decide at the outset the design style of interest. We have chosen to investigate high integration digital logic circuits. For the purpose of this study, it is significant that standard CMOS digital logic circuit performance
can be generalized relatively effectively by ring oscillator (RO) frequency. Although RO frequency is an excellent indicator of overall circuit performance of standard digital CMOS, care must be taken in choosing the stage gate. Variations in interconnect capacitance and resistance, threshold voltage, gate oxide thickness, mobility, and junction depth have all been shown to have significant impact on stage delay, depending on gate configuration. Because our initial purpose was to study the effect of intra-die linewidth variation on RO frequency, the stage gate is designed to make the RO realistically sensitive to linewidth variation. All gates are drawn at minimum length, reflecting actual design practice. The gate is an inverter with a single pull-up and single pull-down device. This non-stacked topology minimizes threshold variation impact. Finally, interconnect is minimized and a fanout of four provides predominantly gate capacitance loading. Alternatively, similar approaches could be taken if the goal were to study interconnect effects and minimize the effects of device parameter variation. Process Test Structures
Scribe Lane with
Abstract
CDTest RO
CDTest RO
CDTest RO
CDTest RO
CDTest RO
CDTest RO
CDTest RO
CDTest RO
CDTest RO
CDTest RO
CDTest RO
CDTest RO
CDTest RO
CDTest RO
CDTest RO
CDTest RO
CDTest RO
CDTest RO
CDTest RO
CDTest RO
CDTest RO
CDTest RO
CDTest RO
CDTest RO
CDTest RO
CDTest RO
CDTest RO
CDTest RO
CDTest RO
CDTest RO
CDTest RO
CDTest RO
CDTest RO
CDTest RO
CDTest RO
CDTest RO
Figure 1 Test chip layout The test chip has been fabricated in the UC Berkeley microfabrication facility using the baseline
2/3
An on-chip counter and multiplexor scheme is designed to allow testing of the chip by available standard autoprobe and DC parametric measurement equipment. As depicted in Figure 2, a set of four RO’s are multiplexed into a single count/shift register. An externally supplied timed pulse allows the pulse count to be stored on-chip and shifted out digitally. This provides better than 0.05% accuracy of frequency measurement.
RO1
...
...
Within Die Position Avg(Freq)
H )
Freq(MHz) 18.5 19
Accompanying the RO’s are linewidth test structures. These structures consist of a Van der Pauw sheet resistance measurement structure along with a 4-point resistor measurement structure to allow for the determination of the drawn gate length in the proximate ring oscillator.
one can see the periodic pattern corresponding to individual dice.
6 4 Y
2 1
3
2
5
4
6
X
Figure 3 Within die position effect on frequency of RO oscillation .
Wafer Position Avg(Freq)
Freq(MHz) 18 19 20
CMOS 2-micron process. The chip floorplan is shown in Figure 1. Ring oscillators are distributed uniformly across the stepper field in a 6x6 array. All poly gates are drawn with a vertical orientation and are separated from other gates to prevent linewidth variations due to lens astigmatism or feature proximity effects.
8 6
RO2 MUX
Count/ Shift Registers
RO3
Y4
Count Out
2 1
Freq. Out
2
3
4
6
5
7
8
X
Figure 4 Within wafer position effect on frequency of RO oscillation
RO4
3.0
Analysis and Results
Measurements of RO frequency and gate linewidth have been analyzed to determine the effects due to their position within the wafer and their position within the die. The within wafer position effect for RO frequency is shown in Figure 3 as the average of all available RO’s, excluding outliers, at a given location on the 6x6 intra-die array. (Eight RO’s failed to operate on any die and therefore are not represented in this figure). Similarly, the wafer map of die averages of within wafer position is shown in Figure 4. Figure 5 shows the raw wafer map of frequencies, in which
Freq(MHz) 16 17 18 19 20 21
Figure 2 Ring oscillator design and frequency measurement strategy
40
30
2 Y 0
10
10
20
30
40
X
Figure 5 Wafer map of ring oscillator frequencies Considering within die position and within wafer position as separate treatments, analysis of variance has been conducted on an additive model for both RO frequency variation and drawn gate CD variation. The results are shown in Table 1 and Table 2, respectively.
3/3
D.F.
Sum of Squares
F Value
Pr(F)
Wafer Effect
47
5.91E13
74.27
0.00
Die Effect
27
2.84E13
62.17
0.00
Residuals
999
1.67E13
20.0
• • •
19.0
Frequency(MHz)
Table 1: ANOVA of Frequency Effects
quency vs. 1/CD. The resulting correlation coefficient is 0.342.
• •
•• •
18.0
Results of the F-test for frequency effects show that both the within wafer position effect and the within die position effect are highly significant. Moreover, the additive model has an R2=0.84, with within wafer position accounting for 57% of the overall variance and within die position accounting for an additional 27%.
The F-test for the drawn gate CD shows that both the die and wafer effects are significant as well. However, the additive model has an overall R 2 =0.29. While the within wafer position accounts for a sizeable 25% of the overall variance, the within die position effect accounts for only 4%. In the face of the 71% residual, the within die effect for the drawn gate CD is insignificant. Analysis of the CD measurement data indicates that the high noise level in the CD data is likely due to difficulty in accurately measuring the sheet resistance from the Van der Pauw structure.
Table 2: ANOVA of CD Effects D.F.
Sum of Squares
F Value
Pr(F)
Wafer Effect
51
4.6127
12.00
0.00
Die Effect
35
0.6649
2.52
2.3E-6
Residuals
1743
13.139
R2=0.29
Because of the relatively high noise level in the spatial CD model, we have attempted to correlate RO frequency with CD by taking within wafer position averages (averages of all points within the die). This averaging choice emphasizes the within wafer effect, which is much more significant than the within die effect. Figure 6 shows the scatter plot and leastsquares fit of within wafer position averages of fre-
• •
•
•
• •• • •• • • • • • • •• • ••• •• •
•
• •• •
•
•
•
• •
•• •
• 0.54
R2=0.84
•
0.55
0.56
0.57
0.58
0.59
1/CD(microns)
Figure 6 Frequency vs. 1/CD for within wafer position averages
4.0
Conclusions
The analysis of the RO frequency dependence on die and wafer position indicates a very strong effect from both causes. This can be the result only of one or more underlying process parameter variations with a similar spatial dependence. The attempt to correlate this spatial variation with the previously observed drawn gate CD variation shows only weak correlation when the more significant within wafer position effect is included. This is due to the fact that the data for CD cannot be well explained by a spatial model. There exists the possibility that the residual observed in the measurement data is due to fabrication noise; it is perhaps more likely that it is due to measurement noise and that the trend observed in the weak correlation has deeper roots. In order to expand upon the conclusions of this experiment, the test chip is being fabricated after a redesign to include a more robust CD measurement structure along with other location specific structures for device parameter extraction. We hope to correlate the observed frequency variation to either CD or other process parameters with spatial dependence.
Acknowledgments This research has been supported by the California State MICRO program under grant #95-113.
References [1] Crid Yu, Tinaung Maung, Costas Spanos, Duane Boning, James Cheung, Hua-Yu Liu, Keh-Jeng Chang, and Dirk Bartelink, “Use of Short-Loop Electrical Measurements for Yield Improvement”, IEEE Trans. Semicond. Manuf., vol. 8, no. 2. May 1995, pp. 150-159.
1/3
RING OSCILLATOR SENSITIVITY TO SPATIAL PROCESS VARIATION Mark Hatzilambrou, Andrew Neureuther, and Costas Spanos Department of Electrical Engineering & Computer Sciences University of California, Berkeley CA 94720 office: (510) 643-6776, home: (510) 635-1882, fax: (510) 642-2739 e-mail:
[email protected]
A test chip has been fabricated with a 6x6 array of ring oscillator (RO) test circuits and linewidth measurement structures to observe and explain spatial performance variation. On-chip counter circuitry allows the measurement and digital readout of frequency to 0.05% accuracy. Strong within wafer position and within die position effects on performance are observed.
1.0
Introduction
Analysis of process variation is undertaken to control or design around that variation in order to produce more manufacturable, and therefore less expensive, products. Thus, it is most important to understand the impact of the components of variation on the performance of the fabricated circuits in order to focus process control and design verification efforts on those high impact components. To date, the efforts to control or account for process variation have concentrated on global temporal and spatial uniformity and consistency. In circuit design, these variations have been accounted for as aggregate, random, mutually correlated parameter distributions. Intra-die variation has been an issue primarily in analog design where matching has been much more important than absolute control. Intra-die variation is increasingly difficult to avoid with large field sizes. Studies have shown a 10% intra-die linewidth variation which has a large deterministic component [1]. This allows the effect to be corrected or accounted for if the benefits exceed the costs. This study demonstrates a method for determining the degree of correlation between intra-die linewidth variations and overall circuit performance.
2.0
Experiment Design
Different circuit design styles are sensitive to different process variations, so it is necessary to decide at the outset the design style of interest. We have chosen to investigate high integration digital logic circuits. For the purpose of this study, it is significant that standard CMOS digital logic circuit performance
can be generalized relatively effectively by ring oscillator (RO) frequency. Although RO frequency is an excellent indicator of overall circuit performance of standard digital CMOS, care must be taken in choosing the stage gate. Variations in interconnect capacitance and resistance, threshold voltage, gate oxide thickness, mobility, and junction depth have all been shown to have significant impact on stage delay, depending on gate configuration. Because our initial purpose was to study the effect of intra-die linewidth variation on RO frequency, the stage gate is designed to make the RO realistically sensitive to linewidth variation. All gates are drawn at minimum length, reflecting actual design practice. The gate is an inverter with a single pull-up and single pull-down device. This non-stacked topology minimizes threshold variation impact. Finally, interconnect is minimized and a fanout of four provides predominantly gate capacitance loading. Alternatively, similar approaches could be taken if the goal were to study interconnect effects and minimize the effects of device parameter variation. Process Test Structures
Scribe Lane with
Abstract
CDTest RO
CDTest RO
CDTest RO
CDTest RO
CDTest RO
CDTest RO
CDTest RO
CDTest RO
CDTest RO
CDTest RO
CDTest RO
CDTest RO
CDTest RO
CDTest RO
CDTest RO
CDTest RO
CDTest RO
CDTest RO
CDTest RO
CDTest RO
CDTest RO
CDTest RO
CDTest RO
CDTest RO
CDTest RO
CDTest RO
CDTest RO
CDTest RO
CDTest RO
CDTest RO
CDTest RO
CDTest RO
CDTest RO
CDTest RO
CDTest RO
CDTest RO
Figure 1 Test chip layout The test chip has been fabricated in the UC Berkeley microfabrication facility using the baseline
2/3
An on-chip counter and multiplexor scheme is designed to allow testing of the chip by available standard autoprobe and DC parametric measurement equipment. As depicted in Figure 2, a set of four RO’s are multiplexed into a single count/shift register. An externally supplied timed pulse allows the pulse count to be stored on-chip and shifted out digitally. This provides better than 0.05% accuracy of frequency measurement.
RO1
...
...
Within Die Position Avg(Freq)
H )
Freq(MHz) 18.5 19
Accompanying the RO’s are linewidth test structures. These structures consist of a Van der Pauw sheet resistance measurement structure along with a 4-point resistor measurement structure to allow for the determination of the drawn gate length in the proximate ring oscillator.
one can see the periodic pattern corresponding to individual dice.
6 4 Y
2 1
3
2
5
4
6
X
Figure 3 Within die position effect on frequency of RO oscillation .
Wafer Position Avg(Freq)
Freq(MHz) 18 19 20
CMOS 2-micron process. The chip floorplan is shown in Figure 1. Ring oscillators are distributed uniformly across the stepper field in a 6x6 array. All poly gates are drawn with a vertical orientation and are separated from other gates to prevent linewidth variations due to lens astigmatism or feature proximity effects.
8 6
RO2 MUX
Count/ Shift Registers
RO3
Y4
Count Out
2 1
Freq. Out
2
3
4
6
5
7
8
X
Figure 4 Within wafer position effect on frequency of RO oscillation
RO4
3.0
Analysis and Results
Measurements of RO frequency and gate linewidth have been analyzed to determine the effects due to their position within the wafer and their position within the die. The within wafer position effect for RO frequency is shown in Figure 3 as the average of all available RO’s, excluding outliers, at a given location on the 6x6 intra-die array. (Eight RO’s failed to operate on any die and therefore are not represented in this figure). Similarly, the wafer map of die averages of within wafer position is shown in Figure 4. Figure 5 shows the raw wafer map of frequencies, in which
Freq(MHz) 16 17 18 19 20 21
Figure 2 Ring oscillator design and frequency measurement strategy
40
30
2 Y 0
10
10
20
30
40
X
Figure 5 Wafer map of ring oscillator frequencies Considering within die position and within wafer position as separate treatments, analysis of variance has been conducted on an additive model for both RO frequency variation and drawn gate CD variation. The results are shown in Table 1 and Table 2, respectively.
3/3
D.F.
Sum of Squares
F Value
Pr(F)
Wafer Effect
47
5.91E13
74.27
0.00
Die Effect
27
2.84E13
62.17
0.00
Residuals
999
1.67E13
20.0
• • •
19.0
Frequency(MHz)
Table 1: ANOVA of Frequency Effects
quency vs. 1/CD. The resulting correlation coefficient is 0.342.
• •
•• •
18.0
Results of the F-test for frequency effects show that both the within wafer position effect and the within die position effect are highly significant. Moreover, the additive model has an R2=0.84, with within wafer position accounting for 57% of the overall variance and within die position accounting for an additional 27%.
The F-test for the drawn gate CD shows that both the die and wafer effects are significant as well. However, the additive model has an overall R 2 =0.29. While the within wafer position accounts for a sizeable 25% of the overall variance, the within die position effect accounts for only 4%. In the face of the 71% residual, the within die effect for the drawn gate CD is insignificant. Analysis of the CD measurement data indicates that the high noise level in the CD data is likely due to difficulty in accurately measuring the sheet resistance from the Van der Pauw structure.
Table 2: ANOVA of CD Effects D.F.
Sum of Squares
F Value
Pr(F)
Wafer Effect
51
4.6127
12.00
0.00
Die Effect
35
0.6649
2.52
2.3E-6
Residuals
1743
13.139
R2=0.29
Because of the relatively high noise level in the spatial CD model, we have attempted to correlate RO frequency with CD by taking within wafer position averages (averages of all points within the die). This averaging choice emphasizes the within wafer effect, which is much more significant than the within die effect. Figure 6 shows the scatter plot and leastsquares fit of within wafer position averages of fre-
• •
•
•
• •• • •• • • • • • • •• • ••• •• •
•
• •• •
•
•
•
• •
•• •
• 0.54
R2=0.84
•
0.55
0.56
0.57
0.58
0.59
1/CD(microns)
Figure 6 Frequency vs. 1/CD for within wafer position averages
4.0
Conclusions
The analysis of the RO frequency dependence on die and wafer position indicates a very strong effect from both causes. This can be the result only of one or more underlying process parameter variations with a similar spatial dependence. The attempt to correlate this spatial variation with the previously observed drawn gate CD variation shows only weak correlation when the more significant within wafer position effect is included. This is due to the fact that the data for CD cannot be well explained by a spatial model. There exists the possibility that the residual observed in the measurement data is due to fabrication noise; it is perhaps more likely that it is due to measurement noise and that the trend observed in the weak correlation has deeper roots. In order to expand upon the conclusions of this experiment, the test chip is being fabricated after a redesign to include a more robust CD measurement structure along with other location specific structures for device parameter extraction. We hope to correlate the observed frequency variation to either CD or other process parameters with spatial dependence.
Acknowledgments This research has been supported by the California State MICRO program under grant #95-113.
References [1] Crid Yu, Tinaung Maung, Costas Spanos, Duane Boning, James Cheung, Hua-Yu Liu, Keh-Jeng Chang, and Dirk Bartelink, “Use of Short-Loop Electrical Measurements for Yield Improvement”, IEEE Trans. Semicond. Manuf., vol. 8, no. 2. May 1995, pp. 150-159.
1/3
RING OSCILLATOR SENSITIVITY TO SPATIAL PROCESS VARIATION Mark Hatzilambrou, Andrew Neureuther, and Costas Spanos Department of Electrical Engineering & Computer Sciences University of California, Berkeley CA 94720 office: (510) 643-6776, home: (510) 635-1882, fax: (510) 642-2739 e-mail:
[email protected]
A test chip has been fabricated with a 6x6 array of ring oscillator (RO) test circuits and linewidth measurement structures to observe and explain spatial performance variation. On-chip counter circuitry allows the measurement and digital readout of frequency to 0.05% accuracy. Strong within wafer position and within die position effects on performance are observed.
1.0
Introduction
Analysis of process variation is undertaken to control or design around that variation in order to produce more manufacturable, and therefore less expensive, products. Thus, it is most important to understand the impact of the components of variation on the performance of the fabricated circuits in order to focus process control and design verification efforts on those high impact components. To date, the efforts to control or account for process variation have concentrated on global temporal and spatial uniformity and consistency. In circuit design, these variations have been accounted for as aggregate, random, mutually correlated parameter distributions. Intra-die variation has been an issue primarily in analog design where matching has been much more important than absolute control. Intra-die variation is increasingly difficult to avoid with large field sizes. Studies have shown a 10% intra-die linewidth variation which has a large deterministic component [1]. This allows the effect to be corrected or accounted for if the benefits exceed the costs. This study demonstrates a method for determining the degree of correlation between intra-die linewidth variations and overall circuit performance.
2.0
Experiment Design
Different circuit design styles are sensitive to different process variations, so it is necessary to decide at the outset the design style of interest. We have chosen to investigate high integration digital logic circuits. For the purpose of this study, it is significant that standard CMOS digital logic circuit performance
can be generalized relatively effectively by ring oscillator (RO) frequency. Although RO frequency is an excellent indicator of overall circuit performance of standard digital CMOS, care must be taken in choosing the stage gate. Variations in interconnect capacitance and resistance, threshold voltage, gate oxide thickness, mobility, and junction depth have all been shown to have significant impact on stage delay, depending on gate configuration. Because our initial purpose was to study the effect of intra-die linewidth variation on RO frequency, the stage gate is designed to make the RO realistically sensitive to linewidth variation. All gates are drawn at minimum length, reflecting actual design practice. The gate is an inverter with a single pull-up and single pull-down device. This non-stacked topology minimizes threshold variation impact. Finally, interconnect is minimized and a fanout of four provides predominantly gate capacitance loading. Alternatively, similar approaches could be taken if the goal were to study interconnect effects and minimize the effects of device parameter variation. Process Test Structures
Scribe Lane with
Abstract
CDTest RO
CDTest RO
CDTest RO
CDTest RO
CDTest RO
CDTest RO
CDTest RO
CDTest RO
CDTest RO
CDTest RO
CDTest RO
CDTest RO
CDTest RO
CDTest RO
CDTest RO
CDTest RO
CDTest RO
CDTest RO
CDTest RO
CDTest RO
CDTest RO
CDTest RO
CDTest RO
CDTest RO
CDTest RO
CDTest RO
CDTest RO
CDTest RO
CDTest RO
CDTest RO
CDTest RO
CDTest RO
CDTest RO
CDTest RO
CDTest RO
CDTest RO
Figure 1 Test chip layout The test chip has been fabricated in the UC Berkeley microfabrication facility using the baseline
2/3
An on-chip counter and multiplexor scheme is designed to allow testing of the chip by available standard autoprobe and DC parametric measurement equipment. As depicted in Figure 2, a set of four RO’s are multiplexed into a single count/shift register. An externally supplied timed pulse allows the pulse count to be stored on-chip and shifted out digitally. This provides better than 0.05% accuracy of frequency measurement.
RO1
...
...
Within Die Position Avg(Freq)
H )
Freq(MHz) 18.5 19
Accompanying the RO’s are linewidth test structures. These structures consist of a Van der Pauw sheet resistance measurement structure along with a 4-point resistor measurement structure to allow for the determination of the drawn gate length in the proximate ring oscillator.
one can see the periodic pattern corresponding to individual dice.
6 4 Y
2 1
3
2
5
4
6
X
Figure 3 Within die position effect on frequency of RO oscillation .
Wafer Position Avg(Freq)
Freq(MHz) 18 19 20
CMOS 2-micron process. The chip floorplan is shown in Figure 1. Ring oscillators are distributed uniformly across the stepper field in a 6x6 array. All poly gates are drawn with a vertical orientation and are separated from other gates to prevent linewidth variations due to lens astigmatism or feature proximity effects.
8 6
RO2 MUX
Count/ Shift Registers
RO3
Y4
Count Out
2 1
Freq. Out
2
3
4
6
5
7
8
X
Figure 4 Within wafer position effect on frequency of RO oscillation
RO4
3.0
Analysis and Results
Measurements of RO frequency and gate linewidth have been analyzed to determine the effects due to their position within the wafer and their position within the die. The within wafer position effect for RO frequency is shown in Figure 3 as the average of all available RO’s, excluding outliers, at a given location on the 6x6 intra-die array. (Eight RO’s failed to operate on any die and therefore are not represented in this figure). Similarly, the wafer map of die averages of within wafer position is shown in Figure 4. Figure 5 shows the raw wafer map of frequencies, in which
Freq(MHz) 16 17 18 19 20 21
Figure 2 Ring oscillator design and frequency measurement strategy
40
30
2 Y 0
10
10
20
30
40
X
Figure 5 Wafer map of ring oscillator frequencies Considering within die position and within wafer position as separate treatments, analysis of variance has been conducted on an additive model for both RO frequency variation and drawn gate CD variation. The results are shown in Table 1 and Table 2, respectively.
3/3
D.F.
Sum of Squares
F Value
Pr(F)
Wafer Effect
47
5.91E13
74.27
0.00
Die Effect
27
2.84E13
62.17
0.00
Residuals
999
1.67E13
20.0
• • •
19.0
Frequency(MHz)
Table 1: ANOVA of Frequency Effects
quency vs. 1/CD. The resulting correlation coefficient is 0.342.
• •
•• •
18.0
Results of the F-test for frequency effects show that both the within wafer position effect and the within die position effect are highly significant. Moreover, the additive model has an R2=0.84, with within wafer position accounting for 57% of the overall variance and within die position accounting for an additional 27%.
The F-test for the drawn gate CD shows that both the die and wafer effects are significant as well. However, the additive model has an overall R 2 =0.29. While the within wafer position accounts for a sizeable 25% of the overall variance, the within die position effect accounts for only 4%. In the face of the 71% residual, the within die effect for the drawn gate CD is insignificant. Analysis of the CD measurement data indicates that the high noise level in the CD data is likely due to difficulty in accurately measuring the sheet resistance from the Van der Pauw structure.
Table 2: ANOVA of CD Effects D.F.
Sum of Squares
F Value
Pr(F)
Wafer Effect
51
4.6127
12.00
0.00
Die Effect
35
0.6649
2.52
2.3E-6
Residuals
1743
13.139
R2=0.29
Because of the relatively high noise level in the spatial CD model, we have attempted to correlate RO frequency with CD by taking within wafer position averages (averages of all points within the die). This averaging choice emphasizes the within wafer effect, which is much more significant than the within die effect. Figure 6 shows the scatter plot and leastsquares fit of within wafer position averages of fre-
• •
•
•
• •• • •• • • • • • • •• • ••• •• •
•
• •• •
•
•
•
• •
•• •
• 0.54
R2=0.84
•
0.55
0.56
0.57
0.58
0.59
1/CD(microns)
Figure 6 Frequency vs. 1/CD for within wafer position averages
4.0
Conclusions
The analysis of the RO frequency dependence on die and wafer position indicates a very strong effect from both causes. This can be the result only of one or more underlying process parameter variations with a similar spatial dependence. The attempt to correlate this spatial variation with the previously observed drawn gate CD variation shows only weak correlation when the more significant within wafer position effect is included. This is due to the fact that the data for CD cannot be well explained by a spatial model. There exists the possibility that the residual observed in the measurement data is due to fabrication noise; it is perhaps more likely that it is due to measurement noise and that the trend observed in the weak correlation has deeper roots. In order to expand upon the conclusions of this experiment, the test chip is being fabricated after a redesign to include a more robust CD measurement structure along with other location specific structures for device parameter extraction. We hope to correlate the observed frequency variation to either CD or other process parameters with spatial dependence.
Acknowledgments This research has been supported by the California State MICRO program under grant #95-113.
References [1] Crid Yu, Tinaung Maung, Costas Spanos, Duane Boning, James Cheung, Hua-Yu Liu, Keh-Jeng Chang, and Dirk Bartelink, “Use of Short-Loop Electrical Measurements for Yield Improvement”, IEEE Trans. Semicond. Manuf., vol. 8, no. 2. May 1995, pp. 150-159.
1/3
RING OSCILLATOR SENSITIVITY TO SPATIAL PROCESS VARIATION Mark Hatzilambrou, Andrew Neureuther, and Costas Spanos Department of Electrical Engineering & Computer Sciences University of California, Berkeley CA 94720 office: (510) 643-6776, home: (510) 635-1882, fax: (510) 642-2739 e-mail:
[email protected]
A test chip has been fabricated with a 6x6 array of ring oscillator (RO) test circuits and linewidth measurement structures to observe and explain spatial performance variation. On-chip counter circuitry allows the measurement and digital readout of frequency to 0.05% accuracy. Strong within wafer position and within die position effects on performance are observed.
1.0
Introduction
Analysis of process variation is undertaken to control or design around that variation in order to produce more manufacturable, and therefore less expensive, products. Thus, it is most important to understand the impact of the components of variation on the performance of the fabricated circuits in order to focus process control and design verification efforts on those high impact components. To date, the efforts to control or account for process variation have concentrated on global temporal and spatial uniformity and consistency. In circuit design, these variations have been accounted for as aggregate, random, mutually correlated parameter distributions. Intra-die variation has been an issue primarily in analog design where matching has been much more important than absolute control. Intra-die variation is increasingly difficult to avoid with large field sizes. Studies have shown a 10% intra-die linewidth variation which has a large deterministic component [1]. This allows the effect to be corrected or accounted for if the benefits exceed the costs. This study demonstrates a method for determining the degree of correlation between intra-die linewidth variations and overall circuit performance.
2.0
Experiment Design
Different circuit design styles are sensitive to different process variations, so it is necessary to decide at the outset the design style of interest. We have chosen to investigate high integration digital logic circuits. For the purpose of this study, it is significant that standard CMOS digital logic circuit performance
can be generalized relatively effectively by ring oscillator (RO) frequency. Although RO frequency is an excellent indicator of overall circuit performance of standard digital CMOS, care must be taken in choosing the stage gate. Variations in interconnect capacitance and resistance, threshold voltage, gate oxide thickness, mobility, and junction depth have all been shown to have significant impact on stage delay, depending on gate configuration. Because our initial purpose was to study the effect of intra-die linewidth variation on RO frequency, the stage gate is designed to make the RO realistically sensitive to linewidth variation. All gates are drawn at minimum length, reflecting actual design practice. The gate is an inverter with a single pull-up and single pull-down device. This non-stacked topology minimizes threshold variation impact. Finally, interconnect is minimized and a fanout of four provides predominantly gate capacitance loading. Alternatively, similar approaches could be taken if the goal were to study interconnect effects and minimize the effects of device parameter variation. Process Test Structures
Scribe Lane with
Abstract
CDTest RO
CDTest RO
CDTest RO
CDTest RO
CDTest RO
CDTest RO
CDTest RO
CDTest RO
CDTest RO
CDTest RO
CDTest RO
CDTest RO
CDTest RO
CDTest RO
CDTest RO
CDTest RO
CDTest RO
CDTest RO
CDTest RO
CDTest RO
CDTest RO
CDTest RO
CDTest RO
CDTest RO
CDTest RO
CDTest RO
CDTest RO
CDTest RO
CDTest RO
CDTest RO
CDTest RO
CDTest RO
CDTest RO
CDTest RO
CDTest RO
CDTest RO
Figure 1 Test chip layout The test chip has been fabricated in the UC Berkeley microfabrication facility using the baseline
2/3
An on-chip counter and multiplexor scheme is designed to allow testing of the chip by available standard autoprobe and DC parametric measurement equipment. As depicted in Figure 2, a set of four RO’s are multiplexed into a single count/shift register. An externally supplied timed pulse allows the pulse count to be stored on-chip and shifted out digitally. This provides better than 0.05% accuracy of frequency measurement.
RO1
...
...
Within Die Position Avg(Freq)
H )
Freq(MHz) 18.5 19
Accompanying the RO’s are linewidth test structures. These structures consist of a Van der Pauw sheet resistance measurement structure along with a 4-point resistor measurement structure to allow for the determination of the drawn gate length in the proximate ring oscillator.
one can see the periodic pattern corresponding to individual dice.
6 4 Y
2 1
3
2
5
4
6
X
Figure 3 Within die position effect on frequency of RO oscillation .
Wafer Position Avg(Freq)
Freq(MHz) 18 19 20
CMOS 2-micron process. The chip floorplan is shown in Figure 1. Ring oscillators are distributed uniformly across the stepper field in a 6x6 array. All poly gates are drawn with a vertical orientation and are separated from other gates to prevent linewidth variations due to lens astigmatism or feature proximity effects.
8 6
RO2 MUX
Count/ Shift Registers
RO3
Y4
Count Out
2 1
Freq. Out
2
3
4
6
5
7
8
X
Figure 4 Within wafer position effect on frequency of RO oscillation
RO4
3.0
Analysis and Results
Measurements of RO frequency and gate linewidth have been analyzed to determine the effects due to their position within the wafer and their position within the die. The within wafer position effect for RO frequency is shown in Figure 3 as the average of all available RO’s, excluding outliers, at a given location on the 6x6 intra-die array. (Eight RO’s failed to operate on any die and therefore are not represented in this figure). Similarly, the wafer map of die averages of within wafer position is shown in Figure 4. Figure 5 shows the raw wafer map of frequencies, in which
Freq(MHz) 16 17 18 19 20 21
Figure 2 Ring oscillator design and frequency measurement strategy
40
30
2 Y 0
10
10
20
30
40
X
Figure 5 Wafer map of ring oscillator frequencies Considering within die position and within wafer position as separate treatments, analysis of variance has been conducted on an additive model for both RO frequency variation and drawn gate CD variation. The results are shown in Table 1 and Table 2, respectively.
3/3
D.F.
Sum of Squares
F Value
Pr(F)
Wafer Effect
47
5.91E13
74.27
0.00
Die Effect
27
2.84E13
62.17
0.00
Residuals
999
1.67E13
20.0
• • •
19.0
Frequency(MHz)
Table 1: ANOVA of Frequency Effects
quency vs. 1/CD. The resulting correlation coefficient is 0.342.
• •
•• •
18.0
Results of the F-test for frequency effects show that both the within wafer position effect and the within die position effect are highly significant. Moreover, the additive model has an R2=0.84, with within wafer position accounting for 57% of the overall variance and within die position accounting for an additional 27%.
The F-test for the drawn gate CD shows that both the die and wafer effects are significant as well. However, the additive model has an overall R 2 =0.29. While the within wafer position accounts for a sizeable 25% of the overall variance, the within die position effect accounts for only 4%. In the face of the 71% residual, the within die effect for the drawn gate CD is insignificant. Analysis of the CD measurement data indicates that the high noise level in the CD data is likely due to difficulty in accurately measuring the sheet resistance from the Van der Pauw structure.
Table 2: ANOVA of CD Effects D.F.
Sum of Squares
F Value
Pr(F)
Wafer Effect
51
4.6127
12.00
0.00
Die Effect
35
0.6649
2.52
2.3E-6
Residuals
1743
13.139
R2=0.29
Because of the relatively high noise level in the spatial CD model, we have attempted to correlate RO frequency with CD by taking within wafer position averages (averages of all points within the die). This averaging choice emphasizes the within wafer effect, which is much more significant than the within die effect. Figure 6 shows the scatter plot and leastsquares fit of within wafer position averages of fre-
• •
•
•
• •• • •• • • • • • • •• • ••• •• •
•
• •• •
•
•
•
• •
•• •
• 0.54
R2=0.84
•
0.55
0.56
0.57
0.58
0.59
1/CD(microns)
Figure 6 Frequency vs. 1/CD for within wafer position averages
4.0
Conclusions
The analysis of the RO frequency dependence on die and wafer position indicates a very strong effect from both causes. This can be the result only of one or more underlying process parameter variations with a similar spatial dependence. The attempt to correlate this spatial variation with the previously observed drawn gate CD variation shows only weak correlation when the more significant within wafer position effect is included. This is due to the fact that the data for CD cannot be well explained by a spatial model. There exists the possibility that the residual observed in the measurement data is due to fabrication noise; it is perhaps more likely that it is due to measurement noise and that the trend observed in the weak correlation has deeper roots. In order to expand upon the conclusions of this experiment, the test chip is being fabricated after a redesign to include a more robust CD measurement structure along with other location specific structures for device parameter extraction. We hope to correlate the observed frequency variation to either CD or other process parameters with spatial dependence.
Acknowledgments This research has been supported by the California State MICRO program under grant #95-113.
References [1] Crid Yu, Tinaung Maung, Costas Spanos, Duane Boning, James Cheung, Hua-Yu Liu, Keh-Jeng Chang, and Dirk Bartelink, “Use of Short-Loop Electrical Measurements for Yield Improvement”, IEEE Trans. Semicond. Manuf., vol. 8, no. 2. May 1995, pp. 150-159.
1/3
RING OSCILLATOR SENSITIVITY TO SPATIAL PROCESS VARIATION Mark Hatzilambrou, Andrew Neureuther, and Costas Spanos Department of Electrical Engineering & Computer Sciences University of California, Berkeley CA 94720 office: (510) 643-6776, home: (510) 635-1882, fax: (510) 642-2739 e-mail:
[email protected]
A test chip has been fabricated with a 6x6 array of ring oscillator (RO) test circuits and linewidth measurement structures to observe and explain spatial performance variation. On-chip counter circuitry allows the measurement and digital readout of frequency to 0.05% accuracy. Strong within wafer position and within die position effects on performance are observed.
1.0
Introduction
Analysis of process variation is undertaken to control or design around that variation in order to produce more manufacturable, and therefore less expensive, products. Thus, it is most important to understand the impact of the components of variation on the performance of the fabricated circuits in order to focus process control and design verification efforts on those high impact components. To date, the efforts to control or account for process variation have concentrated on global temporal and spatial uniformity and consistency. In circuit design, these variations have been accounted for as aggregate, random, mutually correlated parameter distributions. Intra-die variation has been an issue primarily in analog design where matching has been much more important than absolute control. Intra-die variation is increasingly difficult to avoid with large field sizes. Studies have shown a 10% intra-die linewidth variation which has a large deterministic component [1]. This allows the effect to be corrected or accounted for if the benefits exceed the costs. This study demonstrates a method for determining the degree of correlation between intra-die linewidth variations and overall circuit performance.
2.0
Experiment Design
Different circuit design styles are sensitive to different process variations, so it is necessary to decide at the outset the design style of interest. We have chosen to investigate high integration digital logic circuits. For the purpose of this study, it is significant that standard CMOS digital logic circuit performance
can be generalized relatively effectively by ring oscillator (RO) frequency. Although RO frequency is an excellent indicator of overall circuit performance of standard digital CMOS, care must be taken in choosing the stage gate. Variations in interconnect capacitance and resistance, threshold voltage, gate oxide thickness, mobility, and junction depth have all been shown to have significant impact on stage delay, depending on gate configuration. Because our initial purpose was to study the effect of intra-die linewidth variation on RO frequency, the stage gate is designed to make the RO realistically sensitive to linewidth variation. All gates are drawn at minimum length, reflecting actual design practice. The gate is an inverter with a single pull-up and single pull-down device. This non-stacked topology minimizes threshold variation impact. Finally, interconnect is minimized and a fanout of four provides predominantly gate capacitance loading. Alternatively, similar approaches could be taken if the goal were to study interconnect effects and minimize the effects of device parameter variation. Process Test Structures
Scribe Lane with
Abstract
CDTest RO
CDTest RO
CDTest RO
CDTest RO
CDTest RO
CDTest RO
CDTest RO
CDTest RO
CDTest RO
CDTest RO
CDTest RO
CDTest RO
CDTest RO
CDTest RO
CDTest RO
CDTest RO
CDTest RO
CDTest RO
CDTest RO
CDTest RO
CDTest RO
CDTest RO
CDTest RO
CDTest RO
CDTest RO
CDTest RO
CDTest RO
CDTest RO
CDTest RO
CDTest RO
CDTest RO
CDTest RO
CDTest RO
CDTest RO
CDTest RO
CDTest RO
Figure 1 Test chip layout The test chip has been fabricated in the UC Berkeley microfabrication facility using the baseline
2/3
An on-chip counter and multiplexor scheme is designed to allow testing of the chip by available standard autoprobe and DC parametric measurement equipment. As depicted in Figure 2, a set of four RO’s are multiplexed into a single count/shift register. An externally supplied timed pulse allows the pulse count to be stored on-chip and shifted out digitally. This provides better than 0.05% accuracy of frequency measurement.
RO1
...
...
Within Die Position Avg(Freq)
H )
Freq(MHz) 18.5 19
Accompanying the RO’s are linewidth test structures. These structures consist of a Van der Pauw sheet resistance measurement structure along with a 4-point resistor measurement structure to allow for the determination of the drawn gate length in the proximate ring oscillator.
one can see the periodic pattern corresponding to individual dice.
6 4 Y
2 1
3
2
5
4
6
X
Figure 3 Within die position effect on frequency of RO oscillation .
Wafer Position Avg(Freq)
Freq(MHz) 18 19 20
CMOS 2-micron process. The chip floorplan is shown in Figure 1. Ring oscillators are distributed uniformly across the stepper field in a 6x6 array. All poly gates are drawn with a vertical orientation and are separated from other gates to prevent linewidth variations due to lens astigmatism or feature proximity effects.
8 6
RO2 MUX
Count/ Shift Registers
RO3
Y4
Count Out
2 1
Freq. Out
2
3
4
6
5
7
8
X
Figure 4 Within wafer position effect on frequency of RO oscillation
RO4
3.0
Analysis and Results
Measurements of RO frequency and gate linewidth have been analyzed to determine the effects due to their position within the wafer and their position within the die. The within wafer position effect for RO frequency is shown in Figure 3 as the average of all available RO’s, excluding outliers, at a given location on the 6x6 intra-die array. (Eight RO’s failed to operate on any die and therefore are not represented in this figure). Similarly, the wafer map of die averages of within wafer position is shown in Figure 4. Figure 5 shows the raw wafer map of frequencies, in which
Freq(MHz) 16 17 18 19 20 21
Figure 2 Ring oscillator design and frequency measurement strategy
40
30
2 Y 0
10
10
20
30
40
X
Figure 5 Wafer map of ring oscillator frequencies Considering within die position and within wafer position as separate treatments, analysis of variance has been conducted on an additive model for both RO frequency variation and drawn gate CD variation. The results are shown in Table 1 and Table 2, respectively.
3/3
D.F.
Sum of Squares
F Value
Pr(F)
Wafer Effect
47
5.91E13
74.27
0.00
Die Effect
27
2.84E13
62.17
0.00
Residuals
999
1.67E13
20.0
• • •
19.0
Frequency(MHz)
Table 1: ANOVA of Frequency Effects
quency vs. 1/CD. The resulting correlation coefficient is 0.342.
• •
•• •
18.0
Results of the F-test for frequency effects show that both the within wafer position effect and the within die position effect are highly significant. Moreover, the additive model has an R2=0.84, with within wafer position accounting for 57% of the overall variance and within die position accounting for an additional 27%.
The F-test for the drawn gate CD shows that both the die and wafer effects are significant as well. However, the additive model has an overall R 2 =0.29. While the within wafer position accounts for a sizeable 25% of the overall variance, the within die position effect accounts for only 4%. In the face of the 71% residual, the within die effect for the drawn gate CD is insignificant. Analysis of the CD measurement data indicates that the high noise level in the CD data is likely due to difficulty in accurately measuring the sheet resistance from the Van der Pauw structure.
Table 2: ANOVA of CD Effects D.F.
Sum of Squares
F Value
Pr(F)
Wafer Effect
51
4.6127
12.00
0.00
Die Effect
35
0.6649
2.52
2.3E-6
Residuals
1743
13.139
R2=0.29
Because of the relatively high noise level in the spatial CD model, we have attempted to correlate RO frequency with CD by taking within wafer position averages (averages of all points within the die). This averaging choice emphasizes the within wafer effect, which is much more significant than the within die effect. Figure 6 shows the scatter plot and leastsquares fit of within wafer position averages of fre-
• •
•
•
• •• • •• • • • • • • •• • ••• •• •
•
• •• •
•
•
•
• •
•• •
• 0.54
R2=0.84
•
0.55
0.56
0.57
0.58
0.59
1/CD(microns)
Figure 6 Frequency vs. 1/CD for within wafer position averages
4.0
Conclusions
The analysis of the RO frequency dependence on die and wafer position indicates a very strong effect from both causes. This can be the result only of one or more underlying process parameter variations with a similar spatial dependence. The attempt to correlate this spatial variation with the previously observed drawn gate CD variation shows only weak correlation when the more significant within wafer position effect is included. This is due to the fact that the data for CD cannot be well explained by a spatial model. There exists the possibility that the residual observed in the measurement data is due to fabrication noise; it is perhaps more likely that it is due to measurement noise and that the trend observed in the weak correlation has deeper roots. In order to expand upon the conclusions of this experiment, the test chip is being fabricated after a redesign to include a more robust CD measurement structure along with other location specific structures for device parameter extraction. We hope to correlate the observed frequency variation to either CD or other process parameters with spatial dependence.
Acknowledgments This research has been supported by the California State MICRO program under grant #95-113.
References [1] Crid Yu, Tinaung Maung, Costas Spanos, Duane Boning, James Cheung, Hua-Yu Liu, Keh-Jeng Chang, and Dirk Bartelink, “Use of Short-Loop Electrical Measurements for Yield Improvement”, IEEE Trans. Semicond. Manuf., vol. 8, no. 2. May 1995, pp. 150-159.
1/3
RING OSCILLATOR SENSITIVITY TO SPATIAL PROCESS VARIATION Mark Hatzilambrou, Andrew Neureuther, and Costas Spanos Department of Electrical Engineering & Computer Sciences University of California, Berkeley CA 94720 office: (510) 643-6776, home: (510) 635-1882, fax: (510) 642-2739 e-mail:
[email protected]
A test chip has been fabricated with a 6x6 array of ring oscillator (RO) test circuits and linewidth measurement structures to observe and explain spatial performance variation. On-chip counter circuitry allows the measurement and digital readout of frequency to 0.05% accuracy. Strong within wafer position and within die position effects on performance are observed.
1.0
Introduction
Analysis of process variation is undertaken to control or design around that variation in order to produce more manufacturable, and therefore less expensive, products. Thus, it is most important to understand the impact of the components of variation on the performance of the fabricated circuits in order to focus process control and design verification efforts on those high impact components. To date, the efforts to control or account for process variation have concentrated on global temporal and spatial uniformity and consistency. In circuit design, these variations have been accounted for as aggregate, random, mutually correlated parameter distributions. Intra-die variation has been an issue primarily in analog design where matching has been much more important than absolute control. Intra-die variation is increasingly difficult to avoid with large field sizes. Studies have shown a 10% intra-die linewidth variation which has a large deterministic component [1]. This allows the effect to be corrected or accounted for if the benefits exceed the costs. This study demonstrates a method for determining the degree of correlation between intra-die linewidth variations and overall circuit performance.
2.0
Experiment Design
Different circuit design styles are sensitive to different process variations, so it is necessary to decide at the outset the design style of interest. We have chosen to investigate high integration digital logic circuits. For the purpose of this study, it is significant that standard CMOS digital logic circuit performance
can be generalized relatively effectively by ring oscillator (RO) frequency. Although RO frequency is an excellent indicator of overall circuit performance of standard digital CMOS, care must be taken in choosing the stage gate. Variations in interconnect capacitance and resistance, threshold voltage, gate oxide thickness, mobility, and junction depth have all been shown to have significant impact on stage delay, depending on gate configuration. Because our initial purpose was to study the effect of intra-die linewidth variation on RO frequency, the stage gate is designed to make the RO realistically sensitive to linewidth variation. All gates are drawn at minimum length, reflecting actual design practice. The gate is an inverter with a single pull-up and single pull-down device. This non-stacked topology minimizes threshold variation impact. Finally, interconnect is minimized and a fanout of four provides predominantly gate capacitance loading. Alternatively, similar approaches could be taken if the goal were to study interconnect effects and minimize the effects of device parameter variation. Process Test Structures
Scribe Lane with
Abstract
CDTest RO
CDTest RO
CDTest RO
CDTest RO
CDTest RO
CDTest RO
CDTest RO
CDTest RO
CDTest RO
CDTest RO
CDTest RO
CDTest RO
CDTest RO
CDTest RO
CDTest RO
CDTest RO
CDTest RO
CDTest RO
CDTest RO
CDTest RO
CDTest RO
CDTest RO
CDTest RO
CDTest RO
CDTest RO
CDTest RO
CDTest RO
CDTest RO
CDTest RO
CDTest RO
CDTest RO
CDTest RO
CDTest RO
CDTest RO
CDTest RO
CDTest RO
Figure 1 Test chip layout The test chip has been fabricated in the UC Berkeley microfabrication facility using the baseline
2/3
An on-chip counter and multiplexor scheme is designed to allow testing of the chip by available standard autoprobe and DC parametric measurement equipment. As depicted in Figure 2, a set of four RO’s are multiplexed into a single count/shift register. An externally supplied timed pulse allows the pulse count to be stored on-chip and shifted out digitally. This provides better than 0.05% accuracy of frequency measurement.
RO1
...
...
Within Die Position Avg(Freq)
H )
Freq(MHz) 18.5 19
Accompanying the RO’s are linewidth test structures. These structures consist of a Van der Pauw sheet resistance measurement structure along with a 4-point resistor measurement structure to allow for the determination of the drawn gate length in the proximate ring oscillator.
one can see the periodic pattern corresponding to individual dice.
6 4 Y
2 1
3
2
5
4
6
X
Figure 3 Within die position effect on frequency of RO oscillation .
Wafer Position Avg(Freq)
Freq(MHz) 18 19 20
CMOS 2-micron process. The chip floorplan is shown in Figure 1. Ring oscillators are distributed uniformly across the stepper field in a 6x6 array. All poly gates are drawn with a vertical orientation and are separated from other gates to prevent linewidth variations due to lens astigmatism or feature proximity effects.
8 6
RO2 MUX
Count/ Shift Registers
RO3
Y4
Count Out
2 1
Freq. Out
2
3
4
6
5
7
8
X
Figure 4 Within wafer position effect on frequency of RO oscillation
RO4
3.0
Analysis and Results
Measurements of RO frequency and gate linewidth have been analyzed to determine the effects due to their position within the wafer and their position within the die. The within wafer position effect for RO frequency is shown in Figure 3 as the average of all available RO’s, excluding outliers, at a given location on the 6x6 intra-die array. (Eight RO’s failed to operate on any die and therefore are not represented in this figure). Similarly, the wafer map of die averages of within wafer position is shown in Figure 4. Figure 5 shows the raw wafer map of frequencies, in which
Freq(MHz) 16 17 18 19 20 21
Figure 2 Ring oscillator design and frequency measurement strategy
40
30
2 Y 0
10
10
20
30
40
X
Figure 5 Wafer map of ring oscillator frequencies Considering within die position and within wafer position as separate treatments, analysis of variance has been conducted on an additive model for both RO frequency variation and drawn gate CD variation. The results are shown in Table 1 and Table 2, respectively.
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D.F.
Sum of Squares
F Value
Pr(F)
Wafer Effect
47
5.91E13
74.27
0.00
Die Effect
27
2.84E13
62.17
0.00
Residuals
999
1.67E13
20.0
• • •
19.0
Frequency(MHz)
Table 1: ANOVA of Frequency Effects
quency vs. 1/CD. The resulting correlation coefficient is 0.342.
• •
•• •
18.0
Results of the F-test for frequency effects show that both the within wafer position effect and the within die position effect are highly significant. Moreover, the additive model has an R2=0.84, with within wafer position accounting for 57% of the overall variance and within die position accounting for an additional 27%.
The F-test for the drawn gate CD shows that both the die and wafer effects are significant as well. However, the additive model has an overall R 2 =0.29. While the within wafer position accounts for a sizeable 25% of the overall variance, the within die position effect accounts for only 4%. In the face of the 71% residual, the within die effect for the drawn gate CD is insignificant. Analysis of the CD measurement data indicates that the high noise level in the CD data is likely due to difficulty in accurately measuring the sheet resistance from the Van der Pauw structure.
Table 2: ANOVA of CD Effects D.F.
Sum of Squares
F Value
Pr(F)
Wafer Effect
51
4.6127
12.00
0.00
Die Effect
35
0.6649
2.52
2.3E-6
Residuals
1743
13.139
R2=0.29
Because of the relatively high noise level in the spatial CD model, we have attempted to correlate RO frequency with CD by taking within wafer position averages (averages of all points within the die). This averaging choice emphasizes the within wafer effect, which is much more significant than the within die effect. Figure 6 shows the scatter plot and leastsquares fit of within wafer position averages of fre-
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•
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• •• • •• • • • • • • •• • ••• •• •
•
• •• •
•
•
•
• •
•• •
• 0.54
R2=0.84
•
0.55
0.56
0.57
0.58
0.59
1/CD(microns)
Figure 6 Frequency vs. 1/CD for within wafer position averages
4.0
Conclusions
The analysis of the RO frequency dependence on die and wafer position indicates a very strong effect from both causes. This can be the result only of one or more underlying process parameter variations with a similar spatial dependence. The attempt to correlate this spatial variation with the previously observed drawn gate CD variation shows only weak correlation when the more significant within wafer position effect is included. This is due to the fact that the data for CD cannot be well explained by a spatial model. There exists the possibility that the residual observed in the measurement data is due to fabrication noise; it is perhaps more likely that it is due to measurement noise and that the trend observed in the weak correlation has deeper roots. In order to expand upon the conclusions of this experiment, the test chip is being fabricated after a redesign to include a more robust CD measurement structure along with other location specific structures for device parameter extraction. We hope to correlate the observed frequency variation to either CD or other process parameters with spatial dependence.
Acknowledgments This research has been supported by the California State MICRO program under grant #95-113.
References [1] Crid Yu, Tinaung Maung, Costas Spanos, Duane Boning, James Cheung, Hua-Yu Liu, Keh-Jeng Chang, and Dirk Bartelink, “Use of Short-Loop Electrical Measurements for Yield Improvement”, IEEE Trans. Semicond. Manuf., vol. 8, no. 2. May 1995, pp. 150-159.
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RING OSCILLATOR SENSITIVITY TO SPATIAL PROCESS VARIATION Mark Hatzilambrou, Andrew Neureuther, and Costas Spanos Department of Electrical Engineering & Computer Sciences University of California, Berkeley CA 94720 office: (510) 643-6776, home: (510) 635-1882, fax: (510) 642-2739 e-mail:
[email protected]
A test chip has been fabricated with a 6x6 array of ring oscillator (RO) test circuits and linewidth measurement structures to observe and explain spatial performance variation. On-chip counter circuitry allows the measurement and digital readout of frequency to 0.05% accuracy. Strong within wafer position and within die position effects on performance are observed.
1.0
Introduction
Analysis of process variation is undertaken to control or design around that variation in order to produce more manufacturable, and therefore less expensive, products. Thus, it is most important to understand the impact of the components of variation on the performance of the fabricated circuits in order to focus process control and design verification efforts on those high impact components. To date, the efforts to control or account for process variation have concentrated on global temporal and spatial uniformity and consistency. In circuit design, these variations have been accounted for as aggregate, random, mutually correlated parameter distributions. Intra-die variation has been an issue primarily in analog design where matching has been much more important than absolute control. Intra-die variation is increasingly difficult to avoid with large field sizes. Studies have shown a 10% intra-die linewidth variation which has a large deterministic component [1]. This allows the effect to be corrected or accounted for if the benefits exceed the costs. This study demonstrates a method for determining the degree of correlation between intra-die linewidth variations and overall circuit performance.
2.0
Experiment Design
Different circuit design styles are sensitive to different process variations, so it is necessary to decide at the outset the design style of interest. We have chosen to investigate high integration digital logic circuits. For the purpose of this study, it is significant that standard CMOS digital logic circuit performance
can be generalized relatively effectively by ring oscillator (RO) frequency. Although RO frequency is an excellent indicator of overall circuit performance of standard digital CMOS, care must be taken in choosing the stage gate. Variations in interconnect capacitance and resistance, threshold voltage, gate oxide thickness, mobility, and junction depth have all been shown to have significant impact on stage delay, depending on gate configuration. Because our initial purpose was to study the effect of intra-die linewidth variation on RO frequency, the stage gate is designed to make the RO realistically sensitive to linewidth variation. All gates are drawn at minimum length, reflecting actual design practice. The gate is an inverter with a single pull-up and single pull-down device. This non-stacked topology minimizes threshold variation impact. Finally, interconnect is minimized and a fanout of four provides predominantly gate capacitance loading. Alternatively, similar approaches could be taken if the goal were to study interconnect effects and minimize the effects of device parameter variation. Process Test Structures
Scribe Lane with
Abstract
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Figure 1 Test chip layout The test chip has been fabricated in the UC Berkeley microfabrication facility using the baseline
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An on-chip counter and multiplexor scheme is designed to allow testing of the chip by available standard autoprobe and DC parametric measurement equipment. As depicted in Figure 2, a set of four RO’s are multiplexed into a single count/shift register. An externally supplied timed pulse allows the pulse count to be stored on-chip and shifted out digitally. This provides better than 0.05% accuracy of frequency measurement.
RO1
...
...
Within Die Position Avg(Freq)
H )
Freq(MHz) 18.5 19
Accompanying the RO’s are linewidth test structures. These structures consist of a Van der Pauw sheet resistance measurement structure along with a 4-point resistor measurement structure to allow for the determination of the drawn gate length in the proximate ring oscillator.
one can see the periodic pattern corresponding to individual dice.
6 4 Y
2 1
3
2
5
4
6
X
Figure 3 Within die position effect on frequency of RO oscillation .
Wafer Position Avg(Freq)
Freq(MHz) 18 19 20
CMOS 2-micron process. The chip floorplan is shown in Figure 1. Ring oscillators are distributed uniformly across the stepper field in a 6x6 array. All poly gates are drawn with a vertical orientation and are separated from other gates to prevent linewidth variations due to lens astigmatism or feature proximity effects.
8 6
RO2 MUX
Count/ Shift Registers
RO3
Y4
Count Out
2 1
Freq. Out
2
3
4
6
5
7
8
X
Figure 4 Within wafer position effect on frequency of RO oscillation
RO4
3.0
Analysis and Results
Measurements of RO frequency and gate linewidth have been analyzed to determine the effects due to their position within the wafer and their position within the die. The within wafer position effect for RO frequency is shown in Figure 3 as the average of all available RO’s, excluding outliers, at a given location on the 6x6 intra-die array. (Eight RO’s failed to operate on any die and therefore are not represented in this figure). Similarly, the wafer map of die averages of within wafer position is shown in Figure 4. Figure 5 shows the raw wafer map of frequencies, in which
Freq(MHz) 16 17 18 19 20 21
Figure 2 Ring oscillator design and frequency measurement strategy
40
30
2 Y 0
10
10
20
30
40
X
Figure 5 Wafer map of ring oscillator frequencies Considering within die position and within wafer position as separate treatments, analysis of variance has been conducted on an additive model for both RO frequency variation and drawn gate CD variation. The results are shown in Table 1 and Table 2, respectively.
3/3
D.F.
Sum of Squares
F Value
Pr(F)
Wafer Effect
47
5.91E13
74.27
0.00
Die Effect
27
2.84E13
62.17
0.00
Residuals
999
1.67E13
20.0
• • •
19.0
Frequency(MHz)
Table 1: ANOVA of Frequency Effects
quency vs. 1/CD. The resulting correlation coefficient is 0.342.
• •
•• •
18.0
Results of the F-test for frequency effects show that both the within wafer position effect and the within die position effect are highly significant. Moreover, the additive model has an R2=0.84, with within wafer position accounting for 57% of the overall variance and within die position accounting for an additional 27%.
The F-test for the drawn gate CD shows that both the die and wafer effects are significant as well. However, the additive model has an overall R 2 =0.29. While the within wafer position accounts for a sizeable 25% of the overall variance, the within die position effect accounts for only 4%. In the face of the 71% residual, the within die effect for the drawn gate CD is insignificant. Analysis of the CD measurement data indicates that the high noise level in the CD data is likely due to difficulty in accurately measuring the sheet resistance from the Van der Pauw structure.
Table 2: ANOVA of CD Effects D.F.
Sum of Squares
F Value
Pr(F)
Wafer Effect
51
4.6127
12.00
0.00
Die Effect
35
0.6649
2.52
2.3E-6
Residuals
1743
13.139
R2=0.29
Because of the relatively high noise level in the spatial CD model, we have attempted to correlate RO frequency with CD by taking within wafer position averages (averages of all points within the die). This averaging choice emphasizes the within wafer effect, which is much more significant than the within die effect. Figure 6 shows the scatter plot and leastsquares fit of within wafer position averages of fre-
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•
•
• •• • •• • • • • • • •• • ••• •• •
•
• •• •
•
•
•
• •
•• •
• 0.54
R2=0.84
•
0.55
0.56
0.57
0.58
0.59
1/CD(microns)
Figure 6 Frequency vs. 1/CD for within wafer position averages
4.0
Conclusions
The analysis of the RO frequency dependence on die and wafer position indicates a very strong effect from both causes. This can be the result only of one or more underlying process parameter variations with a similar spatial dependence. The attempt to correlate this spatial variation with the previously observed drawn gate CD variation shows only weak correlation when the more significant within wafer position effect is included. This is due to the fact that the data for CD cannot be well explained by a spatial model. There exists the possibility that the residual observed in the measurement data is due to fabrication noise; it is perhaps more likely that it is due to measurement noise and that the trend observed in the weak correlation has deeper roots. In order to expand upon the conclusions of this experiment, the test chip is being fabricated after a redesign to include a more robust CD measurement structure along with other location specific structures for device parameter extraction. We hope to correlate the observed frequency variation to either CD or other process parameters with spatial dependence.
Acknowledgments This research has been supported by the California State MICRO program under grant #95-113.
References [1] Crid Yu, Tinaung Maung, Costas Spanos, Duane Boning, James Cheung, Hua-Yu Liu, Keh-Jeng Chang, and Dirk Bartelink, “Use of Short-Loop Electrical Measurements for Yield Improvement”, IEEE Trans. Semicond. Manuf., vol. 8, no. 2. May 1995, pp. 150-159.
