RIPPLE CARRY ADDER USING FIVE INPUT MAJORITY GATES Bhupesh Bishnoi, Giridhar.M, Shoubhik Gupta Department of Electrical Engineering Indian Institute of Technology Kanpur Kanpur, India
[email protected],
[email protected] [email protected] Abstract— Quantum dot Cellular Automata (QCA) is a transistor less computational model which is expected to provide high density nanotechnology implementations of various CMOS circuits. QCA has been constrained by the number of basic gates available. This paper aims at using five input majority gate to implement two adder circuits achieving implementation in lesser number of cells and higher density. Keywords- QCA; ripple carry adder; BCD adder; majority gate.
I.
INTRODUCTION
The growth of CMOS industry has been based mainly on the reduction in transistor sizes and thus increasing the packing density. The CMOS industry for the last three decades has tried to follow Moore’s law which states that number devices integrated on a chip doubles every eighteen months. But in recent years we have almost reaches the physical limit of photo lithography as well has physical size of the FETs. Having FETs with sizes less that 0.1 micron have brought about new set of problems. Thus increasing density has become a momentous task in recent years. It’s now realized by the international community that in the next two decades the semiconductor industry has to start using various nanotech devices to keep up with the Moore’s law [1]. The various nanotech devices and technology under consideration include Resonant tunneling diode (RTD), Quantum dot Cellular Automata (QCA), Tunneling Phase Logic (TPL) and Single Electron Tunneling (SET) [2]. Of these QCA has shown to have lesser power consumption, higher density and also higher switch speed [3]. The other advantage of using the QCA is that the building material of both the gates and the wires are the same. The QCA architecture has just two primary gates the inverter and the three input majority gate. This has been considered both a boon and bane, while it’s advantageous for quick and easy implementation of various logic gate. It has proved that even implementation of simple two input gates requires the use of multiple QCA gates thus increasing the complexity. This paper aims at using a five input majority gate for the implementation of certain complex circuits.
Dr. Bahniman Ghosh, Nagaraju.M Department of Electrical Engineering Indian Institute of Technology Kanpur Kanpur, India
[email protected],
[email protected]
II.
QCA BASIC CELL
QCA and the QCA cell were first introduced by Prof. C. S. Lent at the University of Notre Dame [4]. QCA architecture is based on the coulombic interactions between many identical QCA cells; each constructed using four to six electronic sites coupled through quantum mechanical tunneling barriers. In semiconductor implementations, these sites are realized using coupled quantum dots with different potential cell geometries. The cells are capable of having two mobile electrons which repel each other due to the coulombic repulsion, and, in the ground state, tend to occupy the diagonal sites of the cell. Binary information can be encoded in the position of the electrons in the cell. Thus this bi-stable property of QCA cells [5] provides a way to implement digital logic in to the QCA architecture. Also in this paper we consider the four dot implementation of the QCA cell. III.
CELL CLOCKING
QCA clocking is a very important aspect of the architecture the various functions of the clock in the architecture is summarized below: a) Provides a mechanism for synchronizing information flow through the circuit. b) Other technologies have a inbuilt sense of direction flow but in QCA the clock controls the direction of the flow of information in a circuit. c) The QCA clock has also been shown to provide the power gain required for proper circuit operation [6]. d) Also the clock avoids the cells going into meta-stable states. QCA computation is performed by controlling the tunneling with a four phase “clock” signal as shown in Fig.1, 2. The clocking of QCA can be accomplished by controlling the potential barriers between adjacent quantum-dots [7-9]. The clock used in QCA consists of four phases: hold, release, relax, and switch. Each clock lags the previous by 90° [10].
IEEE EDSSC 2012, 3 - 5 December 2012, Chulalongkorn University, Bangkok Thailand.
wire. At this angle, the coupling between cells is negative and can be exploited to realize the compliment function.
Fig.1. Clock During the switch phase, the barrier is gradually raised, and the QCA cell settles down to one of the two ground polarization states as influenced by its neighbors. During the hold phase, the barrier is held high, suppressing electron tunneling and maintaining the current ground polarization state of the QCA cell. During the release and relax phases, the barriers are lowered, and the excess electrons gain mobility. In these two phases, a QCA cell remains un-polarized. The clocking zones in the QCA architecture also determine the flow of information in the circuit these and be seen in the figures.
Fig. 3: Inverter
B. Majority Gate The fundamental logic primitive available with QCA technology is the majority gate. This gate performs the following Boolean function: M (A, B, C) = AB + BC + CA At least two of the inputs to the gate must be asserted before the output is asserted. This gate is a member of the higher class of threshold gates where the sum of weighted inputs must exceed the threshold before the output is asserted. The three-input majority gate is implemented with the layout shown in Fig 4.
Fig.4: Majority Gate The majority gate can be programmed to perform the Standard AND and OR operations by fixing the polarization to one of the three available inputs as illustrated in Fig. 5.
Fig.2: Different Phases of clock IV.
QCA LOGIC
A. Inverter The most common inverter design is shown in Fig. 3. This fork inverter has two legs of the input QCA wire which interact at a 45-degreeangle with the first cell of the output
Fig. 5: AND & OR Gates
IEEE EDSSC 2012, 3 - 5 December 2012, Chulalongkorn University, Bangkok Thailand.
V.
QCA DESIGNER
QCADesigner is the product of an ongoing research effort by the Walus Group at the University of British Columbia to create a design and simulation tool for Quantum Dot Cellular Automata (QCA). The designer tool provides the designer to quickly layout a QCA design and also to simulate it. QCADesigner has provided a new platform for developers, and results from simulations using this tool have been published by several international groups [11]-[16] VI.
MAJORITY GATE
The function of the majority gate is to mimic the majority input onto the output. The three input majority gate is the basic component of the QCA architecture and other gates like AND and OR are designed using this. While this is ideal for small circuits for larger circuits with increased number of inputs the three input majority gate can be replaced by a five input gate[17] in order to decrease the number of active gates and the number of cells used. The table 1 shows the clear advantage of using a five input majority gate.
Fig.7: Output of Full-adder
TABLE 1 Inputs to 5 input majority gate 1
2
3
4
5
Number of 3 input gates to be used
A(B+C)
A
A
B
C
0
2
A(B+C+D)+BCD
A
A
B
C
D
6
A(BC+BD+CD)+BCD
A
0
B
C
D
5
A(B+C+D)+BC+BD+CD
A
1
B
C
D
5
Boolean Function
The major component in the ripple carry adder is a full adder circuit the circuit of the full adder and the output are as in fig. 6 and fig. 7.
Fig. 6: Full Adder Layout.
VII. RIPPLE CARRY ADDER This is the basic among the multiple bit adder designs. In this design the bit of the LSB are added first and then the carry in transferred to the next adder in the circuit where the next significant bits are added and this goes on. This is an ineffective method for addition with large numbers but for with numbers with small number of bits it’s the least complicated and easy to implement design. The layout and results are presented in figures 8,9,10.
Fig. 8: Proposed Ripple Carry Adder
IEEE EDSSC 2012, 3 - 5 December 2012, Chulalongkorn University, Bangkok Thailand.
VIII. CONCLUSION AND FUTURE WORKS The circuit uses lesser number of cells compared to traditional circuit [18-19] and is more densely packed. The circuit has been simulated using QCA designer and the results shown. In extension to this work a fault tolerant majority gate can be used and hence making the circuit more suitable of physical implementation. REFERENCES [1]
Fig. 9: Results (1)
Fig.10. Results (2)
D.A. Antonelli. D.Z. Chen, T.J. Dysart, and X.S. Hu, "quantum-dot cellular automata (QCA) circuit partitioning: Problem modeling and solution", in Proc. of Design Auto. Conf., (san Diego, CA), June 2004 [2] "The intenationaltecnology roadmap for semiconductors: Emerging research devices." http://www.itrs.net/, 2005 [3] R.Zhang, K. Walus, W. Wang, and G.A. Jullien, "A majority reduction technique for adder sturctures in quantum-dot cellular", in Proceedings of SPIE 5559, pp.91-100,2004. [4] P.D. Tougaw and C.S. Lent, "logical devices implemented using quantum cellular automata", J. Appl. Phys., vol. 75, pp. 1818-1825, feb 1994. [5] B. Meurer, D. Heitmann and K. Ploog, “Excitation of three dimensionalquantum dots,” Physical Review B, 48, pp. 11488–11491, 1993. [6] J. Timler and C. S. Lent, BPower gain anddissipation in quantum-dot cellularautomata,[ J. Appl. Phys., vol. 91, no. 2,pp. 823–831, Jan. 2002. [7] P. D. Tougaw and C. S. Lent, BDynamic behavior of quantum cellular automata,J. Appl. Phys., vol. 80, no. 8, pp. 4722–4735,Oct. 1996. [8] R. K. Kummamuru, A. O. Orlov,R. Ramasubramaniam, C. S. Lent,G. H. Berstein, and G. L. Snider, Operationof a quantum-dot cellular automata (QCA)shift register and analysis of errors,IEEE Trans. Electron Devices, vol. 50, no. 9,pp. 1906–1913, Sep. 2003. [9] C. Gyo¨rgy et al. BNanocomputing by fieldcouplednanomagnets,[ IEEE Trans. Nanotechnol.,vol. 1, no. 4, pp. 209–213, Dec. 2002. [10] V. Vankamamidi, M. Ottavi and F. Lombardi, “Twodimensionalschemes for clocking/timing of QCA circuits,” IEEE Transactions onComputer-aided Design of Integrated Circuits and Systems, vol. 27,pp. 34–44, 2008. [11] K. Walus, A. Vetteth, G. A. Jullien, and V. Dimitrov, Design and simulation of quantum-dot cellular automata, presentedat the Symp. Microelectronics Research andDevelopment in Canada, Ottawa, ON,Canada, 2002. [12] W. J. Townsend and J. A. Abraham, Complexgate implementations for quantum dot cellularautomata, in Proc. IEEE Conf. Nanotechnology,2004, pp. 625–627. [13] J. Huang, M. Momenzadeh, M. B. Tahoori,and F. Lombardi, Defect characterization forscaling of QCA devices, in Proc. 19th IEEEInt. Symp. Defect and Fault Tolerance in VLSISystems, 2004, pp. 30–38. [14] K. Kim, K. Wu and R. Karri, “Quantum-dot cellular automata designguideline,” IEICE Transaction Fundamentals, vol. E89-A, pp. 1607–1614, 2006. [15] J. Huang, M. Momenzadeh, M. B. Tahoori, and F. Lombardi, Design and characterizationof an and-or-inverter (AOI) gate for QCAimplementation, in Proc. ACM Great Lakes Symp. VLSI, 2004, pp. 426–429. [16] M. B. Tahoori and F. Lombardi, Testing of quantum dot cellular automata based designs, in Proc. Design, Automation and Test in Europe Conf. and Exhibition, 2004, pp. 1408-1409. [17] [17] Rami Akeela, Meghanad D. Wagh, "A five- input Majority gate in Quantum cellolar automata", NSTI-Nanotech 2011. [18] K. Kim, K. Wu and R. Karri, “The robust QCA adder designs usingcomposable QCA building blocks,” IEEE Transactions on ComputeraidedDesign of Integrated Circuits and Systems1, vol. 26, pp. 176–183, 2007. [19] I. Hänninen and J. Takala, “Binary Adders on Quantum-Dot CellularAutomata,” Journal Signal Processing Systems, vol. 58, pp. 87– 103, 2010
IEEE EDSSC 2012, 3 - 5 December 2012, Chulalongkorn University, Bangkok Thailand.
