Simplifying Sequential Gate-Level Test Generation Through - CiteSeerX

Simplifying Sequential Gate-Level Test Generation Through Exploitation of High-Level Information F. Ferrandi #

F. Fummi #

E. Macii z

# Politecnico di Milano

Dip. di Elettronica e Informazione Milano, ITALY 20133

Abstract

Sequential test generation for large and complex designs, when performed at the gate-level, is known to be a dicult task. Highlevel testing strategies, on the other hand, are less computation intensive, but suer from accuracy problems. In this paper we propose to exploit high-level information to simplify gate-level test generation. In particular, we propose to compute a set of test sequences starting directly from the VHDL description of the system being synthesized, without any knowledge of the nal realization of the design. Such test sequences are then simulated at the gate-level in order to reduce the number of faults for which a test needs to be determined by the gate-level test generation tool, thus allowing substantial time savings. Experimental results, though preliminary, show the eectiveness of the proposed technique.

1 Introduction

The advent of powerful hardware description languages (HDLs), such as VHDL, and the development of synthesis techniques accepting, as input, HDL descriptions have radically changed the scenario of digital system design. HDLs enable the speci cation of complex hardware systems at very high-levels of abstraction. This allows considerable time and resource savings in the chip development process, since engineers are no longer required to pay attention to some tedious design details as they were in the past. In fact, such details are handled by the synthesis tools commonly used to map the highlevel speci cation of the system onto a target library of components (i.e., simple logic gates or more complex structures, such as multiplexers). Though the high-level synthesis approach is not yet completely mature (human intervention is still required at some critical stages of the design process), it is getting more and more accepted even by the designers belonging to the industrial community. Besides the speci cation and the design phases, an industrial synthesis ow usually includes also a test generation (TG) phase. Even though some attempts to realize high-level test pattern generation tools have been made in the past (see, for example, [1, 2, 3, 4, 5, 6, 7]), for accuracy reasons, the test generation step is commonly performed at the gate-level, that is, starting with an implementation of the sequential circuit under development. Clearly, this is the best solution, in terms of fault-coverage, that can be obtained. However, the problem which arises when this path is followed has to do with the size of the circuits that state-of-the-art sequential test generators (e.g., HITEC [8], Veritas [9]) are able to handle in reasonable time and with limited

M. Poncino z

D. Sciuto #

Politecnico di Torino Dip. di Automatica e Informatica Torino, ITALY 10129 z

computation resources. The fact that high-level test generation is not yet practically eective does not necessarily imply that the knowledge of the system behavior has to be totally ignored. Therefore, the solution to the complexity of gate-level test generation we propose in this paper goes towards the exploitation of the available highlevel information to aid the calculation of the test patterns for the nal implementation of the design. Our approach is based on the idea of providing to the gatelevel test generator and the associated fault simulator some test sequences calculated from the high-level circuit description using the stuck-at fault model. Obviously, this helps the TG process, since the total number of faults for which a test sequence needs to be generated results smaller after the test set computed on the high-level description has been simulated. The main steps required by our strategy are the following. We start with a VHDL description of the system being synthesized, whose architecture may contain both controllers and data-paths. Such architecture is linearized (in the sense proposed by Rho and Somenzi in [10]) through cycle elimination; to do that, the latches that need to be inserted into the scan chain are identi ed. After this transformation is applied, the VHDL description is suitable for synthesis through a commercial tool, such as Synopsis [11] or Autologic [12], and a gate-level implementation is obtained for which test generation is required. From the linearized VHDL description, using the symbolic algorithms of [13], a two-level cover of each module is calculated and stored using BDDs [14]. Redundant faults associated to any prime implicant in the covers are identi ed and removed using the algorithm described in [15]. Test sequences for the faults in the essential primes of the optimized covers are then computed using the technique of [16] and passed to the tool which is in charge of determining the global test set for the synthesized design, thus simplifying its task. A technique somehow related to ours was presented by Dave and Patel in [17]. However, in that work, only combinational circuits without hierarchical structure were considered. In addition, the application of the algorithm was intrinsically limited by the representation (an explicit table) chosen to generate and manipulate the two-level AND/OR network corresponding to the functional description of the circuit. As a result, only very small examples were used to demonstrate the applicability and the eectiveness of the approach. The plan of the paper is as follows. Section 2 describes our technique. Section 3 summarizes the work by Dave and Patel, so as to provide a reference for our approach. Section 4 presents a dis-

cussion on preliminary experimental results. Finally, Section 5 gives concluding remarks and directions for future research.

2 Our Approach

The technique we present is based on the assumption that the system under consideration is described as a network of VHDL entities modeling interacting nite state machines controlling data-paths (IFSMDs). In fact, this is the most commonly adopted formalism in industrial synthesis of highly complex devices. In addition, it is assumed that the testability for the data portion of the system is obtained through scan registers and appropriate driving circuitry; in fact, this is what is commonly done in the development of practical designs. Therefore, the focus is on the control part of the system. In the most general case, the system topology consists of an arbitrary directed graph. However, for our purposes, we are interested in architectures whose connection graphs are directed acyclic graphs (DAGs). Therefore, the original system is transformed into a serial (cascade) decomposition through an initial elimination of the cycles and a subsequent application of the linearization procedure proposed by Rho and Somenzi in [10]. Clearly, cycle elimination imposes the insertion into the scan chain of some memory elements which have been synthesized as the interface between the distinct entities. The linearization, on the other hand, simply requires to add dummy input and output ports to some VHDL entities so as to mimic the structure of a topological sort. The topology of the system we end-up with after the application of the above transformations is then the one shown in Figure 1. Entity #1

Entity # i−1

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Figure 1: Linearized System Architecture. At this point, the following operations are performed in order to compute, before the design is actually synthesized, a set of test sequences that may help the TG tool to determine a test set for the nal gate-level realization of the circuit:  Extraction of the global relation of the nite state machine associated to each VHDL entity. Such relation, describing the input/output behavior and the state transitions of the FSM, is derived directly from the VHDL code and it is stored implicitly using BDDs through the application of the procedure proposed in [13]. The extraction of the global relation from VHDL is carried out by looking at the speci c style used to design the entities. Typically, the VHDL description consists of a process embedding a conditional structure (either an IF-THEN-ELSE statement or a CASE statement) that models the nite state machine. Automatic translation of these particular descriptions is thus feasible.  For each system entity (now represented by its symbolic relation), a minimal two-level cover is determined through application of the procedure by Coudert and Madre [18]. Such cover is again represented using BDDs and consists of a sum of prime implicants, some of which are essential primes.  For each system entity, faults in all the prime implicants forming the two-level cover are rst identi ed using the model proposed in [13]. Three classes are considered: (a) SA-1 faults on all literals of each prime; (b) SA-0





faults on one literal of each prime; (c) SA-0 and SA-1 faults on all input variables. Faults are then injected one at a time into the global relation, to compute the corresponding faulty relations. Redundant faults in all the primes are then detected and removed, so as to obtain an optimized version of the twolevel cover. In order to perform the removal, redundancies in a speci c entity must be proved with respect to the neighboring system components. Since there exists a serial decomposition in the design, as shown in Figure 1, we can resort to the application of the technique presented in [15]. The method works as follows: Given the two-level cover of an entity, the set of components that are in the transitive fanin of such entity can be used as an equivalent driving (or controlling) machine to allow logic optimization via constrained redundancy removal. In this context, redundancies are removed by exploiting the sequences produced by the controlling machine, which are used as input don't care sequences to the given component. The process is iterated on each system component, so as to reduce the size of the two-level cover as much as possible. A set of test sequences can now be generated for faults corresponding to the essential primes of the optimized two-level cover using the approach of [16]. Here, given a speci c entity containing the fault, a three-way partition is induced on the global architecture, to identify: { The machine under test (MUT), i.e., the component itself; { The observing network (ON), consisting of all the components in the transitive fanout of MUT, with respect to the serial decomposition; { The controlling network (CN), consisting of all the components in the transitive fanin of MUT, with respect to the serial decomposition. The symbolic algorithm, based on eective representation of test sequences and state manipulation, computes the test for the faults, in terms of the circuit external inputs. It is important to observe that, since the two-level covers for which test sequences need to be generated have been optimized, chances of successful computation of such sequences increase.

Since faults in the essential primes of the optimized two-level cover will be surely present in the nal implementation of the synthesized circuit, the corresponding test sequences are guaranteed to be helpful for the gate-level fault simulator, thus resulting in a reduction of the amount of work required by the gate-level test generator. In addition, since redundant faults corresponding to prime implicants have been already removed from the two-level covers, if such covers are used as input descriptions for the synthesizer, chances are high that the nal circuit implementation will have less redundancies than the case where synthesis is performed directly from the VHDL description.

3 Comparison to Previous Work

In [17], Dave and Patel have presented an high-level test generation procedure which is somehow comparable to the technique we have outlined in Section 2.

The ultimate goal consists of generating test vectors (and not test sequences, since only combinational circuits are considered) for stuck-at faults in circuits synthesized from a functional description without resorting directly to the structural information available at the gate-level. The procedure takes, as input, the functional description of the circuit being tested, and translates it into a table of product terms. Some degrees of minimization are performed on such table by application of Espresso [19], and a two-level AND/OR circuit is derived from the optimized table. The set of test vectors to detect all single stuck-at faults in the two-level circuit are then computed through a test generation program similar to Podem [20]. Finally, the fault-coverage (computed without considering undetectable faults) for the implementation of the functional speci cation is evaluated through simulation of the test vectors previously determined. In all the cases where the obtained fault coverage is not satisfactory (i.e., it is below a xed threshold), an optional step can be taken to improve the quality of the test set computed so far. The idea exploited by this additional phase consists of using the Espresso minimizer to generate a new table containing the product terms of the complement of the function speci ed at the high-level. From such table, a product-of-sums circuit description is generated and the test vectors computed during the rst phase are simulated on it. The Podem-like test generator is then invoked to generate test vectors for the faults that have remained undetected after simulation, and such vectors are used to augment the overall test set for the circuit. The rst observation that can be made about the algorithm summarized above is that, conversely from our approach, the functional description of the circuit is stored as a sum-of-products through an explicit table. Clearly, this limits the applicability of the method to very small circuits, since the size of the table is exponential in the number of circuit inputs. In our method, on the other hand, the high-level speci cation of the design (i.e., the VHDL code of each system entity) is translated directly into a BDD, thus increasing the chances of handling large circuits. The same argument applies to the minimization step, since the optimization of the sum-of-products in [17] is performed using Espresso, while in our approach the BDD-based procedure of [18] is employed. Besides the dierence in the ultimate target (Dave and Patel are aiming at computing the complete test set of a circuit starting from the functional speci cation, while we are proposing to use the set of test sequences calculated at the high-level as an aid for the gate-level test generator), there is another substantial dierence that needs to be pointed out in the comparison of the two methods. In [17] redundant faults are not considered; test vectors are then generated only for detectable faults, but no indication is given about the way redundant faults are identi ed. In our approach, on the other hand, we nd redundant faults in the two-level circuit, and we use this information for two purposes:  To further simplify the two-level circuit through redundancy removal. This simpli es the calculation of the test sequences at the high-level.  In case the two-level covers are used as starting point for the synthesis, it is possible for the nal circuit implementation to contain fewer redundancies than the case where the initial VHDL description is used as input to the synthesizer. This may simplify the test generation step at the gate-level. Last, but not least, the method of [17] only considers combina-

tional circuits with no hierarchy inside. On the contrary, the technique we propose is applicable to complex, sequential speci cations described using the hierarchical paradigm allowed by VHDL.

4 Experimental Results

The eciency of the proposed technique has been tested by analyzing an industrial telecom controller, and experimental data have been obtained on a Sun SparcStation 20/125. The design is described in VHDL and it is composed of several interconnected control entities driving a data-path. Part of the data-path section has been removed since we assume that it is testable (possibly by applying a scan-path technique). The control logic, on the other hand, originates an IFSM (partially shown in Figure 2) containing a total of ve components. The implementation of the circuit is synthesized by Autologic [12] starting from its VHDL representation. It is composed of 77 memory elements and approximately 700 gates. Simple test pattern generation at the gate level for the entire circuit is not feasible. For instance, HITEC [8] achieves a fault coverage of 55.1% after 6.2 hours of computation. Moreover, a standard scan-path technique results very expensive. To give an idea, we applied OPUS [21] to the circuit to identify memory elements to be connected into a scan-chain. The full scan methodology requires three additional pins and a 50% increase in the number of gates. A partial scan approach requires a very large number of clock cycles for test application, while a partial scan technique that allows parallel loading results in an acceptable test application time but with the same implementation cost of the full scan methodology. Therefore, this is an example where a testing approach exploiting high-level information is required. With the current implementation of our method we are able to back-propagate test sequences for one level only; thus, the global circuit is initially partitioned into ve blocks of interconnected entities that are separately analyzed. Such blocks are reported in Table 1. The rst ve columns report the complexity of each block in terms of number of inputs, outputs, literals, gates, ip- ops, and stuck-at faults. Columns named HITEC show the results obtained by direct application of HITEC; in particular, FC indicates the total fault coverage, TL the test length, and CPU the total execution time. On the other hand, columns named Proposed+HITEC show the results achieved by rst generating test sequences at the VHDL level with the proposed approach, and eventually simulating those sequences before running HITEC. The results show that the combined approach results in an improvement in both coverage and test length. Furthermore, CPU time is reduced by about one order of magnitude, except for those circuits for which test generation time is so small to make the computational overhead not negligible. A second experiment concerns the removal of redundancies at the VHDL level by minimizing the two level representation of each module before logic synthesis; redundancy removal is performed across pairs of modules as described in Section 2. Table 2 reports two implementations of the telecom device of Figure 2. The rst one (STANDARD) has been directly synthesized from the original VHDL description, while the second one (MINIMIZED) has been synthesized from an intermediate, reduced, two-level representation of the same VHDL description, minimized by reduction of redundant faults. Notice that the same redundancy removal algorithm [15] cannot be directly applied at the gate level due to the unmanageable BDD sizes. Results reported in Table 2 show that the gate-level TPG sensibly improved its performance in terms of both CPU time and

halt start_master

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Figure 2: IFSM Description of a Telecom Device.

Name sync master master sync math master math chp chp memory

Implementation STANDARD MINIMIZED

IN 10 11 10 26 28

HITEC Proposed + HITEC OUT Lits. Gates FF Faults FC [%] TL CPU FC [%] TL CPU 7 134 80 13 228 93.4 174 1.3s 96.7 174 5.3s 8 134 80 13 232 98.2 145 0.5s 98.2 137 0.2s 26 541 298 19 816 97.3 583 1.5m 97.5 665 13.9s 27 579 316 16 814 96.9 846 1.5m 97.2 744 14.2s 21 601 325 20 832 94.2 1770 10.1m 98.8 564 54.3s Table 1: Results for the Proposed Approach Applied to Sub-Blocks.

IN OUT Lits. Gates. FF Faults Aborted Redundant FE [%] TL 25 37 1214 683 77 1812 760 53 58.1 169 25 37 667 378 33 996 196 496 80.3 197 Table 2: Results for the Proposed Approach Applied to Dierent Implementations.

CPU 373.6m 115.2m

fault eciency (Column FE) when the MINIMIZED circuit was used.

5 Concluding Remarks and Future Work

The intrinsic diculty of generating a test set for complex, hierarchical designs through gate-level TG tools has been the motivation of this work. What we have proposed is, in fact, a technique which provides an aid to existing test generators (HITEC in our speci c case) when an high-level speci cation of the design (the VHDL description in our case) is available. The method makes use of symbolic algorithms (whose main feature is the use of BDDs to compactly represent large Boolean functions) to handle circuits of interest. Experimental results, though preliminary, indicate some promise in the method shown here. As future work, the rst step we are intending to take consists of increasing the degree of automation for the proposed testing strategy. In addition, we are planning on investing some eorts in studying how the information about redundant faults identi ed in the two-level covers can be translated back to the VHDL descriptions of the system entities. In case of success, this will allow us to perform redundancy removal directly at the VHDL level, thus enabling a potentially better realization of the design during VHDL synthesis.

References

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