Simulation of the Hello World Application for the ... - Semantic Scholar

Simulation of the Hello World Application for the Field-programmable Port Extender (FPX) John W. Lockwood, Washington University, Applied Research Lab http://www.arl.wustl.edu/arl/projects/fpx/ Spring 2001 Gigabit Kits Workshop Supported by NSF-ANI-0096052 and Xilinx Corp

Field Programmable Port Extender (FPX)

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The HelloWorld Testbench – Visit • http://www.arl.wustl.edu/arl/projects/fpx/workshop_0101/

– Download HelloWorld Testbench • Right-click on HelloTestbench.tar • Save Target in: D:\fpx\

– Access Files in Cygwin Bash Shell • Start > Programs > Cygwin > Bash • cd /cygdrive/d/fpx/ • tar xvf HelloTestbench.tar • cd HelloTestbench.tar • ls

Field Programmable Port Extender (FPX)

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Problem Statement • General Statement – “Implement a plug-in module that monitors a traffic flow. For cells with payloads that begin with “Hello”, have the module replace the following bytes with “World”.

• Details – Scan Flows on VCI=5 – Match the content of the cell for the “HELLO” • ASCII: “HELLO” • Hex: 48 – 45 – 4C – 4C – 4F • Binary: 0100,1000 - 0100,0101- 0100,1100 - 0100,1100 - 0100,1111

– Replace following contents with “WORLD.” • ASCII “WORLD.” • Hex: 57 – 4F – 52 – 4C – 44 – 2E • Binary: 0101,0111 – 0100,1111 – 0101,0010 – 0100,1100 – 0100,0100 – 0010,1110

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Field Programmable Port Extender (FPX)

“Hello, World” Module Function Compare

Header

VPI

VCI=5

[5 bytes in 2 words]

VPI=X

PAD

VCI=5

Match

PAD

’H’ ’E’ ’L’ ’L’

’H’ ’E’ ’L’ ’L’

Match

Payload

’O’

P5

P7

’O’ ’ ’ ’W’’O’

Match+Write

[48 bytes in 12 words]

P8

P9 P10 P11

’R’ ’L’ ’D’ ’.’

Write Copy

P6

...

.. Payload ..

.. Payload ..

P44 P45 P46 P47

P44 P45 P46 P47

... Copy

JWL:ARL 07/00

32 bits

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Case 1: Mismatched VCI Compare VPI

VCI!=5

Mismatch

VPI=X VCI!=5

PAD

PAD

’H’ ’E’ ’L’ ’L’

’H’ ’E’ ’L’ ’L’

’O’

P5

’O’

P5

P8

P9 P10 P11

P8

P9 P10 P11

P6

P7

P6

Copy

P7

...

...

.. Payload ..

.. Payload ..

P44 P45 P46 P47

P44 P45 P46 P47

Copy

JWL:ARL 07/00

• Only process Cells on the selected VCI – All other flows should pass unchanged 5

Field Programmable Port Extender (FPX)

Case 2: Mismatched Source String Compare VPI

VCI=5

VPI=X

Match

VCI=5 PAD

PAD

’M’ ’E’ ’L’ ’L’

’M’ ’E’ ’L’ ’L’

Mismatch+Copy

’O’

P5

’O’

P5

Copy

P8

P9 P10 P11

P8

P9 P10 P11

P6

P7

P6

P7

...

.. Payload ..

.. Payload ..

P44 P45 P46 P47

P44 P45 P46 P47

... Copy

JWL:ARL 07/00

• Cell payload must contain “HELLO” in payload. – “MELLO” ≠ “HELLO” Field Programmable Port Extender (FPX)

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Case 3: Mismatched Source String [word 2] Compare VPI

VCI=5

VPI=X

Match

VCI=5 PAD

PAD

’H’ ’E’ ’L’ ’L’

’H’ ’E’ ’L’ ’L’

Match

’P’

P5

’P’

P5

Mismatch+Copy

P8

P9 P10 P11

P8

P9 P10 P11

P6

P7

P6

P7

...

...

.. Payload ..

.. Payload ..

P44 P45 P46 P47

P44 P45 P46 P47

Copy

JWL:ARL 07/00

• Payload must match over entire string. – Data arrives as streaming words 7

Field Programmable Port Extender (FPX)

Logical Implementation

Append “WORLD” to payload VCI Match

New Cell

Field Programmable Port Extender (FPX)

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Manifest of Files in HelloTestbench.tar •

File: –

•

http://www.arl.wustl.edu/arl/projects/fpx/workshop_0101/HelloTestbench.tar

Contains: – README.txt: – Makefile:

General Information Build and complile programs

– TESTCELL.DAT: – CELLSOUT.DAT:

Cells written into simulation (Hex) Data written out from simulation

– Hex.txt:

HEX/ASCII Table

– fake_NID_in.vhd: – fake_NID_out.vhd:

Utilities to save cells to file Utility to read cells from file

– top.vhd: – helloworld.vhd:

Top level design Top-level helloworld design

– pins.ucf:

Pin mapping for RAD FPGA 9

Field Programmable Port Extender (FPX)

Module Implementation D_MOD_IN[31:0] SOC_MOD_IN

Data Interface

TCA_MOD_OUT

D_MOD_OUT[31:0] SOC_MOD_OUT TCA_MOD_IN

Module Logic

X X

SRAM_GR SRAM_D_IN[35:0]

SDRAM_GR SDRAM_DATA[63:0]

CLK RESET_L ENABLE_L

SRAM Interface

SDRAM Interface

X X

SRAM_REQ SRAM_D_OUT[35:0] SRAM_ADDR[17:0] SRAM_RW

SDRAM_REQ SDRAM_DATA[63:0] SRAM_ADDR[17:0] SRAM_RW

Module Interface

Field Programmable Port Extender (FPX)

READY_L

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Hello, World Entity

RAD

NID

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Field Programmable Port Extender (FPX)

TestBench configuration TESTCELL.DAT top

NID_Out

soc Data tcaff

NID_In

soc Data tcaff

Clk Reset

HelloWorld

CELLSOUT.DAT Field Programmable Port Extender (FPX)

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Contents of TESTCELL.DAT wait__10 new_cell 0000005a 00FFFFFF 48454C4C 4F202020 20202020 20202020 20202020 20202020 20202020 20202020 20202020 20202020 20202020 2020FFFF wait__10

Pause before sending cell Indicate Beginning of cell Cell Header = { VPI[12]:VCI[16]:PT[4] } Cell Header = { HEC[8]:Pad[24] } Payload [ 48 Bytes ]

Pause before sending cell

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Source: Architecture • • • •

-- Hello World: Sample FPX Application -- Operates as Ingress (switch-side) cell processor of RAD -- Copyright: July 2000, John Lockwood, David Lim -- Washington University, Applied Research Lab

architecture Hello_arch of HelloWorld is type state_type is (rst, dout, hell_check, o_check, world); ...

signal state, nx_state : state_type; signal counter, nx_counter : std_logic_vector (3 downto 0); signal CEN, nx_CEN : std_logic; signal BData_Out : std_logic_vector (31 downto 0); signal BData_in : std_logic_vector (31 downto 0); signal BSOC_In : std_logic; signal BTCA_In : std_logic; signal BSOC_Out : std_logic; signal BTCA_Out : std_logic; signal clkin : std_logic; Field Programmable Port Extender (FPX)

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Source: Cell Counter counter_process: process (CEN, counter) begin if CEN = ’0’ then nx_counter 1F US (unit sep) 3F ?

Hx -40 41 42 43 44 45 46 47 48 49 4A 4B 4C 4D 4E 4F 50 51 52 53 54 55 56 57 58 59 5A 5B 5C 5D 5E 5F

Char ---@ A B C D E F G H I J K L M N O P Q R S T U V W X Y Z [ \ ] ^ _

Hx -60 61 62 63 64 65 66 67 68 69 6A 6B 6C 6D 6E 6F 70 71 72 73 74 75 76 77 78 79 7A 7B 7C 7D 7E 7F

Char ---‘ a b c d e f g h i j k l m n o p q r s t u v w x y z { | } ~ DEL

Field Programmable Port Extender (FPX)

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Exercises • Simulate cell on VCI=5 with content: “HELLO” – Process first cell in TESTCELL.DAT

• Simulate cell on VCI=6 with content: “HELLO” • Simulate cell on VCI=5 with content: “MELLO” • Modify the simulation input to inject cell with “YELLOW” (sp) • Modify state machine to search for “YELLOW” Field Programmable Port Extender (FPX)

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Implementation [Homework] • Front-end Synthesis – Map VHDL constructs into LUTs – Tools • FPGA Express (Xilinx Alliance) • Synplicity • More..

• Back-end Tools – Xilinx • Place • Route • Bitgen

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Field Programmable Port Extender (FPX)

FPGA: Design Flow VHDL

VHDL Design

EDIF

Synplicity

BIT

Download Xilinx bit file to FPX FPGA

Xilinx

Timing Logical Simulation

Verification

• Application groups develop RAD module – – – –

Compile of Architecture Synthesize into LUT functions Route and place into CLB Array Verify timing of circuit to 100 MHz

Field Programmable Port Extender (FPX)

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I/O Definitions (Pins.UCF) ## File: rad.ucf ## Backend constraints file for ## RAD FPGA ## Switch (SW) Side Module ## DataIn (Linecard interface, from NID) NET d_sw_nid(0) LOC=B31; NET d_sw_nid(1) LOC=C31; NET d_sw_nid(2) LOC=C32;

## Start of Cell NET soc_sw_rad LOC=D27; NET soc_sw_nid LOC=A32; ## TCA NET tcaff_sw_nid LOC=B26; NET tcaff_sw_rad LOC=D39;

… (see paper) …

## DataOut (Linecard interface, from RAD) NET d_sw_rad(0) LOC=B20; NET d_sw_rad(1) LOC=B21; NET d_sw_rad(2) LOC=E22;

## clock NET rad_clk LOC=AW19; ## Reset NET rad_reset LOC=B30;

… (see paper) ...

Field Programmable Port Extender (FPX)

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Hello, World – Silicon Layout View

Field Programmable Port Extender (FPX)

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FPGA Routing and Placement Detail • Silicon Process – Highly regular Configurable Logic Block (CLB) • Two slices/CLB • Two LUTs/slice

– Dense routing Between modules • GRM • Short lines • Long Lines

• Reprogrammable – SRAM – Pass Transistors Field Programmable Port Extender (FPX)

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Post-Synthesis Signal Timing

– Start_of_cell (SOC): Buffered across Edge flops – data_in : VCI=5, Payload=“HELLOEEO…” – data_out : “HELLO WORLD.” Field Programmable Port Extender (FPX)

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Results: Performance • Operating Frequency: 119 MHz. – 8.4ns critical path • Well within the 10ns period RAD's clock. • Targeted to RAD’s V1000E-FG680-7

• Maximum packet processing rate: – 7.1 Million packets per second. • (100 MHz)/(14 Clocks/Cell) • Circuit handles back-to-back packets

Field Programmable Port Extender (FPX)

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Results: Chip Utilization • Slice utilization: – 1% (49/12,288 slices)

• Details – Edge Flops: • DataIn + DataOut + SOCs + TCAs = 32+32+4 = 68

– Internal Flops : • BufferedData + SOCs + TCAs + state + counter • = 32+4+6=42

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Conclusions • "Hello World” Illustrates: – Example of simple hardware module implemented on the the RAD. – Starting point for new application development.

• FPX provides – Simple and efficient platform to implement certain types of cell and packet processing operations. • Hardware handles 7.1 Million packets/second

– Software Functions: • Should be done on SPC

• Interesting Ideas for Future Work – Hardware/software co-design • Example: Send matching packets to software for processing. Field Programmable Port Extender (FPX)

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“Hello, World” References • FPX Homepage – http://www.arl.wustl.edu/arl/projects/fpx/

• Hello World Handout – John Lockwood, David Lim, "Hello World: A simple application for the Field Programmable Port Extender (FPX), Washington University, Department of Computer Science, Technical Report WUCS-00-12, July 11, 2000.

– http://www.arl.wustl.edu/arl/projects/fpx/references/hello_world_techreport.pdf

• Hello World Testbench – http://www.arl.wustl.edu/arl/projects/fpx/workshop_0101/HelloTestbench.tar

• FPX Tool Environment – http://www.arl.wustl.edu/arl/projects/fpx/workshop_0101/tools.html

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