Substrate coupling evaluation in BiCMOS technology - Semantic Scholar

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IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 32, NO. 4, APRIL 1997

Substrate Coupling Evaluation in BiCMOS Technology Juan M. Casalta, Xavier Aragonès, and Antonio Rubio

Abstract—The magnitude of switching noise coupled through common substrate in BiCMOS technology is analyzed. Noise dependence on collector resistance and buried layer doping of the noisy bipolar junction transistor (BJT) is obtained by means of simulation. It is observed that trends are different depending on bipolar transistor biasing: in common-collector, a low collector resistance is desired, while in common-emitter biasing, large values of RC make the transistor less noisy. A test chip is fabricated in 3-m BiCMOS technology to measure the substrate coupling produced by different BiCMOS inverter gates. These experimental measurements show that noise increases with transistor size and collector resistance. Dependence on distance and speed of signal are also obtained, together with the effect of a guard ring. Index Terms— Crosstalk minimization, noise in BiCMOS circuits, substrate coupling.

I. INTRODUCTION

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HE continuous trend toward miniaturization of circuits and packages carries interaction and switching noise trouble. Transients produced in digital circuits, working at high clock speeds, provoke disturbances that may affect, through the common substrate, sensitive analog parts in mixed-signal circuits. These phenomena have been experienced and simulation results can be found in the literature. A first solution to the problem is the physical partitioning of functions, splitting analog and digital circuits and integrating them in hybrid packages or in multichip modules [1]. Design solutions include noise minimization with guard rings [2], [3], while the use of technologies like silicon-on-insulator (SOI) has also been considered [4]. After adopting these basic measures, other factors must be taken into account, like inductance of package leads [2]. Given that all the work published to the moment deals with CMOS circuitry, the aim of this work is the evaluation of coupling in BiCMOS technologies. BiCMOS technologies are faster than CMOS and provide lower power dissipation than bipolar, with only three or four additional masking levels compared to CMOS technologies. However, even this small increase in process complexity makes BiCMOS designs more expensive than their CMOS counterparts [5], [6]. It is worth knowing whether the noise coupling issue will be an advantage or a disadvantage of BiCMOS. Results have been obtained through simulation and measurements on a test circuit and are compared with coupling evaluated in CMOS technology. Manuscript received November 27, 1995; revised September 25, 1996. This work is supported by the Spanish Research Commission (CICYT), project TIC95-0469 and by the EU ESPRIT Basic Research in the framework of ARCHIMEDES Project. The authors are with the Departament d’Enginyeria Electrònica, Universitat Politècnica de Catalunya, 08034 Barcelona, Spain. Publisher Item Identifier S 0018-9200(97)02474-8.

II. SUBSTRATE COUPLING IN CMOS TECHNOLOGY Coupling in CMOS circuitry is produced when a switching MOS gate induces a substrate voltage disturbance that affects neighboring devices in two ways: first through capacitive coupling, by means of the depletion capacitances associated to source and drain regions, and second through body-effect coupling, as drain current depends on threshold voltage, which in turn is affected by nonzero source-bulk voltage. It can be demonstrated both analytically and by device simulation that the body-effect coupling becomes less important relative to depletion-capacitance coupling as the substrate doping is increased. Crosstalk analysis made with CMOS devices show substrate type to be of major importance on coupling magnitude [2], [3]. Uniform, lightly-doped substrates present important noise peaks, and their magnitude decreases linearly with increasing distance between coupled devices. Heavily-doped substrates with an epitaxial p layer present peaks an order of magnitude smaller if the substrate is well biased (a grounded backplane). Due to the substrate structure, coupling becomes independent of device distance above a certain limit [2], when lateral effects disappear and current flow is produced through the low resistive heavily-doped part of the die. III. SUBSTRATE COUPLING IN BiCMOS TECHNOLOGY Once the characteristics of substrate noise in heavily-doped substrates have been determined, coupling in BiCMOS processes will be analyzed. The study will be restricted to coupling between a bipolar n-p-n transistor and an NMOS device. The study is done through transient analysis with the two-dimensional device simulator MEDICI [7]. This program allows device connection to lumped circuit elements, so it can be used for circuit analysis. A typical structure of two coupled transistors is defined for the simulations, using parameters of a BiCMOS 3- m MIETEC-ALCATEL technology (Fig. 1). It can be observed that the substrate is heavily-doped p-type, with a thin p epitaxial layer on the surface. An n-p-n transistor’s collector is made up of a deep lightly-doped n diffusion, and a conductive (3 /sq.) n buried layer and plug, so that the collector resistance is minimized. The bulk is biased through a backside contact, and its parasitics are modeled with a 10 nH inductance. Given that in this technology we integrate bipolar and fieldeffect transistors, it will be necessary to distinguish between bipolar or MOS device acting as a noise source. A. Common-Emitter Bipolar Transistor as a Noise Source We first analyze the interaction between a bipolar and a MOS transistor when the collector voltage switches from

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Fig. 1. Cross-sectional view of the structure simulated.

high to low level. A typical 1.5-ns low-high transient in the base terminal is applied Fig. 2(a), driving the transistor from off state to saturation. Fluctuations in the substrate voltage will appear due mainly to capacitive coupling through the junction between the n buried layer and the p bulk. These fluctuations affect the NMOS drain voltage [Fig. 2(b)], which is saturated by means of a 1.5 V gate biasing. Given that noise levels depend on the transient duration, the same 1.5 ns rise/fall time was used in the rest of the simulations. Coupled devices are 40 m distant, and a 30 mV peak is measured in the victim MOS drain. An experiment between MOS transistors, using the same technology data and distance between devices, and 0.5 ns rise/fall time at the gate of the disturbing device, has given 2.6 mV peak noise levels, showing the importance of substrate coupling in BiCMOS technologies. Looking again at Fig. 1, it is suspected that the reason for this high noise level is the switching collector being in contact (through the low-resistive plug and buried layer) with the heavily-doped substrate. To confirm this suspicion, we obtain the coupling dependence on the buried layer doping and on the presence of the deep plug, using the circuit in Fig. 3(a). Results represented in Fig. 3(b) show that noise increases both with buried layer doping and with the presence of the plug. The plug helps to decrease the collector resistance and so decrease the transient time at this node, which increases coupling through the depletion capacitance. Increasing buried layer doping not only decreases collector resistance, but increases collector-to-substrate capacitance and noise injection to the substrate. Thus, with common-emitter biasing, a large collector resistance is desired from a noise point of view, which represents a tradeoff with low resistance values required to minimize propagation delay in loaded BiCMOS gates [5]. B. Common-Collector Bipolar Transistor as a Noise Source We next perform a similar analysis, but now the bipolar device is common-collector biased, as shown in Fig. 4(a). The influence of the plug and buried layer is also evaluated, and results are shown in Fig. 4(b). Simulations indicate a considerable noise peak reduction in relation to the common-emitter situation. This is because now the collector contact voltage is fixed, and only the inner part of the transistor is switching. Now the dependence of noise on collector resistance is opposite to that observed in

(a)

(b) Fig. 2. (a) Transition in bipolar base terminal (continuous) and in collector terminal (dashed). External collector resistance Rc is 2 K , and internal rc is 1 K . (b) Drain voltage waveform obtained from the simulator.

the previous section. Crosstalk increases with lower buried layer doping and without the plug: that is, with commoncollector biasing, a small collector resistance is desired from a noise standpoint. Even in circuits like that in Fig. 4(a), with the external collector terminal being tied to a fixed

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(a)

Fig. 5. Coupling comparison between the situations considered.

with the substrate and thus the noisiest one. Then the lowest resistance to the contact is desired to keep the internal voltage as fixed as possible. This is mainly achieved with the plug. Increasing the buried layer doping is also of importance, but its effect is somewhat counterbalanced because of the depletion capacitance increase. (b) Fig. 3. (a) Common-emitter biasing. (b) Peak noise voltage as a function of buried layer doping in a common-emitter bipolar transistor.

(a)

C. NMOS Transistor as a Noise Source The robustness of bipolar transistors in the presence of disturbances will be studied in this section. The noisy device is now a common source NMOS transistor, as we keep on using the substrate structure defined in Fig. 1. Once again we will distinguish between common-emitter and common-collector biasing, now in the sensitive device. Results are shown in Fig. 5, together with data obtained in other sections. In all cases, the epitaxial layer is 4 m deep, with a 9.12E14 cm doping, and the rest of the bulk is 1E18 cm . In a commonemitter configuration, a rising edge in the MOS gate will produce a 5.75 mV peak, and the noise dependence with collector resistance is negligible. In a common-collector setup, crosstalk is even lower (1.65 mV), although it increases slightly with . IV. EXPERIMENTAL RESULTS

(b) Fig. 4. (a) Common-collector biasing. (b) Peak noise voltage as a function of buried layer doping in a common-collector bipolar transistor.

voltage, the distributed resistance of the collector allows some switching in the inner collector, this part being in contact

The analysis performed with the device simulator shows an important substrate coupling when noise is produced by bipolar transistors. A test circuit has been designed to measure the substrate noise produced by a BiCMOS inverter and its dependence with transistors size and collector resistance. The basic inverter designed is shown in Fig. 6 [6], and noise will be measured in the drain terminal of a distant NMOS transistor , biased through a PMOS transistor . Note there are two bipolar transistors in the inverter, one of them common-emitter biased and the other one common-collector. At each transition of the input signal, one of the transistors will switch from off-state to saturation, while the other commutes reversely. In consequence, results obtained will not be directly comparable to that obtained in the previous section. Anyway,


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Fig. 7. Chip photograph of one of the coupled pairs (pair C).

Fig. 6. BiCMOS inverter and sensing transistor.

different kinds of n-p-n transistors will be used in the inverters, so that the influence of collector resistance and transistor size is verified. The circuit has been fabricated in a BiCMOS 3- m technology by MIETEC-ALCATEL. It consists of four inverters like that of Fig. 6 and a sensing device close to each of the inverters. The existence of four sensing transistors will also allow us to measure noise dependence on the distance between coupled devices. The characteristics of the four coupled pairs are next specified. Pair A) The bipolar transistors have minimum emitter area (7 m 7 m) and deep collector contact (plug). Pair B) Equal to pair A, except that there is no deep collector contact (plug). Pair C) Equal to pair A, but now emitter area is ten times larger. Pair D) Equal to pair A, but now the sensing device is surrounded by a p ring, to observe its noise reduction effect. The ring is grounded by means of a dedicated pad A photograph of one of the inverters of the test die is shown in Fig. 7. Measurements are performed by exciting the BiCMOS inverter gate with a square wave of 200 kHz frequency, 50 ns rise/fall time. Transient times at the base terminals of the bipolar transistors will be sensibly faster, though. The IC is not packaged, so that noise waveform is not affected by output pad circuitry. Coupled NMOS drain voltage is sensed with a dynamic 1 M , 1 pF output lead, and nodes are connected to the different voltage sources with static probes. Fig. 8 shows typical input signal and noise waveforms, displayed in a Tektronix DSA at 2 G-samples/s. Averaging over a number of acquisitions is made to eliminate white noise. Probe-to-probe coupling was also a source of trouble, and it has been eliminated with the help of the DSA recording a wave and subtracting the waveform obtained when the input probe is not contacting the corresponding pad. Fig. 9 shows peak-to-peak crosstalk measurements as a function of transition time at the input of the inverter in Pair

Fig. 8. Input square signal and noise voltage waveform measured.

A. It can be seen that noise decreases with increasing rise/fall time, which could also be observed in the simulations. The dependence of noise on distance is shown in Fig. 10, when the disturbing inverter is that of Pair C (large transistors), and noise is measured in each of the four sensing devices in the chip. We can see that the dependence is small (note the large range of distances considered), which is typical of heavily-doped substrates, as mentioned in Section II. Crosstalk peaks measured in each pair are compared in Fig. 11. It can be observed that transistors in Pair C, whose area is larger than that of the other types, are the noisiest ones. This could be predicted from the suspicion of the importance of the collector buried layer in direct contact with the substrate; that is, larger collector areas imply more coupling. Since variation of the buried layer doping has not been possible, the only way we have to check the influence of the collector resistance is to observe the effect of the deep collector contact. In Section III we saw that its absence influenced mainly in a common-collector transistor, resulting in more coupling. This is checked in the measurements, as noise produced by the

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Fig. 9. Measured noise as a function of rise/fall time of the input square signal.

Fig. 10.

Measured noise as a function of BiCMOS inverter to sensing device distance.

inverter without the plug is larger than noise when the plug is present. Finally, the inclusion of a grounded guard ring reduces noise by 30%. This improvement may seem small, but we must take into account that substrate is heavily-doped, and in these cases the effect of rings is reduced [2]. V. CONCLUSION In this article we have analyzed the magnitude and importance of noise coupled through the common substrate in BiCMOS technologies. Analyses performed with a device simulator show bipolar transistors to be much noisier than MOS ones, assuming equal technological characteristics. Coupling is mainly originated by switching at the collector; thus commonemitter biased transistors are noisier than common-collector

biased ones. The importance of collector resistance for each type of biasing has also been determined. For transistors in common-collector configurations, collector resistance should be as low as possible. In common-emitter configurations, large values for this resistance are desired, although this reduces the device speed. Collector doping is also of importance, due to its direct relation with the depletion capacitance of the collectorsubstrate junction. On the other hand, bipolar devices are insensitive to disturbances, particularly in common-collector configurations. A test circuit has been carried out with a 3- m BiCMOS technology to measure the noise produced by inverters implemented with different types of transistors. Measurement results show the increase of noise with the speed of the disturbing


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the simulations has also been seen experimentally. Finally, the noise-reducing effect of a grounded p guard ring has been verified. REFERENCES

Fig. 11.

Measured coupling for the different coupled pairs.

signal transitions and the slight decrease with separation between coupled devices. The importance of the collector area has also been observed, as the largest transistors are the noisiest ones. The effect of the collector resistance obtained in

[1] B. M. J. Kup, E. C. Dijkmans, P. J. A. Naus, and J. Sneep, “A bit-stream digital-to-analog converter with 18-b resolution,” IEEE J. Solid-State Circuits, vol. 26, pp. 1757–1763, Dec. 1991. [2] D. K. Su, M. J. Loinaz, S. Masui, and B. A. Wooley, “Experimental results and modeling techniques for substrate noise in mixed-signal integrated circuits,” IEEE J. Solid-State Circuits, vol. 28, pp. 420–430, Apr. 1993. [3] B. R. Stanisic, N. K. Verghese, R. A. Rutenbar, L. R. Carley, and D. J. Allstot, “Addressing substrate coupling in mixed-mode IC’s: Simulation and power distribution synthesis,” IEEE J. Solid-State Circuits, vol. 29, pp. 226–238, Mar. 1994. [4] K. Joardar, “A simple approach to modeling cross-talk in integrated circuits,” IEEE J. Solid-State Circuits, vol. 29, pp. 1212–1219, Oct. 1994. [5] A. R. Alvarez, J. Teplik, R. A. Maken, R. Lahri, K. Deirling, C. Hochstedler, and H. S. Lee, BiCMOS Technology and Applications. Norwell, MA: Kluwer, 3rd printing, 1990. [6] M. I. Elmasry, VLSI BiCMOS Digital Circuit Design, Session 3: BiCMOS design I, Barcelona, Mar. 1994. [7] TMA MEDICI: Two-Dimensional Device Simulation Program. Version 1.1, Technology Modeling Associates Inc., Mar. 1993.