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Synchronous Mirror Delay for Multiphase Locking Yong Jin Yoon, Hyuck In Kwon, Jong Duk Lee, Member, IEEE, Byung Gook Park, Member, IEEE, Nam Seog Kim, Uk Rae Cho, and Hyun Guen Byun
Abstract—A clock generation circuit having the function of multiphase locking was designed using the synchronous mirror delay (SMD) scheme. The internal clock can be synchronized to the external clock with intended phase difference. The synchronizing error of the clock generation circuit is reduced below the delay time of unit delay stage by compensation characteristics of detecting circuit in SMD. A 32-M double data rate (DDR) SRAM including the clock generation circuit is fabricated using 0.13- m CMOS technology. To measure the synchronizing error of the clock generation circuit, the test elements group (TEG) system is designed and fabricated with the main system. The synchronizing error of the clock generation circuit is far smaller than the delay time of unit delay stage at zero phase locking and similar to the delay time of unit delay stage at multiphase locking. Index Terms—Clock, multiphase, SRAM, synchronous mirror delay.
I. INTRODUCTION
F
OR THE CASE of a general synchronous system, the amplitude and the shape of the external clock signal are not applicable to the internal circuits, for which a clock receiver must be used. A high-speed synchronous system with a few pipelines like synchronous static random access memory (SRAM) is influenced by the delay time of the receiver and its variation. To remove the influence originated from the timing difference between external clock and internal clock, many synchronous clock generation circuits in which internal signal synchronizes with external signal using the normality of clock are developed [1]–[11]. In the application of double data rate (DDR) SRAM, two types of synchronized clocks are needed to improve setup/hold characteristics of DDR inputs. One has the phase difference of 0 against the external clock and the other has the phase difference of 90 against the external clock. The basic concept of the clock generator in which the internal clock can be synchronized to the external clock with intended phase difference was suggested in our previous work [12]. In this paper, the structure of a synchronous mirror delay (SMD) was modified for the application of DDR SRAM and an overall clock generation circuit including the SMD was designed as a part of 32-M DDR SRAM. The test elements group (TEG) pattern was designed to measure the resolution of the SMD. All circuits are designed and fabricated using 0.13- m CMOS process. The operation of the clock generation circuit is verified Manuscript received December 5, 2002; revised July 30, 2003. Y. J. Yoon, N. S. Kim, U. R. Cho, and H. G. Byun are with the Device Solution Network, Samsung Electronics, Gyeonggi-do 445-701, Korea (e-mail:
[email protected]). H. I. Kwon, J. D. Lee, and B. G. Park are with the School of Electrical Engineering and Computer Science, Seoul National University, Seoul 151-742, Korea. Digital Object Identifier 10.1109/JSSC.2003.820871
Fig. 1. Concept of multiphase locking. The unit delay has two inputs for symmetry between the forward delay chain and the backward delay chain. One input of the unit delay in the forward delay chain is not active. It is connected to dc supply.
by electron beam (e-beam) probing. The synchronizing error is estimated by the setup/hold characteristics of 32-M DDR SRAM and calculated from the measured data of TEG. II. CONCEPT OF MULTIPHASE LOCKING According to the specification of DDR SRAM, two modes of input operation must be supported. One is the clock-centered (CC) mode and the other is the clock-aligned (CA) mode. In CA mode, the margin of input setup/hold is maximized when the internal clock is synchronized at the center of the rising edge and falling edge (or the center of the falling edge and rising edge) of the external clock because the input DATA is aligned to the clock. It means that the synchronized internal clock has phase difference of 90 with external clock. Due to the same reason, the internal clock is synchronized at the rising edge or the falling edge in CC mode. In an SMD scheme, to make phase is needed difference , an added delay corresponding to in both forward and reverse delay chain. But it is impossible to find the exact number of unit delay stages corresponding to because the time corresponding to is varied with operation frequency and the delay time of the unit delay stage is varied with operating condition and device characteristics. A new concept to solve this problem is suggested in Fig. 1. Two sets of SMD are needed because the input signal of the SMD for multiphase locking in Fig. 1 is the internal clock synchronized to external clock with no phase difference. This signal is generated from other SMD and used as the sampling clock in CC mode.
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TABLE I ADDITIONAL DELAY TIME CORRESPONDING TO THE INSERTING RATIO ( )
m
Let the delay time of unit delay stage be and the number of unit delay stages corresponding to clock period be : (1)
Fig. 2. Schematic diagram of the detecting circuit. This circuit is activated when signal IN transits to low while signal REF is low. The voltage of node A is related to the time difference between signal IN and signal REF.
Assume that one unit delay stage is inserted in the reference signal path per unit delay stages in the forward delay chain, where is the inserting ratio. The unit delay stages inserted in the reference signal path increase the number of unit delay stages in the forward delay chain for locking. Let the number of increased unit delay stages in forward delay chain be . Additional delay time in the reference signal path is expressed by (2) and that of forward delay chain is expressed by (3). They must be the same at locking position. (2) (3) (4) (1) and (4) result in (5) Additional delay time in the forward delay chain becomes the ratio of clock period. Because the same delay time is added to the backward delay chain, the total additional delay time in the SMD becomes twice the additional delay time expressed by (5). As a result, the output of the backward delay chain is from input. If the input is generated after synchronized to the external clock, the output is synchronized to . Several the external clock with phase difference values of phase difference are arranged in Table I. In CA mode (equal to 90 ) operation, the needed phase difference is . and it can be obtained at III. DESIGN OF NEW DETECTING CIRCUIT The function of the detecting circuit in an SMD is a timing comparator. The detecting circuit generates output when two input signals are inputted at the same time. The detecting circuit composed of general combinational logic may have timing error corresponding to the pulsewidth of signal. In SMD scheme, one of the input signals always advances another signal until locking timing. Using this condition a new simple detecting circuit independent of pulsewidth is designed. The schematic diagram of
Fig. 3. Timing diagram of the detecting circuit. It has compensation characteristics of synchronizing error of the SMD due to discrete unit delay is related to the voltage time. The response time of the detecting circuit, of node A which is related to the time difference of two inputs (IN and REF), . So gets shorter as gets longer and gets longer as gets and becomes constant by size optimization shorter. The summation of of the transistor M1. (a) Disable timing. (b) Enable timing 1 for short . . (c) Enable timing 2 for long
t
t
t
t
t
t
t t
t
t
the detecting circuit is shown in Fig. 2 and the timing diagram of the detecting circuit is shown in Fig. 3. When the output of the forward delay unit (IN) goes to transition in advance of the clock (REF), the output of detecting circuit (OUT) is not changed because the precharged node A is discharged and the transistor M1 is turned off. In the opposite case, the detecting circuit generates the output signal from the output of the forward delay unit. The signal REF is fixed on the time domain and the signal IN is varied. If the signal IN locates before the signal REF, the signal OUT is not changed, as shown in Fig. 3(a). As the number of unit delay stage in the forward delay chain is increasing, the signal IN locates after the signal REF and the signal OUT transits to low, as shown in Fig. 3(b) and (c). Because the signal IN is
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TABLE II LOCKING CHARACTERISTICS OF THE CLOCK GENERATOR
delay time of the unit delay circuit in the SMD, which means the synchronizing error can be reduced to 10% of the delay time of the unit delay circuit.
Fig. 4. Simulated compensation characteristics of the detecting circuit. The open circles stand for the response time of the detecting circuit (t in Fig. 3(b) and (c)). The solid circles show the total delay time from reference signal expressed in (7). The value of the x axis is the timing difference (t in Fig. 3(b)) in locking position due to discrete delay time of delay chain of SMD. The average value of solid circles can be compensated by emulation circuit. So the synchronizing error of SMD is equal to the amplitude of solid circle.
varied with discrete delay time (the number of unit delay stages delay time of unit delay stage), the time difference between the signal IN and the signal REF may increase up to the delay time of unit delay stage at the locking position. This difference is the major factor in causing synchronizing errors in an SMD. The new detecting circuit can reduce this difference under the delay time of the unit delay stage. The total delay of the SMD becomes (6) From (6), the synchronizing error of SMD is expressed as (7) In Fig. 2, node A is partially discharged at the condition of Fig. 3(b) because the time difference between two input signals is similar to the falling time of input signals. As the time differgets larger, the voltage of node A gets higher and the ence gets shorter. Thereresponse time of the detecting circuit fore, the synchronizing error expressed in (7) becomes nearly constant. The size of transistor M1 is optimized to minimize the and . The emulation cirvariation of the summation of cuit having delay time equal to the average of the summation and is inserted in front of the forward delay chain. of and is comBecause the average of the summation of pensated by the emulation circuit, the synchronizing error of the and SMD is reduced to the variation of the summation of . HSPICE simulation data of the new detecting circuit is shown in Fig. 4. The synchronizing error expressed in (7) is less . It is equal to 20% of the than 6 ps for all time difference
IV. DESIGN OF OVERALL CLOCK GENERATOR The overall clock generator, which consists of the SMD, clock receiver, emulation circuits, clock driver, selector, and other additional circuits, is designed using 0.13- m CMOS device. The block diagram of the clock generator is shown in Fig. 5. Two types of unit delay circuit are used in the SMD to obtain a wide locking range of the clock generator with a limited number of unit delays. At high-speed operation above 300 MHz, only the unit delay stage having minimum delay time (type I) is operated in the SMD. At low-speed operation, about 100–300 MHz, the unit delay stage having more delay time (type II) is also used with type I in the SMD. The output of the detecting circuit is connected to the disable port of the next unit delay stages. Therefore, all delay units behind the locking position do not operate to reduce power consumption in delay chain. The layout of the clock generator is shown in Fig. 6. The size of the clock generator is about 1600 m 200 m. The characteristics of the overall clock generator are calculated by simulation utilizing the HSPICE with 0.13- m MOSFET model parameter developed by Samsung Electronics. The simulation results obtained under several operation conditions are summarized in Table II. Because the input signals of the clock receiver have no relation to the supply voltage of the clock generator, the emulation circuit of the receiver cannot completely compensate the varied delay time of the receiver with operating condition. So the synchronizing error of the overall clock generator is larger than that of the SMD. The clock generator has 17-ps synchronizing error at 0 of locking phase difference and has 40-ps synchronizing error at 90 of locking phase difference. The synchronizing error at 90 of locking phase difference is theoretically larger than that in 0 locking because the synchronizing error from the delay time of unit delay in the reference signal path is not compensated and added to the synchronizing error of the internal clock signal at 0 of locking phase difference. But it is small enough to satisfy the sample-and-hold margin of the data signal in DDR specifications of an SRAM.
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Fig. 5. Block diagram of the overall clock generator. The external clock is differential signal. The Clock for Address is aligned to the cross point of external clock. The Clock for Data is aligned to the cross point of external clock in CC mode and phase-shifted by 90 from the cross point of external clock in CA mode. The variable delay circuit makes the phase shift of internal clock through JTAG. The Clock for Data and the Clock for Address are phase shifted 7 steps by the 4-bit code from JTAG. Amount of the shifted phase equivalent to one step is about 15 ps.
6
Fig. 6. Layout drawing of the overall clock generator. The left part is the delay chain for 90 shifted locking and the right part is that for 0 locking. The number of unit delay stages in the forward delay chain of the SMD at the left part is 153. The upper limit of locking range of SMD for 90 shifted locking is about 9 ns.
V. MEASUREMENT A 32-M DDR SRAM including the clock generation circuit was fabricated using a 0.13- m CMOS process. The waveforms of the internal clock for zero phase locking and multiphase locking were measured using e-beam probing. The operating frequency is set to 250 MHz, which is the upper limit of the equipment. In Fig. 7, the address sampling clock is aligned to the cross point of the external clock and the data sampling clock is phase shifted by about 90 . Fig. 7 shows that the clock generator operates correctly in CA mode. The jitter of the overall clock generator can be estimated from the setup/hold windows of the main memory system. The setup/hold windows measured in the main memory system include the skew between input pins, the accuracy of the tester, and the mismatch characteristics of receivers. Other setup/hold windows are measured using a fixed delayed clock to eliminate the jitter due to the parts skew between input pins, accuracy of the tester, and the mismatch characteristics of receivers. The setup/hold windows at both conditions are shown in Fig. 8. Assuming that the skew between input pins, accuracy of the tester, and the mismatch characteristics of receivers are fixed
Fig. 7. Measured internal clock signals generated from the SMD. The waveform is measured by E-beam probe. The waveforms of K and KB are external clocks. The waveforms of KACB and KAC2B are the internal clocks at zero phase shifted locking and they are equal to the signal Clock for Address in Fig. 5. The waveforms of KDI1B and KDI2B are the internal clocks at 90 shifted locking and they are equal to the signal Clock for Data in Fig. 5.
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Fig. 9. Setup/hold windows versus the cycle time of the clock. This data is not processed by the compensation method mentioned in Fig. 8. The measuring resolution of the tester is 30 ps. The setup/hold windows are independent of the cycle time of the clock.
Fig. 8. Setup/hold windows of the overall clock generator. The solid circles are the setup/hold windows measured when the sampling clock is generated from the clock generator including the SMD. The solid rectangles are the setup/hold windows measured when the sampling clock has the fixed delay from external clock. Assuming that the skew between input pins, the accuracy of the tester and the mismatch characteristics of receivers are fixed parameters and have no distribution, the setup/hold windows due to the clock generator is calculated by subtracting the value of solid rectangles from the value of solid circles. The circles stand for the calculated setup/hold windows due to the overall clock generator. The data are measured at (a) 80 C and (b) 5 C.
0
parameters and have no distribution, the setup/hold windows due to the clock generator are calculated by subtraction. As the setup/hold windows are measured at 10 times (equivalent to in normal Gaussian distribution), the standard deviation of jitter of the clock generator becomes about 10 ps. The setup/hold windows are independent of cycle time. This means that the synchronizing error of the SMD is independent of the number of unit delays operated in the SMD. The setup/hold windows versus cycle time are described in Fig. 9. To measure the synchronizing error (variation of locking position) of the clock generation circuit, the TEG system was designed and fabricated. The block diagram of the TEG system is shown in Fig. 10. The frequency of the internal voltage-controlled oscillator (VCO) is controlled by the external reference voltage and its frequency range is from 300 is used as to 800 MHz. The output of internal VCO the input signal of the clock generator and the reference signal of the comparator. The output of the clock generator is inputted to the comparator through a multiplexer (MUX). The comparator makes the pulse whose width corresponds to
K
Fig. 10. Block diagram of the TEG. is the signal generated from VCO, is the output signal from SMD and the [0:1] are reference signals to is synchronized to compensate the offset of comparator and integrator. the by an SMD. The inputs of the comparator are selected by external code.
K
K
K
K
the timing difference between reference signal and . Using this pulse, the MOS transistor locked signal connected to current source is switched. The precharged output of comparator is discharged by the switched current of the MOS transistor for several cycles. The timing offset of pulse generator in the comparator and the loading effect of the integrator output are eliminated using other VCO output signals (K[0:1]), which have known timing differences from the reference signal. This process is shown in Figs. 11 and 12. Using the MUX output at code 00 and code 01, the relation of the time difference versus voltage level of integrator output (OUT) is calculated. The timing difference between reference and locked signal is measured at code 11. signal The synchronizing error of the clock generation circuit is calculated by the linear interpolation method. To eliminate the variation of output loading of the integrator from the output voltage level, a large external capacitor is used at the output of the integrator. At code XX, the output of the integrator is always dis-
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time of a clock. The ratio of time value for code 11 and time value for code XX must be to a quarter in 90 shifted locking. Twenty samples of the TEG system were measured in various operating conditions to obtain the synchronizing error of the clock generator. At the condition of 1.2 V and room temperature, the synchronizing error is measured to be about 10 ps in zero phase locking and 40 ps in multiphase locking. The center point of locking position (average time value of internal clock) is measured under the same condition and resulted in about 25 ps in zero phase locking and 0.28 clock cycle in multiphase locking. The mismatch of the center point is due to the mismatch of metal loading in emulation circuits. But the center of the synchronizing point can be controlled by external code or metal option in the main system. Fig. 11. Waveform of the comparator output at zero phase locking. The codes stand for the input status of the comparator. They are shown in Table III.
Fig. 12. Waveform of the comparator output at 90 shifted locking. The codes stand for the input status of the comparator. They are shown in Table III. TABLE III INPUT STATUS OF THE COMPARATOR DECIDED BY THE CODES
VI. CONCLUSION By using the SMD scheme, the clock generation circuit of DDR SRAM to synchronize the internal clock to the external clock is designed. Two types of internal clock are synchronized to the external clock signal with the phase difference 0 and 90 to satisfy the DDR specifications. A new detecting circuit is designed to reduce the synchronizing error of SMD, the so-called jitter. The synchronizing error of the SMD is reduced to 15% of the delay time of the unit delay circuit. The overall clock generator operates successfully and it is confirmed by e-beam probing, as shown in Fig. 7. The jitter of the overall clock generator is estimated from the setup/hold windows of the main memory system. The skew between input pins, the accuracy of the tester, and the mismatch characteristics of receivers compensated by the setup/hold windows are measured using fixed delayed clock. The setup/hold windows are measured for all address (10 cells) and DATA (36 I/O). The standard deviation of jitter of the clock generator is about 10 ps after the compensation mentioned above. Also, the jitter of the SMD is independent of the number of unit delays operated in the SMD. The synchronizing error (variation of locking position) of the clock generation circuit is calculated from the measured result of the TEG system. At the condition of 1.2 V and room temperature, the synchronizing error is measured to be about 10 ps in zero phase locking and 40 ps in multiphase locking. The center point of locking position (average time value of internal clock) differs from the designed value due to the mismatch of metal loading in emulation circuits. The mismatch of center point is about 25–40 ps and it can be corrected by external code (JTAG) in the main system. REFERENCES
*The delay time of t stands for the delay time of one buffer (two inverters) and the delay time of t2 stands for the delay time of two buffers (four inverters). These values are measured using another ring oscillator.
charged, as shown in Fig. 12. This means that the time value corresponding to the output value for code XX is equal to the cycle
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Yong Jin Yoon was born in Seoul, Korea, in 1964. He received the B.S. and M.S. degrees in electrical engineering from Seoul National University in 1987 and 1989, respectively. Since 1998, he has been working toward the Ph.D. degree at the same university. In 1989, he joined the Device Solution Network Division, Samsung Electronics Company, Korea, where he is currently a Member of Technical Staff of the SRAM Development Team. His current research interest is high-speed synchronous SRAM.
Hyuck In Kwon was born in Seoul, Korea, in 1976. He received the B.S. and M.S. degrees in electrical engineering from Seoul National University in 1999 and 2001, respectively. Since 2001, he has been working toward the Ph.D. degree at the same university. His current research interests are CMOS active pixel image sensors and VLSI system design.
Jong Duk Lee (M’79) was born in Youngchun, Kyungpook, Korea, on January 10, 1944. He received the B.S. degree in physics from Seoul National University in 1966 and the Ph.D. degree in physics from the University of North Carolina at Chapel Hill in 1975. He was an Assistant Professor in the Department of Electronics Engineering at Kyungpook National University from 1975 to 1978. In 1978, he studied microelectric technology at HP-ICL, Palo Alto, CA, and later worked for the Korea Institute of Electronic Technology (KIET) as the Director of the Semiconductor Division. In July 1983, he moved to the Department of Electronics Engineering, Seoul National University, which merged with the School of Electrical Engineering in 1992, where he is now a Professor. Dr. Lee was the member of the steering committee for IVMC from 1997 to 2001 and KCS from 1998 to 2008. He was also the member of IEDM Subcommittee on Detectors, Sensors and Displays of the IEEE Electron Devices Society from 1998 to 1999.
Byung Gook Park (M’96) received the B.S. and M.S. degrees in electronics engineering from Seoul National University, Seoul, Korea, in 1982 and 1984, respectively, and the Ph.D. degree in electrical engineering from Stanford University, Stanford, CA, in 1990. From 1990 to 1993, he was with AT&T Bell Laboratories, Murray Hill, NJ, where he contributed to the development of 0.1-m CMOS and its characterization. From 1993 to 1994, he was with Texas Instruments, Dallas, TX, developing 0.25-m CMOS. In 1994, he joined the School of Electrical Engineering, Seoul National University, as an Assistant Professor, and he is currently an Associate Professor. His current research interests are nano-scale CMOS devices, Si single-electron devices, organic electroluminescent display, and scanning probe microscopy system. Dr. Park was a member of the International Electron Devices Meeting (IEDM) Subcommittee on Solid State Devices of the IEEE Electron Devices Society from 2001 to 2002.
Nam Seog Kim was born in Seoul, Korea, in 1974. He received the B.S. degree in electrical engineering from Korea University, Seoul, Korea, in 1997 and the M.S. degree in electrical engineering from Seoul National University, Seoul, in 1999. Since 1999, he has been a Member of Technical Staff with Samsung Electronics, Korea, where he is working on SRAM design and high-speed I/O. His research interests include low-power and high-performance circuits, clock recovery circuits, and highspeed link design.
Uk Rae Cho was born in Sang-ju, Korea, in 1962. He received the B.S. degree in electronic engineering from Kyungpook National University, Taegu, Korea, in 1985. In 1984, he joined the Digital Solution Network Division, Samsung Electronics Company, Korea, where he is currently a Project Leader of the SRAM Development Team. He holds eight international patents, with 18 patents pending. His research interests include core circuits of ultrahigh-speed SRAM, high-bandwidth interface design, design for test, device modeling, and analysis of BGA package substrate.
Hyun Geun Byun was born in Kyungpook, Korea, on October 17, 1957. He received the B.S. degree in electronic engineering from Kyungpook National University, Taegu, Korea, in 1983. He joined the Memory Development Division, Samsung Electronics Company, Korea, in 1983, where he has been engaged in the development of low-power and high-speed SRAM.
