Teaching Digital HW-Design by Implementing a ... - Semantic Scholar

Teaching Digital HW-Design by Implementing a Complete MP3 Decoder Hugo Hedberg, Thomas Lenart, Henrik Svensson, Peter Nilsson, and Viktor Öwall Department of Electroscience, Lund University Box 118, SE-221 00 Lund, Sweden Email: {hhg, tlt, hsn, peter, vikt}@es.lth.se Abstract This paper describes a project course that focuses on all the different stages in an ASIC design flow. The project starts at algorithm level, followed by architecture selection, netlist generation, down to physical layout, fabrication, and finally verification. The scope of the project, implementing a complete MP3 decoder in VHDL and sending it for fabrication, motivates the students to work hard towards a common goal.

1. Introduction Courses on master’s level rarely reflect the problems professional engineers meet in their daily work. Time and other resources tend to limit the focus to well-defined problems, which are thoroughly taught in lectures, labs and assignments. However, designing efficient hardware requires knowledge from a wide area of subjects, all taught in different courses. The fourth year project course IC Project and Verification, presented in this paper, aims at letting the students apply knowledge obtained in previous courses and giving them an overall picture of HDL-based hardware design. In the following sections we will describe the project course, preceding courses, supervision, motivation stimulus, and the knowledge we envision the students to acquire.

2. Course objectives To ensure an adequate knowledge base, a prerequisite for the students is the course Digital IC Design. In this course, basic CMOS technologies and designs are taught together with some basic knowledge of commonly used automation tools. Additional knowledge can be gained in other courses given by the department, e.g. DSP-design and System-on-Chip, which are included in the Socware program [1]. DSP-Design teaches various designs strategies, such as pipelining and parallelism. System-onChip deals with fabrication issues, like effects of substrate noise and trends in modern IC technology. During the project, students should realize the necessity of a design flow and its advantages compared to an intuitive ad-hoc design approach. The students, supported by the design flow and the supervision, will obtain knowledge in the areas of:

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Design and analysis of algorithms Simulation and debugging of HDL code CAD tools for synthesis and place & route System integration FPGA prototyping

3. Course outline The course aims at developing the skills of the students as hardware designers. The eight-week full-time course covers one semester and gives an opportunity not only to practise and confirm existing knowledge, but also emphasises the HDL-based design perspective. This is achieved by letting the students use modern hardware design methodologies and various automation tools. Furthermore, the project assignment has been carefully chosen to contain and illustrate many important hardware design issues, e.g. the trade-off between area, speed, and power consumption.

3.1. Design flow The course covers the whole design process from specification to implementation and documentation. A brief overview of the design flow and design automation tools used throughout the course can be seen in Figure 1. The students should document their work on all levels in the design flow, meaning that they should reflect upon the design strategy and trade-offs they have made throughout the design process.

4. Project description The course starts with an introductory lecture where the students are given an overview of the MP3 decoding process. The project is divided into several smaller Specification Algorithm Modelsim Architecture Netlist

Synopsys DC Layout

Silicon Ensemble

Figure 1. Design flow. Grey indicates material supplied to the students.

Proceedings of the 2003 IEEE International Conference on Microelectronic Systems Education (MSE’03) 0-7695-1973-3/03 $17.00 © 2003 IEEE

assignments, or sub-blocks. The implementation work is carried out in groups of two students. Each group has a dedicated supervisor to answer questions about the project and to discuss design methodologies, as well as implementation aspects. Supervisors keep regular contact to monitor the progress of each group. In order to have redundancy and to create a competitive atmosphere, more than one group should implement the same sub-block, of which only one is included in the design sent for fabrication.

4.1. Implementation The implementation phase of the project course starts with an initial assignment to implement one of the minor stages of the MP3 decoder, alias reduction, using VHDL. All groups implement the assignment independently during two weeks, ending with a comparison of the synthesis results. Students should realize the importance of thinking in terms of hardware when using a hardware description language, e.g. the balance between the execution time and the required hardware resources. This is essential in a MP3 decoder, where some parts require a high throughput while other parts should use resource sharing to minimize the required area. Figure 2 illustrates the variations in synthesis result due to different design approaches in terms of speed and area. By giving this feedback to the students, they realize the necessity of a design methodology for the rest of the project. After the initial project, the students continue with a larger assignment. The MP3 decoding process is divided into several parts, which can be implemented and verified independently, partitioned as in Figure 3. A VHDL framework has been developed for the course, simplifying the implementation by defining the interfaces between the blocks. The students are also provided with: ƒ A reference model in C-code and project manuals ƒ Testbench framework and input stimuli ƒ Manuals and scripts for the CAD tools 4

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Group 1 Group 2 Group 3 Group 4 Group 5 Group 6 Group 7 Group 8

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Synchronizer

Huffman Decoder

Requantizer

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IMDCT

Alias Reduction

Stereo Decoding

Figure 3. The MP3 decoding process. The grey box is provided.

Course related material is available on the course homepage [2]. It also contains a contact list for students and supervisors and frequently asked questions to minimize the supervision overhead. By putting all questions and suggestions on the web, future versions of the project course can be improved.

4.2. Motivation The students have 24-hour access to a lab with 16 workstations, dedicated for the project course. They work with commonly used CAD tools, which means that the gained knowledge is directly applicable at most companies developing digital hardware. FPGA platforms are also available for rapid prototyping. Both formal and informal meetings with the supervisors are crucial to motivate and guide the students. Reviews of code and documentation, at the end of each design phase, provide important feedback to the students and the supervisors [3]. To improve the students writing skills, the documentation should be written as a scientific article. The students know from the start that only one set of sub-blocks for the MP3 decoder will be put together and sent for fabrication in a 0.35µm CMOS technology. This increases the ambition in the groups to find the most suitable implementation of the functionality according to the specification. However, all groups will verify their design on the FPGA platform together with the rest of the MP3 decoder. We believe it is important to show the students that their work can be executed on a real hardware platform, and not only inside a simulation environment.

5. Conclusion In this projects course, a larger hardware project is used as a case study to illustrate all the different design aspects in hardware implementation. By working together to reach a common goal, the students are motivated to put more effort into their work. The students go through all the different stages in the design flow, including fabrication, to get the overall picture of systematic hardware design methodologies.

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Figure 2. Variations in synthesis results. For the initial assignment, the students have not been given any specific hardware constraints.

[1] [2] [3]

Peter Nilsson et.al., “Socware: A New Swedish Design Cluster for System-on-Chip”, Proc. of MSE, June, 2001 http://www.es.lth.se/edu/education.html David L. Parnas, “Education for Computing Professionals”, IEEE - Computer, January, 1990

Proceedings of the 2003 IEEE International Conference on Microelectronic Systems Education (MSE’03) 0-7695-1973-3/03 $17.00 © 2003 IEEE